CN102683423A - Metal oxide thin film transistor with top gate structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a top gate structure metal oxide thin film transistor and a manufacturing method thereof, wherein the thin film transistor comprises a substrate, an active layer, an insulating layer, a gate, a source electrode and a drain electrode, the active layer is arranged on the substrate, the source electrode is arranged at one end of the upper side of the active layer, the drain electrode is arranged at the other end of the upper side of the active layer, the insulating layer is arranged in the middle of the upper side of the active layer, and the gate is arranged on the insulating layer; a metallization layer is arranged between the active layer and the source electrode, and a metallization layer is also arranged between the active layer and the drain electrode; the active layer is of a composite film layer structure and sequentially comprises an oxygen-deficient metal oxide film layer and an oxygen-enriched metal oxide film layer from bottom to top. The active layer is made into a composite film layer by the same material and different processes, and the contact resistance is reduced by a metallization method at a source/drain electrode contact area; and an optimized sputtering process is adopted to manufacture the insulating layer, so that the plasma is prevented from damaging the active layer of the channel. And annealing to obtain the high-performance top gate structure metal oxide thin film transistor.

Description

Metal oxide thin film transistor with top gate structure and manufacturing method thereof

technical field

The invention relates to a thin film transistor, in particular to a metal oxide thin film transistor with a top gate structure and a manufacturing method thereof.

Background technique

Metal oxide thin film transistors are mainly used for organic light-emitting displays, liquid crystal displays, and active drives for electronic paper, and can also be used for integrated circuits.

In recent years, thin film transistors based on metal oxides have attracted more and more attention because of their advantages such as high mobility, good light transmission, stable film structure, low fabrication temperature, and low cost. In particular, the oxide semiconductor TFT technology represented by In-Ga-Zn-O (IGZO) can achieve higher resolution compared to a-Si TFT, and can improve yield, reduce cost and reduce costs compared to LTPS TFT technology. Realize energy saving; generally speaking, IGZO TFT technology has superior comprehensive performance and has made many breakthroughs.

At present, although the development of IGZO technology has made great progress, there are still problems such as stability and uniformity, which hinder its industrialization process. Many research groups in industry and academia have conducted research on IGZO film preparation technology, such as: Takafumi Aoi et al. (Thin Solid Films, 2010, 518(11): 3004-3007) and Dong Kyu Seo et al. , 59:6743-6750) reported that different coating methods (DC or RF) were used to prepare IZGO films; Hai Q.Chiang et al. Thin Solid Films 2009,517(14):4078–4081) and C.J.Chiu et al. (Vacuum,2011,86(3):246-249) respectively studied the coating parameters from the sputtering pressure, oxygen partial pressure, power, etc. IGZO preparation technology; the South China University of Technology group specifically aimed at the bottom gate structure, and proposed the technology of using transition layer and semiconductor layer to improve the characteristics of oxide TFT (application number: 201010182715.5). There are also research groups reporting improved processing techniques after active layer preparation, for example: Seok-Jun Seo et al. (Electrochemical and Solid-State Letters, 2010,13(10):H357-H359), Soyeon Park et al. (Journal of Nanoscience and Nanotechnology, 2011, 11:6029-6033) and Chur-Shyang Fuh et al. (Thin Solid Films, 2011, 520(5): 1489-1494) by changing the temperature, atmosphere, time and other annealing conditions to IGZO-TFT Performance optimization and improvement. In addition, the preparation of the channel protective layer and the optimization of materials are also very critical. Antonis Olziersky et al. (Journal of Applied Physics, 2010, 108, 064505) and Shou-En Liu et al. (IEEE Electron Device Letters, 2011, 32 :161-163) by studying the fabrication method and material type of the channel passivation layer.

Most of the research on IGZO oxide semiconductor TFT is based on devices with bottom gate structure. In this structure, since the active layer is located above the gate electrode and the insulating layer, it is difficult to improve the process of IGZO alone without affecting other film layers. However, the preparation technology of top-gate structure TFT is relatively high, and only a few enterprises or research groups are adopting it. For this structure, the semiconductor active layer is in the first layer, and the IGZO process can be optimized independently without affecting other film layers; and there is no need for a subsequent etching stopper layer. Furthermore, in the top-gate top-contact structure, the interface between the active layer and the insulating layer can be better treated, the interface defect state density can be reduced, the sub-threshold swing can be reduced, and the high mobility characteristics of IGZO can be fully utilized; at the same time, the Improve the contact interface between the active layer and the source/drain electrodes to form a good ohmic contact and reduce current crowding, thereby increasing the output current of the device and reducing the driving voltage. However, for the top gate structure, there are still stability and uniformity problems. After the IGZO coating, the insulating layer and electrodes are deposited, and the subsequent film production process needs to be produced under vacuum or in a plasma atmosphere, which will affect the IGZO film. The microstructure, such as too small or too large crystal grains, uneven and unreasonable crystal structure between crystal interfaces; even defects, such as ion vacancies. Therefore, the top-gate structure TFT also has unique and high requirements on the preparation technology of the active layer.

In view of this, people are eager to propose a composite active layer structure and manufacturing technology to meet the special requirements of the active layer in the top gate structure TFT; at the same time, for this composite active layer structure, the source and drain regions The method of active layer metallization reduces contact resistance; and annealing is carried out in an appropriate process, and finally a high-performance top-gate structure TFT device is obtained.

Contents of the invention

The technical problem to be solved by the present invention is to provide a top-gate structure metal oxide thin film transistor with excellent stability and uniformity in view of the insufficient characteristics, uniformity and stability of existing thin film transistor devices; for this reason, the present invention also provides A method for manufacturing the metal oxide thin film transistor with a top gate structure.

In order to solve the first technical problem above, the technical solution of the present invention is: a metal oxide thin film transistor with a top gate structure, including a substrate, an active layer, an insulating layer, a gate, a source and a drain, and the active layer is set On the substrate, the source is set at one end of the upper side of the active layer, the drain is set at the other end of the upper side of the active layer, the insulating layer is set in the middle of the upper side of the active layer, and the gate is set on the insulating layer ; A metallization layer is provided between the active layer and the source electrode, and a metallization layer is also provided between the active layer and the drain electrode; the active layer is a composite film structure, and the oxygen-poor Type metal oxide film layer, oxygen-rich type metal oxide film layer.

In the above technical solution, the active layer is prepared by sputtering, and the same target is used in the sputtering process, and the material of the target is (In ₂ O ₃ ) _x (Ga ₂ O ₃ ) _y (ZnO ) _z , where 0≤x, y, z≤1, and x+y+z=1; choose an oxygen-free or low-oxygen atmosphere during the sputtering process to obtain an oxygen-deficient metal oxide film, and choose an oxygen-rich atmosphere to obtain Oxygen-rich metal oxide film layer.

In the above technical solution, the metallization layer has a thickness of 0.1-20 nm, preferably 1-10 nm.

In order to solve the above-mentioned second technical problem, the technical solution of the present invention is: a method for manufacturing a top-gate structure metal oxide thin film transistor according to claim 1, comprising the following steps:

a. Make the active layer on the substrate by sputtering method, choose an oxygen-free or low-oxygen atmosphere to obtain an oxygen-deficient metal oxide film layer, and select an oxygen-rich atmosphere to obtain an oxygen-rich metal oxide film layer; the active layer is finished And after patterning, high-temperature annealing, the annealing temperature is 150 ° C ~ 500 ° C, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere;

b. On the upper side of the active layer, an insulating layer is made by sputtering, chemical vapor deposition, spin coating or printing; and the shape of the insulating layer is obtained by photolithography or masking; after the insulating layer is made, it is annealed at high temperature and annealed The temperature is 150℃～500℃, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere;

c. At both ends of the upper side of the active layer, metallization layers are fabricated by vacuum sputtering or evaporation methods; after the metallization layer is fabricated, anneal at high temperature to diffuse the metal into the active layer to form a metallized source contact region or drain contact region;

c. At both ends of the upper side of the active layer, metallization layers are fabricated by vacuum sputtering or evaporation methods; after the metallization layer is fabricated, anneal at high temperature to diffuse the metal into the active layer to form a metallized source contact region or drain contact region; the annealing temperature is 150°C to 500°C, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere;

e. Making a gate on the insulating layer by sputtering or vapor deposition, and obtaining the shape of the gate by photolithography or masking.

The beneficial effects of the present invention are: the present invention is a top-gate structure, and the active layer of the composite film structure is composed of an oxygen-poor metal oxide film layer and an oxygen-rich metal oxide film layer, and the active layer and the insulating layer can Better interfacial contact, reducing charge defects at the interface, and showing better electrical performance; a metallization layer is provided between the active layer and the source electrode of the present invention, and a metallization layer is also provided between the drain electrode, Improve the interface contact resistance between the semiconductor active layer and the source or drain, that is, the contact area between the metallized semiconductor and the source and drain, reduce the contact resistance, reduce the state leakage current, increase the electron mobility, and increase the current switch ratio (I _on /I _off ), which can significantly improve the electrical performance of the top-gate thin film transistor. In addition, the present invention improves the annealing link and the environment in the preparation process; further realizes the low off-state current, high electron mobility and current switch ratio of the enhanced metal oxide thin film transistor with good uniformity.

Description of drawings

FIG. 1 is a schematic diagram of the structure of the metal oxide thin film transistor of the present invention.

Fig. 2 is an output characteristic curve diagram of Embodiment 1 in the present invention.

Fig. 3 is a transfer characteristic curve diagram of Example 1 of the present invention.

Fig. 4 is an output characteristic curve diagram of Embodiment 2 of the present invention.

Fig. 5 is a transfer characteristic graph of Example 2 of the present invention.

Detailed ways

The inventive top gate structure metal oxide thin film transistor and its preparation method will be further described in detail below with reference to the accompanying drawings and specific embodiments.

As shown in Figure 1, the metal oxide thin film transistor with a top gate structure includes a substrate 1, an active layer 2, an insulating layer 3, a gate 4, a source and a drain 6, the active layer is arranged on the substrate, and the source Set at one end on the upper side of the active layer 2, the drain is set at the other end on the upper side of the active layer 2, the insulating layer 3 is set at the middle of the upper side of the active layer, and the gate 4 is set on the insulating layer 3; A metallization layer 5 is provided between the active layer 2 and the source electrode, and a metallization layer 5 is also provided between the active layer 2 and the drain electrode; the active layer 2 is a composite film structure, sequentially from bottom to top These are the oxygen-deficient metal oxide film layer 21 and the oxygen-enriched metal oxide film layer 22 .

The insulating layer 3 is an insulating metal oxide or a silicon-based insulating material or a polymer material.

Based on the above, the active layer 2 is prepared by sputtering, and the same target is used in the sputtering process, and the material of the target is (In ₂ O ₃ ) _x (Ga ₂ O ₃ ) _y (ZnO) _z , where 0≤x, y, z≤1, and x+y+z=1; in the sputtering process, an oxygen-free or low-oxygen atmosphere is selected to obtain an oxygen-deficient metal oxide film layer 21, and an oxygen-rich atmosphere is selected to obtain a rich Oxygen type metal oxide film layer 22 .

The material of the substrate 1 is silicon wafer, glass or ceramics; the glass substrate is preferably an alkali-free glass substrate or a glass substrate coated with a silicon dioxide film.

The insulating layer 3 is an insulating metal oxide or a silicon-based insulating material or a polymer material; further, the silicon-based insulating material is a silicon dioxide or silicon nitride insulating material or a composite material of the two.

The metallization layer 5 is one or more of metals Al, Mo, Cu, Ti or other low-resistivity metal materials, preferably Al here.

The metallization layer 5 has a thickness of 0.1-20 nm, preferably 1-10 nm.

The manufacturing method of the metal oxide thin film transistor with the above-mentioned top gate structure comprises the following steps:

a. Make the active layer on the substrate by sputtering method, choose an oxygen-free or low-oxygen atmosphere to obtain an oxygen-deficient metal oxide film layer, and select an oxygen-rich atmosphere to obtain an oxygen-rich metal oxide film layer; the active layer is finished And after patterning, high-temperature annealing, the annealing temperature is 150 ° C ~ 500 ° C, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere;

b. On the upper side of the active layer, an insulating layer is made by sputtering, chemical vapor deposition, spin coating or printing; and the shape of the insulating layer is obtained by photolithography or masking; after the insulating layer is made, it is annealed at high temperature and annealed The temperature is 150℃～500℃, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere;

c. At both ends of the upper side of the active layer, metallization layers are fabricated by vacuum sputtering or evaporation methods; after the metallization layer is fabricated, anneal at high temperature to diffuse the metal into the active layer to form a metallized source contact region or drain contact region; the annealing temperature is 150°C to 500°C, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere;

d. Make the source electrode by sputtering or evaporation on the metallized source contact area, and use photolithography or mask method to obtain the source shape; on the metallized drain contact area by sputtering or evaporation The method makes the drain electrode, and adopts photolithography or mask method to obtain the shape of the drain electrode;

e. Making a gate on the insulating layer by sputtering or vapor deposition, and obtaining the shape of the gate by photolithography or masking.

Further, the annealing temperature after fabrication of the active layer is preferably 150°C to 350°C, the annealing temperature after fabrication of the insulating layer is preferably 150°C to 350°C, and the annealing temperature after fabrication of the metallization layer is It is also preferably 150°C to 350°C.

The electrode materials of the source electrode, the drain electrode and the gate electrode are all one or more of metal Al, Mo, Cu, Ti or other low-resistivity metal materials, preferably Mo here.

The specific production steps are:

Example 1:

(1) Sputtering 20nm oxygen-deficient IGZO (made in a single-component Ar atmosphere) on the alkali-free glass, and then sputtering 5nm oxygen-enriched IGZO (made in a single-component oxygen atmosphere) with the same target; then wet etching Eclipse, graphical IGZO;

(2) Anneal in a dry oxygen atmosphere at 300°C for one hour;

(3) Sputtering 20nm silicon dioxide and 300nm silicon nitride on the composite active layer as the insulating layer;

(4) Anneal in air at 200°C for one hour;

(5) Sputtering 100nm metal molybdenum as the gate electrode;

(6) Sputtering 100nm metal molybdenum as source/drain electrodes.

In addition, in the first embodiment, please refer to FIG. 2 for the output characteristic curve, and please refer to FIG. 3 for the transfer characteristic curve.

Example 2:

In this implementation, a thin film transistor was fabricated according to a method and conditions similar to those of Example 1. The difference is that the following two steps are added between (5) and (6):

(6) Sputtering 5nm metal aluminum for metallizing the active layer;

(7) Anneal in a dry oxygen atmosphere at 300°C for one hour.

In addition, in the second embodiment, please refer to FIG. 4 for the output characteristic curve, and please refer to FIG. 5 for the transfer characteristic curve.

Example 3:

In this example, a thin film transistor was fabricated according to a method and conditions similar to those of Example 2. The difference is that the insulating layer annealing in step (4) is cancelled.

Example 4:

In this example, a thin film transistor was fabricated according to a method and conditions similar to those of Example 3. The difference is that the annealing of the active layer in steps (1) and (2) is changed before patterning.

Example 5:

In this example, a thin film transistor was fabricated according to a method and conditions similar to those of Example 4. The difference is that the annealing of the active layer in steps (1) and (2) is performed once before patterning and once after patterning.

Embodiment 6:

In this example, a thin film transistor was fabricated according to a method and conditions similar to those of Example 2. The difference is that the annealing of the active layer in step (2) is cancelled.

Table 1: The characteristic contrast of each embodiment

From the results in Table 1, it can be known that making a thin layer of aluminum in the source and drain electrode regions and metallizing the active layer in this region by thermal diffusion can effectively reduce the subthreshold swing of the thin film transistor and control the threshold voltage around 0V ; The annealing of the active layer has a great influence on the characteristics of the thin film transistor, and the characteristics are relatively poor without annealing; the annealing of the active layer after patterning can improve the uniformity of the thin film transistor, increase the mobility of the thin film transistor, and improve the subthreshold value Swing, so that the threshold voltage of the device is significantly shifted to the positive direction; the annealing of the active layer before and after patterning is not much different from the annealing of the active layer before patterning. In addition, annealing after the insulating layer can improve the uniformity of the thin film transistor, increase the mobility of the thin film transistor, and change the working mode of the device from depletion to enhancement.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, its architecture can be flexible and changeable, and series of products can be derived. Just making some simple deductions or replacements should be deemed to belong to the patent protection scope of the present invention determined by the submitted claims.

Claims (10)

1. A metal oxide thin film transistor with a top gate structure, comprising a substrate, an active layer, an insulating layer, a gate, a source and a drain, the active layer being arranged on the substrate, and the source being arranged on the upper side of the active layer One end, the drain is set on the other end of the upper side of the active layer, the insulating layer is set in the middle of the upper side of the active layer, and the gate is set on the insulating layer; it is characterized in that: between the active layer and the source A metallized layer is provided, and a metallized layer is also provided between the active layer and the drain electrode; the active layer is a composite film structure, which is an oxygen-deficient metal oxide film layer, an oxygen-rich type film layer from bottom to top. Metal oxide film layer. 2. The metal oxide thin film transistor with top gate structure according to claim 1, characterized in that: the active layer is prepared by sputtering, and the same target is used in the sputtering process, and the material of the target is (In ₂ O ₃ ) _x (Ga ₂ O ₃ ) _y (ZnO) _z , where 0≤x, y, z≤1, and x+y+z=1; choose oxygen-free or low-oxygen during sputtering The oxygen-deficient metal oxide film layer is obtained by using the atmosphere, and the oxygen-enriched metal oxide film layer is obtained by selecting an oxygen-rich atmosphere. 3 . The metal oxide thin film transistor with top gate structure according to claim 1 , wherein the material of the substrate is silicon wafer, glass or ceramics. 4 . 4 . The metal oxide thin film transistor with a top gate structure according to claim 1 , wherein the insulating layer is an insulating metal oxide or a silicon-based insulating material or a polymer material. 5 . The metal oxide thin film transistor with a top gate structure according to claim 4 , wherein the silicon-based insulating material is silicon dioxide or silicon nitride insulating material or a composite material of the two. 6. The metal oxide thin film transistor with top gate structure according to claim 1, characterized in that: the metallization layer is one or more of metal Al, Mo, Cu, Ti or other metal materials with low resistivity kind. 7 . The metal oxide thin film transistor with top gate structure according to any one of claims 1 to 6 , wherein the metallization layer has a thickness of 0.1 to 20 nm, preferably 1 to 10 nm. 8. A method for manufacturing a metal oxide thin film transistor with a top gate structure according to claim 1, comprising the following steps: a. Make the active layer on the substrate by sputtering method, choose an oxygen-free or low-oxygen atmosphere to obtain an oxygen-deficient metal oxide film layer, and select an oxygen-rich atmosphere to obtain an oxygen-rich metal oxide film layer; the active layer is finished And after patterning, high-temperature annealing, the annealing temperature is 150 ° C ~ 500 ° C, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere; b. On the upper side of the active layer, an insulating layer is made by sputtering, chemical vapor deposition, spin coating or printing; and the shape of the insulating layer is obtained by photolithography or masking; after the insulating layer is made, it is annealed at high temperature and annealed The temperature is 150℃～500℃, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere; c. At both ends of the upper side of the active layer, metallization layers are fabricated by vacuum sputtering or evaporation methods; after the metallization layer is fabricated, anneal at high temperature to diffuse the metal into the active layer to form a metallized source contact region or drain contact region; the annealing temperature is 150°C to 500°C, and the annealing is carried out in the atmosphere or an oxygen-containing atmosphere; d. Make the source electrode by sputtering or evaporation on the metallized source contact area, and use photolithography or mask method to obtain the source shape; on the metallized drain contact area by sputtering or evaporation The method makes the drain electrode, and adopts photolithography or mask method to obtain the shape of the drain electrode; e. Making a gate on the insulating layer by sputtering or vapor deposition, and obtaining the shape of the gate by photolithography or masking. 9. The method for manufacturing a metal oxide thin film transistor with a top gate structure according to claim 8, characterized in that: the annealing temperature after the active layer is fabricated is 150° C. to 350° C., and the insulating layer after the fabricated The annealing temperature is 150°C-350°C, and the annealing temperature after the metallization layer is fabricated is 150°C-350°C. 10. The method for manufacturing a metal oxide thin film transistor with a top gate structure according to claim 8 or 9, characterized in that: the electrode materials of the source, drain and gate are metal Al, Mo, Cu, Ti or One or more of other low-resistivity metal materials.

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