CN110993696B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Abstract

The invention discloses a semiconductor device, which comprises a substrate, a first metal layer, a first bump, an insulating layer, a semiconductor layer and a second metal layer. The first metal layer is disposed on the substrate. The first bump is disposed on the substrate, and a first portion of the first metal layer partially covers an upper surface of the first bump. The insulation layer covers the first part of the first metal layer and the local upper surface of the first bump. The semiconductor layer is disposed on the insulating layer. The second metal layer is disposed on the semiconductor layer.

Description

Semiconductor device

technical field

The present invention relates to a semiconductor device.

Background technique

Semiconductor devices are widely used in consumer electronic products, such as mobile phones, notebook computers, digital cameras, and the like. The semiconductor device is, for example, a thin film transistor (TFT), which can be arranged on a display panel, such as a liquid crystal display (liquid crystal displays, LCD) and an organic electroluminescence display (OELD or OLED), etc., to The display panel has the advantages of thinness and low power consumption, so the thin film transistor display panel has become a mainstream commodity in the market.

In general, thin film transistors include top-gate TFTs and bottom-gate TFTs. The TFT includes a semiconductor layer as an active layer or a channel layer. Therefore, if it is irradiated by an external light source (eg, a backlight), the semiconductor layer of the TFT is likely to cause photo-induced current leakage due to the light. Wherein, the leakage current caused by the light will not only affect the performance of the TFT device itself, but also cause cross-talk when the picture is displayed, resulting in a decrease in the display quality of the display. In addition, after the light passes through the TFT substrate, part of the light may still be reflected by the upper substrate and absorbed by the semiconductor layer or reach the semiconductor layer of the TFT through other paths, which needs to be improved.

Contents of the invention

The invention relates to a semiconductor device for improving the performance of the semiconductor device.

According to an aspect of the present invention, a semiconductor device is provided, including a substrate, a first metal layer, a first bump, an insulating layer, a semiconductor layer and a second metal layer. The first metal layer is disposed on the substrate. The first bump is disposed on the substrate, wherein a first portion of the first metal layer partially covers an upper surface of the first bump. The insulating layer covers the first part of the first metal layer and the partial upper surface of the first bump. The semiconductor layer is disposed on the insulating layer. The second metal layer is disposed on the semiconductor layer.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given below, and the accompanying drawings are described in detail as follows:

Description of drawings

FIG. 1A is a schematic plan view of a pixel structure according to an embodiment of the present invention;

FIG. 1B is an enlarged schematic view of a semiconductor device located in the pixel structure of FIG. 1A according to an embodiment of the present invention;

FIG. 1C is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention along the line I-I of FIG. 1B;

2A is a schematic plan view of a pixel structure according to an embodiment of the present invention;

2B is an enlarged schematic view of a semiconductor device located in the pixel structure of FIG. 2A according to an embodiment of the present invention;

2C is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention along the line I-I in FIG. 2B;

3A and 3B are an enlarged schematic view and a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

4A and 4B are an enlarged schematic view and a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

FIG. 5 is a schematic diagram of the improvement percentage of the reduction of light absorption due to the blocking of the raised first metal layer by the semiconductor layer according to another embodiment of the present invention;

FIG. 6 is a schematic diagram showing that the amount of light absorbed by the semiconductor layer in FIG. 5 decreases as the height of the raised first metal layer increases.

Symbol Description

T: thin film transistor

G: grid

GI: gate insulating layer

AS: semiconductor layer

S: source

D: Drain

100A, 100B: pixel structure

101: Substrate

102: scan line

103: shared line

104: data line

105: pixel electrode

110A, 110B, 110C, 110D: semiconductor device

111: first metal layer

111a: Part I

111b: extension

112: first bump

113: insulation layer

114: semiconductor layer

115: second metal layer

117: Second bump

S1, S2, S3: upper surface

OA, OA1, OA2: Open area

B: light

H1: first thickness

H2: second thickness

H3: third thickness

H4: fourth thickness

L: Length

Detailed ways

The following examples are provided for detailed description, and the examples are only used as examples for illustration, and are not intended to limit the scope of protection of the present invention. The same/similar symbols are used to represent the same/similar components in the following description. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only directions referring to the attached drawings. Accordingly, the directional terms used are for the purpose of illustration and not for the purpose of limiting the invention.

According to an embodiment of the present invention, a semiconductor device is provided to avoid the problem of leakage current generated by the semiconductor layer due to light irradiation. As shown in FIG. 1A and FIG. 2A, the semiconductor device is, for example, a thin film transistor T or an active/switching element, and the thin film transistor T is arranged on a substrate 101. The substrate 101 is, for example, glass, quartz, organic polymer, or other applicable material, the substrate 101 has light transmittance, so that the backlight can pass through the substrate 101 . In one embodiment, the thin film transistor T includes a gate G, a gate insulating layer GI, a semiconductor layer AS, an ohmic contact layer, a source S and a drain D. As shown in FIG. The gate G, the scan line 102 and the common line 103 can be formed on the substrate 101 first. Materials of the gate G, the scan line 102 and the common line 103 may include metal, metal oxide, organic conductive material or a combination thereof. The scan line 102 is electrically connected to the gate G, and the scan line 102 and the common line 103 are separated from each other. Next, a gate insulating layer GI is formed on the substrate 101, and the gate insulating layer GI is disposed on the gate G. The material of the gate insulating layer GI includes inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride), organic materials, or other suitable materials. In addition, a semiconductor layer AS is formed on the gate insulating layer GI. The semiconductor layer AS can be metal oxide semiconductor, polysilicon, amorphous silicon or other suitable semiconductor materials. The above metal oxide semiconductor materials are, for example, Indium-Gallium-Zinc Oxide (IGZO), Zinc Oxide (ZnO ), tin oxide (SnO), indium zinc oxide (Indium-ZincOxide, IZO), gallium-zinc oxide (Gallium-Zinc Oxide, GZO), zinc-tin oxide (Zinc-Tin Oxide, ZTO) or indium-tin oxide (Indium-Tin Oxide, ITO) and so on. Next, an ohmic contact layer is formed on the semiconductor layer AS, and part of the semiconductor layer AS is exposed by the ohmic contact layer. The ohmic contact layer may be dopant-containing metal oxide semiconductor material, dopant-containing polysilicon, dopant-containing amorphous silicon, or other suitable dopant-containing semiconductor materials. Next, the data line 104 is formed on the substrate 101, and the source S and the drain D are formed on the ohmic contact layer, so that the thin film transistor T can be formed in a pixel structure 100A of the display panel and electrically connected to the pixel electrode 105, such as Figure 1A and Figure 2A.

1A and 2A, the scanning line 102 and the data line 104 are respectively located in different film layers, and an insulating layer (such as a gate insulating layer GI) is sandwiched between the two, and the common line 103 and the data line 104 are They are respectively located in different film layers, and an insulating layer (such as a gate insulating layer GI) is sandwiched between them. The extending direction of the scanning lines 102 is different from the extending direction of the data lines 104. Preferably, the extending direction of the scanning lines 102 is perpendicular to the extending direction of the data lines 104, but the present invention is not limited thereto.

In this embodiment, in order to solve the problem of leakage current, the gate G (hereinafter referred to as the first metal layer 111 ) can use bumps for raising the height of the gate G so that the height of the gate G is relatively higher than or equal to that covered by the gate G. The height of the upper gate insulating layer GI (hereinafter referred to as the insulating layer 113), so that light incident at a predetermined angle from the side of the gate G will be reflected by the elevated gate G and away from the semiconductor layer AS above the gate insulating layer GI. , so it can effectively solve the problem of the leakage current caused by the semiconductor layer AS (hereinafter referred to as the semiconductor layer 114 ) being illuminated.

Please refer to FIG. 1B and FIG. 1C. FIG. 1B shows an enlarged schematic diagram of a semiconductor device 110A located in the pixel structure 100A of FIG. The semiconductor device 110A includes a substrate 101 , a first metal layer 111 , a first bump 112 , an insulating layer 113 , a semiconductor layer 114 and a second metal layer 115 . The first metal layer 111 is disposed on the substrate 101 . The first bump 112 is disposed on the substrate 101 , wherein a first portion 111 a of the first metal layer 111 partially covers the upper surface S1 of the first bump 112 . The insulating layer covers the first portion 111 a of the first metal layer 111 and the partial upper surface S1 of the first bump 112 . The semiconductor layer 114 is disposed on the insulating layer 113 . The second metal layer 115 is disposed on the semiconductor layer 114 . The second metal layer 115 may include a source S and a drain D. Referring to FIG.

In one embodiment, both the first metal layer 111 and the first bump 112 are disposed on the substrate 101, for example, the first bump 112 is first formed on the substrate 101, and then the first metal layer 111 is formed on the substrate 101 and part of the first bump 101. on a bump 112 . Since the first metal layer 111 only covers part of the upper surface S1 of the first bump 112, the first part 111a of the first metal layer 111 overlaps with a part of the first bump 112, and the first metal layer 111 also has a An extension portion 111b extending along the upper surface S2 of the substrate 101, the length L of the extension portion 111b is at least greater than the length of the first portion 111a overlapping with the first bump 112, for example, the length L of the extension portion 111b is 3 times the length of the first portion 111a times, 4 times or more.

In addition, since the first metal layer 111 only covers part of the upper surface S1 of the first bump 112, the first bump 112 extends out of the side of the first metal layer 111 opposite to the extension portion 111b, for example, the first bump The block 112 is located on the open area OA of the substrate 101 (ie, the open area not covered by the first metal layer 111 ). When the first bump 112 is made of a light-transmitting material, the first bump 112 covers the opening area without affecting the aperture ratio of the substrate 101. Therefore, the first bump 112 is preferably made of a light-transmitting material, but the present invention This is not the limit.

In one embodiment, when light B incident at a predetermined angle passes through the substrate 101 through the opening area OA of the substrate 101, since the first bump 112 and the insulating layer 113 are light-transmittable materials, the light B can pass through the first bump. The block 112 and the insulating layer 113 may enter into the first bump 112 and the insulating layer 113 , but the light B will still be blocked by the raised first metal layer 111 . Therefore, after the first portion 111a of the first metal layer 111 is raised by the first bump 112, a light blocking wall (ie, a raised portion) can be formed to block the light B entering the semiconductor device 110A through the insulating layer 113, or The light reflected into the semiconductor device 110A through the upper plate (eg, color filter plate) is blocked to reduce the leakage current. In another embodiment, if the influence on the aperture ratio of the substrate 101 is not considered, the first bump 112 made of an opaque material can also be selected, and the light B can be blocked by the first bump 112 .

In one embodiment, the first bump 112 has a first material, for example, the first metal layer 111 has a second material, and the first material is different from the second material. That is to say, the first bump 112 and the first metal layer 111 are not made of the same material. The first bump 112 can be made of light-transmitting material, non-light-transmitting material, metal material, organic dielectric material (such as resin and other polymer materials) or inorganic dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) . The first metal layer 111 can be metal material, metal oxide, organic conductive material or other suitable materials.

1C, the first bump 112 has a first thickness H1, the insulating layer 113 has a second thickness H2, the first portion 111a of the first metal layer 111 has a third thickness H3, and the first metal layer 111 An extension portion 111b has a fourth thickness H4. The first thickness H1 refers to the vertical distance between the upper surface S1 of the first bump 112 and the upper surface S2 of the substrate 101, and the second thickness H2 refers to the upper surface of the insulating layer 113 and the upper surface of the extension portion 111b of the first metal layer 111. The vertical distance between the surfaces, the third thickness H3 refers to the vertical distance between the upper surface of the first part 111a of the first metal layer 111 and the upper surface S1 of the first bump 112, and the fourth thickness H4 refers to the first metal layer 111 The vertical distance between the upper surface of the extension portion 111b and the upper surface S2 of the substrate 101 .

Although affected by the vapor deposition and the thickness of the first bump 112, the first metal layer 111 may be non-uniformly formed on the first bump 112 and the substrate 101, especially on the sides of the first bump 112 and the substrate 101. At the intersection of the first metal layer 111, the thickness of the first metal layer 111 may be affected by the deposition process and have errors (for example, the error is less than 5%), but overall, the thickness of the first part 111a of the first metal layer 111 is the same as that of the extension part 111b The thicknesses are substantially equal, for example equal to 5000 angstroms or within a preset error range, or the thickness of the first portion 111a of the first metal layer 111 may be slightly smaller than the thickness of the extension portion 111b. That is, the third thickness H3 may be less than or equal to the fourth thickness H4, but the third thickness H3 may also be greater than the fourth thickness H4.

In addition, there may be a ratio between the first thickness H1 and the second thickness H2, for example, between 1 and 4, that is to say, the first thickness H1 may be greater than or equal to the second thickness H2, but the present invention does not limit. The higher the ratio, the greater the thickness of the first bump 112 relative to the thickness of the insulating layer 113, so the height of the light blocking wall (the sum of the first thickness H1 and the third thickness H3) is also higher; the smaller the ratio, the first The smaller the thickness of the bump 112 relative to the thickness of the insulating layer 113 , the lower the height of the light blocking wall (the sum of the first thickness H1 and the third thickness H3 ) is also.

In one embodiment, the first thickness H1 is, for example, between 5000 angstroms and 15000 angstroms, but even if the first thickness H1 is less than 5000 angstroms, such as 2000 angstroms or 3000 angstroms, light rays B incident at a large angle (for example, the incident angle is greater than 45 degree) can still be blocked by the raised first metal layer 111, so we can change or modify the height of the first bump 112 (ie, the first thickness H1 ) according to the angle change of the incident light.

In addition, the second thickness H2, the third thickness H3 and the fourth thickness H4 may be between 4000 angstroms and 5000 angstroms, the second thickness H2 is, for example, 4000 angstroms, and the third thickness H3 and the fourth thickness H4 are, for example, 5000 angstroms. In one embodiment, the sum of the first thickness H1 and the third thickness H3 is greater than or equal to the sum of the second thickness H2 and the fourth thickness H4, wherein the sum of the first thickness H1 and the third thickness H3 is the height of the light blocking wall , the sum of the second thickness H2 and the fourth thickness H4 is the height of the location of the semiconductor layer 114 . Therefore, as long as the height of the light-blocking wall is greater than or equal to the height of the location of the semiconductor layer 114, the laterally incident light B can be prevented from reaching the semiconductor layer 114 in the semiconductor device 110A through the insulating layer 113, thereby reducing leakage current. question. Certainly, the higher the height of the light blocking wall is, the less likely it is for the light B to reach the semiconductor layer 114 in the semiconductor device 110A through the insulating layer, and more light B will be reflected into the semiconductor device 110A through the upper plate (such as a color filter plate). will be blocked, so the better the light blocking effect.

Please refer to FIG. 2B and FIG. 2C. FIG. 2B shows an enlarged schematic diagram of a semiconductor device 110B located in the pixel structure 100B of FIG. 2A, and FIG. The semiconductor device 110B of this embodiment is similar to the semiconductor device 110A of the above-mentioned embodiment, and the same components are denoted by the same component symbols, which will not be repeated here. The semiconductor devices 110A, 110B of the above two embodiments can be applied in the pixel structures 100A, 100B with multiple domain pixel electrodes 105 , such as 8-domain, 4-domain or other pixel electrodes. That is to say, one pixel has a plurality of domain-divided pixel electrodes 105 to reduce the degree of grayscale inversion, thereby improving the viewing angle of the liquid crystal display panel. Of course, the semiconductor devices 110A, 110B of the above two embodiments are not limited to be used only in the pixel structures 100A, 110B with multi-domain pixel electrodes 105, and can also be applied in wide-viewing film display mode, vertical alignment In the liquid crystal structures of the (vertical alignment) display mode and the in-plane switching display mode, the present invention is not limited thereto.

Please refer to FIG. 3A and FIG. 3B , which illustrate an enlarged schematic view and a schematic cross-sectional view of a semiconductor device 110C according to another embodiment of the present invention. This embodiment is similar to the above two embodiments, the difference is that: the semiconductor device 110C of this embodiment includes a first bump 112 and a second bump 117, and the first bump 112 and a second bump 117 are respectively located on On opposite sides of the first metal layer 111, a first portion 111a of the first metal layer 111 partially covers an upper surface S1 of the first bump 112, and a second portion 111c of the first metal layer 111 partially covers the second bump. An upper surface S3 of the block 117 . Therefore, the opposite sides of the first metal layer 111 are respectively elevated by the first bump 112 and the second bump 117 to bulge. The recessed portion, so that the semiconductor layer 114 can be located in the recessed portion, and the height (H2+H4) of the position of the semiconductor layer 114 is slightly lower than or equal to the height of the raised portion (that is, the thickness of the first bump 112 is the same as that of the first metal The sum of the thickness of the layer 111 H1+H3/the sum of the thickness of the second bump 117 and the thickness of the first metal layer 111 H1+H3).

In one embodiment, the first bump 112 and the second bump 117 have the same height and can be deposited from a film layer of the same material, and part of the film layer is removed by patterned etching, and then the first metal layer 111 is deposited On the substrate 101 , the first bump 112 and the second bump 117 , the height of the raised portion of the first metal layer 111 is greater than the height of the depressed portion.

Please refer to FIG. 4A and FIG. 4B , which illustrate an enlarged schematic view and a schematic cross-sectional view of a semiconductor device 110D according to another embodiment of the present invention. The semiconductor device 110D of this embodiment is similar to the semiconductor device 110C of the above-mentioned embodiment, and the same components are denoted by the same component symbols, which will not be repeated here. The semiconductor devices 110C and 110D in the above two embodiments are formed with light-blocking walls (ie raised portions) on opposite sides of the first metal layer 111 , wherein the first bump 112 is located in an opening area OA1 of the substrate 101 (not covered by the first bump 112 ). On the opening area covered by the metal layer 111), the second bump 117 is located on the other opening area OA2 of the substrate 101. Therefore, when the light B passes through the substrate 101 from the two opening areas OA1 and OA2 of the substrate 101, the light B will be The elevated first metal layer 111 blocks, thereby achieving the problem of reducing leakage current, and the light blocking effect is better than that of the first metal layer 111 with only one light blocking wall on one side.

Please refer to FIG. 5 and FIG. 6, wherein FIG. 5 shows the percentage of light absorption reduced by the blocking of the first metal layer 111 after the semiconductor layer 114 is raised, and FIG. 6 shows that the light absorption of the semiconductor layer 114 increases with A schematic diagram showing that the height of the first metal layer 111 increases and decreases. Taking the spectral integral energy absorbed by the semiconductor layer 114 when the incident angle of light (wavelength range between 400-700nm) incident on the substrate 101 at an incident angle of 40 degrees is taken as an example, when the height of the bump is 0 angstroms, the light absorption amount of the semiconductor layer 114 is 0.0095 energy units (the higher the negative value, the higher the light absorption); when the height of the bump is 5000 angstroms, the light absorption of the semiconductor layer 114 is 0.0068 energy units, which is 28% less than the light absorption percentage of 0.0095 (The higher the negative value, the better the improvement). When the height of the bump is 7000 angstroms, the light absorption of the semiconductor layer 114 is 0.0042 energy units, and the light absorption percentage is reduced by 55%. When the height of the bump is 10000 angstroms, the light absorption of the semiconductor layer 114 is 0.0026 energy units, and the light absorption percentage 72% reduction, when the height of the bump is 12500 angstroms, the light absorption of the semiconductor layer 114 is 0.00036 energy units, the improvement percentage is reduced by 96%, when the height of the bump is 15000 angstroms, the light absorption of the semiconductor layer 114 is 0.0032 energy units unit, the percent absorbance is reduced by 97%.

From the above data, it can be seen that when the thickness of the bump is higher, the light absorption of the semiconductor layer is smaller, and on the contrary, when the thickness of the bump is lower, the light absorption of the semiconductor layer is greater. Therefore, it can be proved that the smaller the light absorption amount of the semiconductor layer, the light incident into the semiconductor device can be effectively blocked by the first metal layer, and the higher the height of the bump, the better the light blocking effect.

In summary, although the present invention is disclosed in combination with the above embodiments, they are not intended to limit the present invention. Those skilled in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (14)

1. A semiconductor device, characterized in that, comprising: Substrate; a first metal layer disposed on the substrate, wherein the first metal layer is a gate; a first bump disposed on the substrate, wherein the first portion of the first metal layer partially covers an upper surface of the first bump; an insulating layer covering the first portion of the first metal layer and part of the upper surface of the first bump; a semiconductor layer disposed on the insulating layer; a second metal layer disposed on the semiconductor layer, wherein the second metal layer includes a source and a drain; and a pixel electrode electrically connected to the drain; Wherein, there is an opening area between the pixel electrode and the first metal layer, and the first bump is located in the opening area. 2. The semiconductor device according to claim 1, wherein the first bump has a first material, the first metal layer has a second material, and the first material is different from the second material. 3. The semiconductor device according to claim 2, wherein the first material is a light-transmitting material. 4. The semiconductor device according to claim 2, wherein the first material is an organic dielectric material or an inorganic dielectric material. 5. The semiconductor device as claimed in claim 2, wherein the first material is a non-transparent material. 6. The semiconductor device as claimed in claim 1, wherein the first bump has a first thickness, a part of the insulating layer overlaps the semiconductor layer and has a second thickness, and the first thickness is greater than or equal to the second thickness. 7. The semiconductor device according to claim 6, wherein the first portion of the first metal layer has a third thickness, the extension portion of the first metal layer covers the upper surface of the substrate, and the extension portion has a fourth thickness, Wherein the third thickness is less than or equal to the fourth thickness. 8. The semiconductor device according to claim 7, wherein the sum of the first thickness and the third thickness is greater than or equal to the sum of the second thickness and the fourth thickness. 9. The semiconductor device according to claim 7, wherein the first thickness is between 5000-15000 angstroms, and the second thickness, the third thickness and the fourth thickness are between 4000-5000 angstroms. 10. The semiconductor device as claimed in claim 7, further comprising a pixel structure having a pixel electrode electrically connected to the second metal layer. 11. The semiconductor device according to claim 1, further comprising a second bump disposed on the substrate, wherein the second portion of the first metal layer partially covers the upper surface of the second bump, and the insulating layer Covering the second portion of the first metal layer and part of the upper surface of the second bump. 12. The semiconductor device according to claim 11, wherein the semiconductor layer is correspondingly located on the insulating layer between the first bump and the second bump. 13. The semiconductor device according to claim 11, wherein a recess is formed between the first bump and the second bump, and the semiconductor layer is correspondingly located on the recess. 14. The semiconductor device as claimed in claim 11, wherein the second bump is located in the opening area.

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