CN116207138A - Transistor, manufacturing method thereof and semiconductor device - Google Patents

Abstract

The present application provides a transistor, a manufacturing method thereof, and a semiconductor device. The transistor includes a substrate, a gate layer disposed on one side of the substrate, a source-drain layer, and an active layer, and the material of the active layer includes a semiconductor oxide; wherein , an auxiliary electrode layer is provided between the active layer and the source-drain layer, and the orthographic projection of the auxiliary electrode layer on the substrate is respectively the same as the orthographic projection of the source-drain layer on the substrate and the orthographic projection of the active layer on the substrate. Projection overlapping, ohmic contact between the auxiliary electrode layer and the active layer; or, ohmic contact between the auxiliary electrode layer and the source-drain layer. By setting the auxiliary electrode layer between the active layer and the source-drain layer, the electrical connection between the active layer and the source-drain layer is realized through the auxiliary electrode layer, which avoids the direct contact between the active layer and the source-drain layer. Oxidation of the surface of the drain layer increases the contact resistance between the source-drain layer and the active layer, ensuring the performance of the transistor.

Description

Transistor, manufacturing method thereof, and semiconductor device

technical field

The present application relates to the technical field of semiconductor devices, and in particular, the present application relates to a transistor, a manufacturing method thereof, and a semiconductor device.

Background technique

Field Effect Transistor (FET) has the advantages of high input resistance, low noise, low power consumption, large dynamic range, easy integration, wide safe operating area, etc., and is widely used in various electronic devices. Depending on the material of the active layer, field effect transistors include semiconductor oxide transistors and amorphous silicon (a-Si) transistors. Materials for the active layer in semiconductor oxide transistors include metal oxides such as Indium Gallium Zinc Oxide (IGZO). Compared with a-si transistors, IGZO transistors have high carrier mobility and light sensitivity. low merit.

However, the existing IGZO transistor has the problem of high contact resistance between the active layer and the source-drain metal layer, which increases the power consumption of the transistor and affects the performance of the transistor.

Contents of the invention

In view of the shortcomings of the existing methods, the present application proposes a transistor and its manufacturing method, and a semiconductor device to solve the problem of high contact resistance between the active layer and the source-drain metal layer of the transistor in the prior art.

In the first aspect, the embodiment of the present application provides a transistor, including:

a substrate, a gate layer, a source-drain layer, and an active layer disposed on one side of the substrate, and the material of the active layer includes a semiconductor oxide;

Wherein, an auxiliary electrode layer is provided between the active layer and the source-drain layer, and the orthographic projection of the auxiliary electrode layer on the substrate is respectively the same as that of the source-drain layer on the substrate. The orthographic projection of and the orthographic projection of the active layer on the substrate overlap;

The auxiliary electrode layer is in ohmic contact with the active layer; or, the auxiliary electrode layer is in ohmic contact with the source-drain layer.

Optionally, including a gate insulating layer;

The gate layer is arranged on one side of the substrate;

The gate insulating layer is disposed on a side of the gate layer away from the substrate, and the gate insulating layer covers the gate layer;

The source-drain layer is disposed on a side of the gate insulating layer away from the substrate;

The active layer is disposed on a side of the source and drain layers away from the substrate.

Optionally, when the auxiliary electrode layer is in ohmic contact with the source-drain layer, the material of the auxiliary electrode layer includes doped polysilicon; or, the material of the auxiliary electrode layer includes metal oxide, so The resistivity of the metal oxide is less than 10 ^-6 ohm·m.

Optionally, when the auxiliary electrode layer is in ohmic contact with the active layer, the material of the auxiliary electrode layer includes gold, silver and iron.

Optionally, the auxiliary electrode layer covers the surface of the source-drain layer facing the active layer.

In a second aspect, the embodiment of the present application provides a semiconductor device, including the transistor in the embodiment of the present application.

In a third aspect, the embodiment of the present application provides a method for manufacturing a transistor, including:

providing a substrate;

making a gate layer on one side of the substrate through a patterning process;

forming a gate insulating layer on the side of the gate layer away from the substrate, so that the gate insulating layer covers the gate layer;

Forming a source-drain layer and an auxiliary electrode layer in sequence on the side of the gate insulating layer away from the substrate, and connecting the source-drain layer to the auxiliary electrode layer;

Forming an active layer on the side of the auxiliary electrode layer away from the substrate, the active layer is connected to the auxiliary electrode layer, wherein an ohmic contact is formed between the auxiliary electrode layer and the active layer ; or, the auxiliary electrode layer is in ohmic contact with the source-drain layer.

Optionally, forming the source-drain layer and the auxiliary electrode layer sequentially on the side of the gate insulating layer away from the substrate includes:

forming a first conductive layer on a side of the gate insulating layer away from the substrate;

forming a second conductive layer on a side of the first conductive layer away from the substrate;

Polishing the first conductive layer and the second conductive layer through a chemical mechanical polishing process until the side of the gate insulating layer away from the substrate is partially exposed, so as to form a source and drain layer and an auxiliary electrode layer, Wherein, the auxiliary electrode layer is in ohmic contact with the active layer.

Optionally, forming the source-drain layer and the auxiliary electrode layer sequentially on the side of the gate insulating layer away from the substrate includes:

forming a first conductive layer on a side of the gate insulating layer away from the substrate;

forming a semiconductor layer on the side of the first conductive layer away from the substrate;

The first conductive layer and the semiconductor layer are polished by a chemical mechanical polishing process until the side of the gate insulating layer away from the substrate is partially exposed, so as to form a source and drain layer and an auxiliary electrode layer, wherein, There is an ohmic contact between the auxiliary electrode layer and the source-drain layer.

Optionally, forming the source-drain layer and the auxiliary electrode layer sequentially on the side of the gate insulating layer away from the substrate includes:

Forming a source and drain layer on the side of the gate insulating layer away from the substrate through a patterning process;

An auxiliary electrode layer is formed on the side of the source and drain layers away from the substrate by a patterning process.

The beneficial technical effects brought by the technical solutions provided by the embodiments of the present application include:

The transistor in the embodiment of the present application includes a substrate, a gate layer arranged on one side of the substrate, a source-drain layer, and an active layer, and the material of the active layer includes a semiconductor oxide; wherein, the active layer and the source-drain layer An auxiliary electrode layer is provided between the layers. The orthographic projection of the auxiliary electrode layer on the substrate overlaps with the orthographic projection of the source and drain layers on the substrate and the orthographic projection of the active layer on the substrate. The active layers are in ohmic contact; or, the auxiliary electrode layer and the source-drain layer are in ohmic contact. By setting the auxiliary electrode layer between the active layer and the source-drain layer, the electrical connection between the active layer and the source-drain layer is realized through the auxiliary electrode layer, which avoids the direct contact between the active layer and the source-drain layer. Oxidation of the surface of the drain layer increases the contact resistance between the source-drain layer and the active layer, ensuring the performance of the transistor.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and will become apparent from the description, or may be learned by practice of the application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic structural diagram of a transistor in the prior art;

FIG. 2 is a schematic structural diagram of a transistor provided in an embodiment of the present application;

FIG. 3 is a schematic structural diagram of another transistor provided in the embodiment of the present application;

FIG. 4 is a schematic structural diagram of another transistor provided in the embodiment of the present application;

FIG. 5 is a schematic structural diagram of stacked transistors;

FIG. 6 is a flow chart of the fabrication of the transistor provided in the embodiment of the present application;

7a to 7g are structural schematic diagrams of different processes for manufacturing transistors provided by the embodiment of the present application;

8a to 8e are structural schematic diagrams of different processes for manufacturing transistors provided by the embodiment of the present application;

9a to 9d are structural schematic diagrams of different processes for manufacturing transistors provided by the embodiment of the present application.

In the picture:

10-transistor; 11-substrate; 12-gate layer; 13-gate insulating layer; 14-source-drain layer; 15-active layer; 16-auxiliary electrode layer;

101-first conductive layer; 102-second conductive layer; 103-semiconductor layer; 104-polysilicon layer; 105-protective layer.

Detailed ways

The present application is described in detail below, and examples of embodiments of the present application are shown in the drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. Also, detailed descriptions of known technologies will be omitted if they are not necessary to illustrate the features of the present application. The embodiments described below by referring to the figures are exemplary only for explaining the present application, and are not construed as limiting the present application.

Those skilled in the art will understand that unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the word "comprising" used in the specification of the present application refers to the presence of said features, integers, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more other features, Integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Additionally, "connected" or "coupled" as used herein may include wireless connection or wireless coupling. The expression "and/or" used herein includes all or any elements and all combinations of one or more associated listed items.

The inventors of the present application considered that in existing transistors using metal oxides such as IGZO as active layer materials, considering the conductivity and manufacturing cost, as shown in Figure 1, the source electrically connected to the active layer 15 The drain layer 14 is usually made of copper or aluminum. However, the source-drain layer 14 made of copper or aluminum is prone to oxidation when in contact with the active layer 15, and a layer of oxide film with higher resistance is formed on the surface of the source-drain layer 14 in contact with the active layer 15, causing the source Between the drain layer 14 and the active layer 15 is no longer an ohmic contact with good conductivity, but a Schottky contact. Therefore, the contact resistance between the source-drain layer 14 and the active layer 15 increases, which adversely affects the performance of the transistor 10 .

The transistor, its manufacturing method, and semiconductor device provided by the present application aim to solve the above technical problems in the prior art.

The transistor, its manufacturing method, and semiconductor device provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

The embodiment of the present application provides a transistor 10. The structure of the transistor 10 is shown in FIG. 2, including:

A substrate 11, a gate layer 12, a source-drain layer 14, and an active layer 15 arranged on one side of the substrate 11, the material of the active layer 15 includes a semiconductor oxide;

Wherein, an auxiliary electrode layer 16 is provided between the active layer 15 and the source-drain layer 14, and the orthographic projection of the auxiliary electrode layer 16 on the substrate 11 is respectively the sum of the orthographic projection of the source-drain layer 14 on the substrate 11. The orthographic projection of the source layer 15 on the substrate 11 overlaps;

The auxiliary electrode layer 16 is in ohmic contact with the active layer 15 ; or, the auxiliary electrode layer 16 is in ohmic contact with the source-drain layer 14 .

Specifically, the material of the substrate 11 includes semiconductor materials such as silicon, or insulating materials such as glass, which can be determined according to actual conditions (when the substrate 11 is made of glass, the transistor 10 is a thin film transistor 10). The gate layer 12 is located on one side of the substrate 11 , and the gate insulating layer 13 is located on a side of the gate layer 12 away from the substrate 11 and covers the gate layer 12 . The active layer 15 is located on the side of the gate insulating layer 13 away from the substrate 11, and the material of the gate insulating layer 13 includes materials with good insulating properties such as silicon oxide, silicon nitride or aluminum oxide, so as to make the active layer 15 and the gate layer 12 are insulated from each other. The source-drain layer 14 is arranged on the side of the gate insulating layer 13 away from the substrate 11, the auxiliary electrode layer 16 is arranged between the source-drain layer 14 and the active layer 15, and the source-drain layer 14 is located on the side of the active layer 15. At both ends, the region where the active layer 15 staggers from the source and drain layers 14 is the channel region, and the material of the active layer 15 includes metal oxides such as indium gallium zinc oxide. When the gate opening voltage is loaded on the gate layer 12, the channel region is turned on, and the source-drain layer 14 on the left in FIG. 2 is electrically connected to the source-drain layer 14 on the right, and the transistor 10 is turned on; When the gate-off voltage is applied, the channel region is disconnected, and the source-drain layer 14 on the left and the source-drain layer 14 on the right in FIG. 2 are insulated from each other.

After the auxiliary electrode layer 16 is provided, the contact area between the source-drain layer 14 and the active layer 15 is reduced or there is no direct contact between the source-drain layer 14 and the active layer 15, as shown in FIGS. 2 and 3 , The electrical connection between the source-drain layer 14 and the active layer 15 is mainly realized through the auxiliary electrode layer 16 . Since the auxiliary electrode layer 16 is an ohmic contact with the active layer 15; or, the auxiliary electrode layer 16 and the source-drain layer 14 are in an ohmic contact (the ohmic contact is a contact with less resistance between the metal and the semiconductor. ). Therefore, the contact resistance between the source-drain layer 14 and the active layer 15 caused by the oxidation of the contact surface between the source-drain layer 14 and the active layer 15 is avoided, ensuring that the source-drain layer 14 and the active layer 14 are connected to each other. Good electrical connection between layers 15 enables transistor 10 to have good performance.

Optionally, in the embodiment of the present application, as shown in FIG. 2 , the transistor 10 includes a gate insulating layer 13;

a gate layer 12, disposed on one side of the substrate 11;

The gate insulating layer 13 is arranged on the side of the gate layer 12 away from the substrate 11, and the gate insulating layer 13 covers the gate layer 12;

The source-drain layer 14 is disposed on the side of the gate insulating layer 13 away from the substrate 11;

The active layer 15 is disposed on a side of the source-drain layer 14 away from the substrate 11 .

As shown in FIG. 2, the transistor 10 has a bottom-gate structure, that is, the gate layer 12 is located below the active layer 15, so the gate layer 12 can block the light at the bottom, preventing the active layer 15 from being illuminated and affecting the performance of the transistor. In addition, there is no need to additionally arrange a light-shielding layer, which saves the production cost. It should be noted that the transistor 10 may also be a top-gate structure, that is, the gate layer is located above the active layer (not shown in the figure). When the gate layer is above the active layer, a light-shielding layer can be provided under the active layer to prevent the bottom light from irradiating the active layer and affecting the performance of the transistor. The relative position between the gate layer 12 and the active layer 15 in the transistor 10 can be determined according to actual conditions, and is not limited here.

There are different ways to realize the ohmic contact between the auxiliary electrode layer 16 and the active layer 15 ; or the ohmic contact between the auxiliary electrode layer 16 and the source-drain layer 14 . Optionally, in some embodiments of the present application, there is an ohmic contact between the auxiliary electrode layer and the source-drain layer, and the material of the auxiliary electrode layer 16 includes doped polysilicon. When making the auxiliary electrode layer 16 , firstly a polysilicon layer is formed on the side of the source-drain layer 14 away from the substrate 11 , and then the polysilicon layer is doped to form the auxiliary electrode layer 16 . The auxiliary electrode layer 16 formed after the doping treatment has a linear and symmetrical current-voltage relationship with the contact of the source-drain layer 14 approximately, and has a small contact resistance, so the auxiliary electrode layer 16 and the source-drain layer There is an ohmic contact between the electrode layers 14, and there is good electrical conductivity between the auxiliary electrode layer 16 and the source-drain layer 14. Since the auxiliary electrode layer 16 and the active layer 15 are all semiconductor materials, the auxiliary electrode layer 16 and the active layer 15 contacts, under certain conditions (transistor 10 is in the open state), carriers can migrate between the active layer 15 and the auxiliary electrode layer 16, that is, there can be a good flow between the active layer 15 and the auxiliary electrode layer 16. Conductivity, and then make the source-drain layer 14 and the active layer 15 also have good conductivity, avoiding the resistance between the two when the source-drain layer 14 and the active layer 15 are in direct contact will affect the transistor 10 performance.

Optionally, in other embodiments of the present application, an ohmic contact is made between the auxiliary electrode layer and the active layer, and the material of the auxiliary electrode layer 16 includes any one of gold, silver and iron. When gold or silver is used as the material of the auxiliary electrode layer 16, since gold and silver are relatively stable in nature and difficult to be oxidized, an ohmic contact with low resistance can be ensured between the auxiliary electrode layer 16 and the active layer 15. Both the auxiliary electrode layer 16 and the source-drain layer 14 are metal, so there is good electrical conductivity between the auxiliary electrode layer 16 and the source-drain layer 14, and thus there is good electrical conductivity between the source-drain layer 14 and the active layer 15. The electrical conductivity avoids a large resistance between the source and drain layers 14 and the active layer 15 when they are in direct contact. At the same time, due to the small volume of the auxiliary electrode layer 16 , the high manufacturing cost of the transistor 10 caused when the entire source-drain layer 14 is made of gold or silver is avoided. It should be noted that, in addition to gold or silver, the material of the auxiliary electrode layer 16 can also be other metals with good electrical conductivity and difficult to be oxidized, which can be determined according to actual conditions.

When iron is used as the material of the auxiliary electrode layer 16, although iron is also prone to oxidation, the material (such as iron tetroxide) produced by iron after oxidation has a small resistance and still has good conductivity, so the auxiliary electrode can be guaranteed The ohmic contact between the layer 16 and the active layer 15 ensures good electrical conductivity between the source-drain layer 14 and the active layer 15 . It should be noted that, in addition to iron, the material of the auxiliary electrode layer 16 may also be other metals with low resistance after oxidation, or the material of the auxiliary electrode layer 16 may be a metal oxide with low resistance. When the auxiliary electrode layer 16 is made of a metal oxide material, it is necessary to ensure that its resistivity is small. Optionally, the auxiliary electrode layer and the source-drain layer are in ohmic contact, and the resistivity of the metal oxide material is less than 10 ^-6 ohm. m, so that the electrical conductivity between the source-drain layer 14 and the active layer 15 can meet the requirement.

As shown in FIG. 3, in some embodiments of the present application, the auxiliary electrode layer 16 covers the surface of the source-drain layer 14 facing the active layer 15, even if there is no direct contact between the source-drain layer 14 and the active layer 15, The source-drain layer 14 is electrically connected to the active layer 15 through the auxiliary electrode layer 16 . By making the auxiliary electrode layer cover the surface of the source-drain layer 14 facing the active layer 15, it is further avoided that the surface of the source-drain layer 14 is oxidized and forms a Schottky contact with a larger resistance between the active layer 15, ensuring Good electrical conductivity between the source-drain layer 14 and the active layer 15 is ensured.

Optionally, in some embodiments of the present application, as shown in FIG. 4 , the transistor 10 is provided with a protective layer 105 on the side of the active layer 15 away from the substrate 11, the protective layer 105 covers the active layer 15, and protects The material of layer 105 is selected from materials with good insulation performance and mechanical strength. After the protective layer 105 is provided, the active layer 15 can be isolated from the air, preventing the properties of the active layer 15 from changing, and preventing the active layer 15 from being damaged due to impact. As shown in FIG. 5 , a plurality of transistors 10 can be stacked according to actual usage conditions.

Based on the same inventive concept, an embodiment of the present application further provides a semiconductor device, which includes the above-mentioned transistor 10 provided in the embodiment of the present application. Since the semiconductor device includes the above-mentioned transistor 10 provided by the embodiment of the present application, the semiconductor device has the same beneficial effect as that of the transistor 10 , which will not be repeated here.

Based on the same inventive concept, the embodiment of the present application also provides a manufacturing method of the transistor 10, as shown in FIG. 6, the manufacturing method includes:

S101. Provide a substrate;

S102, fabricating a gate layer on one side of the substrate through a patterning process;

S103, making a gate insulating layer on the side of the gate layer away from the substrate, so that the gate insulating layer covers the gate layer;

S104, sequentially fabricate a source-drain layer and an auxiliary electrode layer on the side of the gate insulating layer away from the substrate, and connect the source-drain layer to the auxiliary electrode layer;

S105. Fabricate an active layer on the side of the auxiliary electrode layer away from the substrate, and connect the active layer to the auxiliary electrode layer, wherein the auxiliary electrode layer is in ohmic contact with the active layer; or, the auxiliary electrode layer is connected to the source and drain The layers are in ohmic contact.

In the manufacturing method of the transistor 10 provided in the embodiment of the present application, the auxiliary electrode layer 16 is provided between the active layer 15 and the source-drain layer 14, and an ohmic contact is made between the auxiliary electrode layer 16 and the active layer 15 or, between the auxiliary electrode layer 16 and the source-drain layer 14 is an ohmic contact, and the active layer 15 and the source-drain layer 14 are electrically connected by the auxiliary electrode layer 16, avoiding the active layer 15 and the source-drain layer When the layers 14 are in direct contact, the contact resistance between the source and drain layers 14 and the active layer 15 increases after the surface of the source and drain layers 14 is oxidized, which ensures the performance of the transistor 10 .

Specifically, the patterning process in the embodiment of the present application includes photoresist coating, exposure, development, etching and part or all of the photoresist removal process.

In the first specific implementation mode, in the embodiment of the present application, the source-drain layer 14 and the auxiliary electrode layer 16 are sequentially formed on the side of the gate insulating layer 13 away from the substrate 11, including:

making a first conductive layer on the side of the gate insulating layer away from the substrate;

making a second conductive layer on the side of the first conductive layer away from the substrate;

The first conductive layer and the second conductive layer are polished by a chemical mechanical polishing process until the side of the gate insulating layer away from the substrate is partially exposed to form a source and drain layer and an auxiliary electrode layer, wherein the auxiliary electrode layer is connected to the active The layers are in ohmic contact.

The specific process of manufacturing the transistor 10 in the first embodiment will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 7 a , first, a substrate 11 is provided, and the material of the substrate 11 includes insulating materials such as glass or semiconductor materials such as silicon.

As shown in FIG. 7 b , next, a gate layer 12 is formed on one side of the substrate 11 through a patterning process, and the material of the gate layer 12 includes materials with good electrical conductivity such as copper or aluminum.

As shown in FIG. 7 c , next, a gate insulating layer 13 is formed on the side of the gate layer 12 away from the substrate 11 , and the gate insulating layer 13 covers the gate layer 12 . The material of the gate insulating layer 13 includes materials with good insulating properties such as silicon oxide or silicon nitride, which can be formed by chemical vapor deposition or plasma-enhanced atomic layer deposition, and can be determined according to actual conditions.

As shown in FIG. 7 d , next, a first conductive layer 101 is formed on the side of the gate insulating layer 13 away from the substrate 11 , and the material of the first conductive layer 101 includes aluminum or copper.

As shown in FIG. 7 e , next, a second conductive layer 102 is formed on the side of the first conductive layer 101 away from the substrate 11 , and the material of the second conductive layer 102 includes gold, silver or iron.

As shown in FIG. 7f, then, the first conductive layer 101 and the second conductive layer 102 are polished by a chemical mechanical polishing process until the side of the gate insulating layer 13 away from the substrate 11 is partially exposed, so as to form the source and drain layers 14 and auxiliary electrode layer 16. Specifically, the change of the friction force can be detected during grinding, and the grinding is stopped when the gate insulating layer 13 is ground (the friction force is different from the grinding of the first conductive layer 101 and the second conductive layer 102 at this time). Since the material of the auxiliary electrode layer 16 is a metal that is not easily oxidized or a metal that still has good conductivity after oxidation, and the material of the active layer 15 is a semiconductor, the auxiliary electrode layer 16 and the active layer 15 are in ohmic contact.

As shown in FIG. 7 g , next, the active layer 15 is formed on the side of the auxiliary electrode layer 16 and the gate insulating layer 13 away from the substrate 11 to complete the fabrication of the transistor 10 . The material of the active layer 15 includes IGZO.

In the second specific implementation manner, in the embodiment of the present application, the source-drain layer 14 and the auxiliary electrode layer 16 are fabricated sequentially on the side of the gate insulating layer 13 away from the substrate 11, including:

making a first conductive layer on the side of the gate insulating layer away from the substrate;

making a semiconductor layer on the side of the first conductive layer away from the substrate;

The first conductive layer and the semiconductor layer are polished by a chemical mechanical polishing process until the side of the gate insulating layer away from the substrate is partially exposed to form a source-drain layer and an auxiliary electrode layer, wherein the auxiliary electrode layer and the source-drain layer There is an ohmic contact between them.

The specific process of manufacturing the transistor 10 in the second embodiment will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 8a, a substrate 11 is provided, and a gate layer 12, a gate insulating layer 13, and a first conductive layer 101 are sequentially formed on one side of the substrate 11. The specific process can refer to the first specific implementation mode. method, which will not be repeated here.

As shown in FIG. 8 b , a polysilicon layer 104 is formed on the side of the first conductive layer 101 away from the substrate 11 .

As shown in FIG. 8 c , the polysilicon layer 104 is doped to form a semiconductor layer 103 .

As shown in FIG. 8d, the semiconductor layer 103 and the first conductive layer 101 are polished by a chemical mechanical polishing process until the side of the gate insulating layer 13 away from the substrate 11 is partially exposed, so as to form the source and drain layers 14 and the auxiliary electrode layer. 16. Specifically, the change of the friction force can be detected during grinding, and the grinding is stopped when the gate insulating layer 13 is ground (the friction force is different from that of grinding the first conductive layer 101 and the semiconductor layer 103 at this time). Since the material of the auxiliary electrode layer 16 is a semiconductor, the material of the source and drain layers 14 is metal, and the auxiliary electrode layer 16 has a certain doping concentration, carriers can pass through the potential barrier by virtue of the tunnel effect, so that the auxiliary electrode layer 16 An ohmic contact with a lower resistance is formed with the source-drain layer 14 .

As shown in FIG. 8 e , next, the active layer 15 is formed on the side of the auxiliary electrode layer 16 and the gate insulating layer 13 away from the substrate 11 to complete the fabrication of the transistor 10 .

In the third specific implementation mode, in the embodiment of the present application, the source-drain layer and the auxiliary electrode layer are sequentially formed on the side of the gate insulating layer away from the substrate, including:

Fabricate source and drain layers on the side of the gate insulating layer away from the substrate through a patterning process;

An auxiliary electrode layer is fabricated on the side of the source and drain layers away from the substrate through a patterning process.

As shown in FIG. 9a, a substrate 11 is provided, and a gate layer 12 and a gate insulating layer 13 are sequentially fabricated on one side of the substrate 11. For the specific process, refer to the method in the first specific embodiment, where No longer.

As shown in FIG. 9 b , the source-drain layer 14 is formed on the side of the gate insulating layer 13 away from the substrate 11 through a patterning process, and the material of the source-drain layer 14 includes aluminum or copper.

As shown in FIG. 9 c , the auxiliary electrode layer 16 is formed on the side of the source-drain layer 14 away from the substrate 11 through a patterning process. The material of the auxiliary electrode layer 16 includes doped polysilicon, or metals such as gold and silver that are difficult to be oxidized, or metals such as iron that still have good conductivity after oxidation.

As shown in FIG. 9 d , the active layer 15 is formed on the side of the auxiliary electrode layer 16 and the gate insulating layer 13 away from the substrate 11 to complete the fabrication of the transistor 10 .

By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

1. The transistor 10 in the embodiment of the present application includes a substrate 11, a gate layer 12 disposed on one side of the substrate 11, a source-drain layer 14, and an active layer 15, and the material of the active layer 15 includes a semiconductor oxide; Wherein, an auxiliary electrode layer 16 is provided between the active layer 15 and the source-drain layer 14, and the orthographic projection of the auxiliary electrode layer 16 on the substrate 11 is respectively the sum of the orthographic projection of the source-drain layer 14 on the substrate 11. The orthographic projection of the source layer 15 on the substrate 11 overlaps, and the auxiliary electrode layer 16 is in ohmic contact with the active layer 15 ; or, the auxiliary electrode layer 16 is in ohmic contact with the source-drain layer 14 . By setting the auxiliary electrode layer 16 between the active layer 15 and the source-drain layer 14, the active layer 15 and the source-drain layer 14 are electrically connected through the auxiliary electrode layer 16, avoiding the active layer 15 and the source-drain layer. When the electrode layer 14 is in direct contact, the contact resistance between the source and drain layer 14 and the active layer 15 increases after the surface of the source and drain layer 14 is oxidized, which ensures the performance of the transistor 10 .

2. In the embodiment of the present application, the transistor 10 includes a gate insulating layer 13; the gate layer 12 is arranged on the side of the substrate 11, and the gate insulating layer 13 is arranged on the side of the gate layer 12 away from the substrate 11, The gate insulating layer 13 covers the gate layer 12; the source-drain layer 14 is arranged on the side of the gate insulating layer 13 away from the substrate 11, and the active layer 15 is arranged on the side of the source-drain layer 14 away from the substrate 11 . By making the transistor 10 a bottom-gate structure, that is, the gate layer 12 is located under the active layer 15, the gate layer 12 can block the bottom light and prevent the active layer 15 from being affected by light on the performance of the transistor. In addition, there is no need to additionally arrange a light-shielding layer, which saves the production cost.

3. In some embodiments of the present application, the material of the auxiliary electrode layer 16 includes doped polysilicon. When fabricating the auxiliary electrode layer 16 , the polysilicon layer 104 is first formed on the side of the source-drain layer 14 away from the substrate 11 , and then the polysilicon layer 104 is doped to form the auxiliary electrode layer 16 . The auxiliary electrode layer 16 formed after the doping treatment has a linear and symmetrical current-voltage relationship with the contact of the source-drain layer 14 approximately, and has a small contact resistance, so the auxiliary electrode layer 16 and the source-drain layer The electrode layers 14 are in ohmic contact, and the auxiliary electrode layer 16 and the source-drain layer 14 have good conductivity, so that the source-drain layer 14 and the active layer 15 also have good conductivity, avoiding the A large resistance between the source-drain layer 14 and the active layer 15 affects the performance of the transistor 10 .

4. In other embodiments of the present application, the material of the auxiliary electrode layer 16 includes any one of gold, silver and iron. When the auxiliary electrode layer 16 is made of gold or silver, since the properties of gold and silver are relatively stable and difficult to be oxidized, it can ensure an ohmic contact with a small resistance between the auxiliary electrode layer 16 and the active layer 15, thereby making There is good electrical conductivity between the source-drain layer 14 and the active layer 15 . At the same time, due to the small area of the auxiliary electrode layer 16 , the high manufacturing cost of the transistor 10 caused when the entire source-drain layer 14 is made of gold or silver is avoided.

5. In some embodiments of the present application, the auxiliary electrode layer 16 covers the surface of the source-drain layer 14 facing the active layer 15, even if there is no direct contact between the source-drain layer 14 and the active layer 15, the source-drain layer 14 is electrically connected to the active layer 15 through the auxiliary electrode layer 16 . By making the auxiliary electrode layer cover the surface of the source-drain layer 14 facing the active layer 15, it is further avoided to form a Schottky contact with a higher resistance between the surface of the source-drain layer 14 and the active layer 15 after oxidation, ensuring Good electrical conductivity between the source-drain layer 14 and the active layer 15 is ensured.

In the description of this application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", The orientations or positional relationships indicated by "top", "bottom", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or implying References to devices or elements must have a particular orientation, be constructed, and operate in a particular orientation and therefore should not be construed as limiting the application.

The terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present application, unless otherwise specified, "plurality" means two or more.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above description is only part of the implementation of the present application, and it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, some improvements and modifications can also be made, and these improvements and modifications should also be It is regarded as the scope of protection of this application.

Claims (10)

1. A transistor, comprising:

a substrate, a grid electrode layer, a source drain electrode layer and an active layer which are arranged on one side of the substrate, wherein the material of the active layer comprises a semiconductor oxide;

an auxiliary electrode layer is arranged between the active layer and the source drain electrode layer, and orthographic projection of the auxiliary electrode layer on the substrate is overlapped with orthographic projection of the source drain electrode layer on the substrate and orthographic projection of the active layer on the substrate respectively;

ohmic contact is formed between the auxiliary electrode layer and the active layer; or ohmic contact is formed between the auxiliary electrode layer and the source/drain electrode layer.

2. The transistor of claim 1, comprising a gate insulating layer;

the grid electrode layer is arranged on one side of the substrate;

the grid insulation layer is arranged on one side, far away from the substrate, of the grid layer, and the grid insulation layer covers the grid layer;

the source-drain electrode layer is arranged on one side of the gate insulating layer, which is far away from the substrate;

the active layer is arranged on one side of the source-drain electrode layer away from the substrate.

3. The transistor of claim 2, wherein the material of the auxiliary electrode layer comprises doped polysilicon when ohmic contact is made between the auxiliary electrode layer and the source drain layer; alternatively, the material of the auxiliary electrode layer comprises a metal oxide having a resistivity of less than 10 ^-6 Ohm-meter.

4. The transistor according to claim 2, wherein when ohmic contact is made between the auxiliary electrode layer and the active layer, a material of the auxiliary electrode layer includes gold, silver, and iron.

5. The transistor according to any one of claims 1 to 4, wherein the auxiliary electrode layer covers a surface of the source-drain layer facing the active layer.

6. A semiconductor device comprising the transistor according to any one of claims 1 to 5.

7. A method of fabricating a transistor, comprising:

providing a substrate;

manufacturing a grid electrode layer on one side of the substrate through a patterning process;

manufacturing a gate insulating layer on one side of the gate layer far away from the substrate, so that the gate insulating layer covers the gate layer;

sequentially manufacturing a source drain electrode layer and an auxiliary electrode layer on one side of the gate insulating layer, which is far away from the substrate, wherein the source drain electrode layer is connected with the auxiliary electrode layer;

an active layer is manufactured on one side, far away from the substrate, of the auxiliary electrode layer, and the active layer is connected with the auxiliary electrode layer, wherein ohmic contact is formed between the auxiliary electrode layer and the active layer; or ohmic contact is formed between the auxiliary electrode layer and the source/drain electrode layer.

8. The method of claim 7, wherein sequentially forming the source and drain electrode layers and the auxiliary electrode layer on the side of the gate insulating layer away from the substrate comprises:

manufacturing a first conductive layer on one side of the gate insulating layer away from the substrate;

manufacturing a second conductive layer on one side of the first conductive layer far away from the substrate;

and grinding the first conductive layer and the second conductive layer by a chemical mechanical grinding process until one side of the gate insulating layer far away from the substrate is partially exposed, so as to form a source drain electrode layer and an auxiliary electrode layer, wherein ohmic contact is formed between the auxiliary electrode layer and the active layer.

9. The method of claim 7, wherein sequentially forming the source and drain electrode layers and the auxiliary electrode layer on the side of the gate insulating layer away from the substrate comprises:

manufacturing a first conductive layer on one side of the gate insulating layer away from the substrate;

manufacturing a semiconductor layer on one side of the first conductive layer away from the substrate;

and grinding the first conductive layer and the semiconductor layer by a chemical mechanical grinding process until one side part of the gate insulating layer, which is far away from the substrate, is exposed so as to form a source drain electrode layer and an auxiliary electrode layer, wherein ohmic contact is formed between the auxiliary electrode layer and the source drain electrode layer.

10. The method of claim 7, wherein sequentially forming the source and drain electrode layers and the auxiliary electrode layer on the side of the gate insulating layer away from the substrate comprises:

a source drain electrode layer is manufactured on one side, far away from the substrate, of the gate insulating layer through a composition process;

and manufacturing an auxiliary electrode layer on one side of the source drain electrode layer far away from the substrate through a patterning process.

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