CN110915307A - Electronic component mounting substrate and method for producing the same - Google Patents
Electronic component mounting substrate and method for producing the same Download PDFInfo
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- CN110915307A CN110915307A CN201880032995.6A CN201880032995A CN110915307A CN 110915307 A CN110915307 A CN 110915307A CN 201880032995 A CN201880032995 A CN 201880032995A CN 110915307 A CN110915307 A CN 110915307A
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- layer
- electronic component
- laminated
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Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The substrate of the present invention comprises: an insulating layer (11); and a conductor (12) provided on the insulating layer (11). Wherein at least a part of the bottom surface and the side surface of the conductor (12) is closer to the rear surface side of the insulating layer (11) than to the front surface side of the insulating layer (11).
Description
Technical Field
The present invention relates to a substrate for mounting an electronic component and a method for manufacturing the same.
Background
In recent years, with the trend toward high-density mounting of electronic devices, there has been a general demand in the industry for achieving high-density, small-sized, light-weight, and multi-layered conductors on electronic component mounting boards. However, when the conductors are mounted at high density or are miniaturized, if the adhesion between the insulating layer and the conductors formed on the insulating layer is not sufficiently ensured, the adhesion between the insulating layer and the conductors cannot be sufficiently ensured. In addition, when the insulating layer has a plurality of conductors, the adhesion between the insulating layer and the conductor is also insufficient.
[ Prior Art document ]
[ patent document 1 ] Japanese patent laid-open No. 2012-169600
However, when a printed board having a small thickness is to be formed or when the front surface of the insulating layer and the conductor are made to adhere to each other by the semi-additive method, the adhesion between the insulating layer and the conductor cannot be sufficiently secured. In addition, when the insulating layer is thin, conductor peeling is also likely to occur. When the adhesion between the insulating layer and the conductor is insufficient, the printed board cannot be originally manufactured, and even if the printed board is manufactured, the problem of low yield cannot be avoided.
In view of the above circumstances, an object of the present invention is to provide an electronic component mounting board capable of improving adhesion.
Disclosure of Invention
The present invention achieves the above object by embedding a conductor formed on an insulating layer in the insulating layer. When the combined layer of the insulating layer and the conductor forms one or more layers on the insulating layer, at least a part of the conductor included in at least one arbitrary combined layer is buried toward the insulating layer.
The electronic component mounting substrate described in the present invention may be any substrate that can mount an electronic component and has an insulating layer on which a conductor is formed. In the present invention, a substrate having a conductor formed on an insulating layer is referred to as an electronic component mounting substrate. Further, the present invention includes: the electronic component mounted on the electronic component mounting board, the electronic module, and the mounting apparatus according to the present invention are provided. For example, the mounting device of the present invention is: the present invention relates to an electronic component mounting substrate and an electronic component mounting apparatus that performs a predetermined process using the electronic component mounting substrate. Therefore, the present invention can be applied to all electronic components, and devices that operate using the electronic component mounting board.
Effects of the invention
According to the present invention, since at least a part of the conductor is embedded in the insulating layer, the adhesion of the electronic component mounting board, that is, the peel strength can be improved. Thus, the present invention can prevent a decrease in yield in manufacturing an electronic component mounting board, and can improve the durability of the electronic component mounting board, thereby improving the quality of the electronic component mounting board as a whole. In addition, the present invention can improve the reliability of an electronic component, an electronic module, and a device that operate using the wiring board of the present invention.
Drawings
Fig. 1 is an explanatory diagram for explaining a conductor forming process for forming a conductor on an insulating layer.
Fig. 2 is an explanatory diagram for explaining a conductor forming process for forming a conductor on an insulating layer.
Fig. 3 is an explanatory diagram for explaining a press-fitting process for press-fitting or sinking a conductor into an insulating layer.
Fig. 4 is a diagram for explaining the heating step.
Fig. 5 is a diagram for explaining the heating step.
Fig. 6 is a diagram for explaining the heating step.
Fig. 7 is a diagram for explaining the heating step.
Fig. 8 is a diagram for explaining the heating step.
Fig. 9 is a schematic explanatory view when heating.
Fig. 10 is a diagram for explaining a state after the conductor press-fitting step.
Fig. 11 is a diagram for explaining a state after the conductor press-fitting step.
Fig. 12 is an explanatory diagram for explaining a press-fitting process for press-fitting or sinking a conductor into an insulating layer.
Fig. 13 is an explanatory diagram for explaining a press-fitting process for press-fitting or sinking a conductor into an insulating layer.
Fig. 14 is a diagram for explaining a state after the conductor press-fitting step.
Fig. 15 is a diagram for explaining a state after the conductor press-fitting step.
Fig. 16 is a diagram for explaining the VIA formation step.
Fig. 17 is a sectional view showing an example of the electronic component mounting substrate according to the second embodiment.
Fig. 18 is a sectional view showing an example of a boundary portion between the electroless-plated layer and the conductor.
Fig. 19 is an enlarged view showing a first example of the unevenness.
Fig. 20 is an enlarged view showing the second example unevenness.
Fig. 21 is a schematic diagram showing the regularity of the unevenness of the front surface of the insulating layer.
Fig. 22 is an explanatory view of a method for manufacturing the electronic component mounting board according to the third embodiment.
Fig. 23 is a sectional view showing an example of a manufacturing method for manufacturing a conductor having a conductor recess.
Fig. 24 is a sectional view showing an example of a manufacturing method for manufacturing a conductor having a conductor convex portion.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are merely examples of the present invention, and the present invention is not limited to the embodiments described below. In the present invention, the same reference numerals are used for the same components as those shown in the drawings.
(first embodiment)
In this embodiment, a case where the insulator layer is an insulating layer will be described. The method for manufacturing an electronic component mounting substrate according to the present embodiment includes the conductor forming step and the press-fitting step in this order. Thus, the present invention can improve the adhesion between the insulating layer and the conductor, that is, the peel strength.
Fig. 1(a) to 1(c) show a conductor forming process for forming a conductor on an insulating layer in the present invention. In fig. 1(a) to 1(c), 11 denotes an insulating layer, 12 denotes a conductor, 121 denotes a metal foil, and 122 denotes metal plating. In fig. 1, the vertical direction is the thickness direction of the substrate, the upper end face is the front face, and the lower end face is the rear face.
The insulating layer 11 is an insulator that can be used for a printed board. The material for the insulating layer 11 may be, for example, resin, or any material having insulating properties such as glass or ceramic. The insulating layer 11 may be formed by mixing two or more kinds of insulating materials. For example, fibrous or granular insulators may be contained in the insulating layer 11.
The insulating layer 11 may be an insulator in which a base material is mixed with a resin. The resin is preferably a thermosetting resin or an ultraviolet-curable resin. If the resin has a certain heat resistance, a thermoplastic resin may be used. As the thermosetting resin, polyimide resin, epoxy resin, phenol resin, cyanate resin can be exemplified. The thermal deformation temperature of the thermoplastic resin may be 50 degrees or higher. The higher the deformation temperature, the better. Examples of the substrate include glass fibers, ceramic particles, and cellulose fibers, and natural products such as spider web fibers may be used. The substrate may not be limited to the above materials. Further, a prepreg impregnated with the resin and semi-cured may be laminated on the glass cloth, and heated and pressurized to form an insulating layer. This is also the same in any of the following embodiments.
The conductor 12 is a conductor layer formed of any material that can be used as a conductor of a printed circuit board, and includes a metal foil, a metal plating layer, and a rolled sheet. The material of the metal foil 121 and the metal plating 122 constituting the conductor 12 may be any metal, alloy, or paste having conductivity. Alternatively, any substance other than metals such as carbon and ceramics may be used as part or all of the conductor 12 as long as it has conductivity. As the metal suitable for the conductor 12, copper, gold, silver, aluminum, nickel, or an alloy or paste containing these metals at the maximum in mass% may be exemplified, but not limited thereto. This is also the same in any of the following embodiments.
First, metal plating is performed on the metal foil 121 laid on the insulating layer 11 (fig. 1 a) (fig. 1 b). Next, a patterned conductor 12 is formed on the insulating layer 11 by a well-known plating method (plating method) and a Pattern plating method (Pattern plating method) (fig. 1 (c)). The conductor 12 thus formed includes a metal foil and a metal plating layer plated on the metal foil.
Fig. 2(a) to 2(d) show another conductor forming process for forming a conductor on an insulating layer in the present invention. This manufacturing method is called semi-additive method. In fig. 2(a) to 2(d), 11 denotes an insulating layer, 12 denotes a conductor, and 13 denotes a pattern resist.
Examples of the material of the pattern resist 13 include a photosensitive dry film, a liquid resist, and an ED resist, but are not limited thereto. This is also the same in any of the following embodiments. These materials are all of a photo-curing type or a photo-dissolving type.
Next, a pattern resist is applied on the insulating layer 11 (fig. 2(a)), and finally the pattern resist except for the conductor portion is removed (fig. 2 (b)). Then, a conductor is grown by electroless plating on the remaining portion other than the patterned resist 13 (fig. 2 (c)). Next, the patterned resist 13 is removed, leaving the conductor 12. At this time, as shown in fig. 17 described later, in a cross section perpendicular to the insulating layer 11, a corner 12E of the upper end surface (top surface) of the conductor 12 has an arc shape. In the conductor forming step, the conductor 12 is formed on the insulating layer 11 after patterning. The conductor forming step is not limited to the above method.
Fig. 3(a) to 3(b) show a press-fitting process of press-fitting a conductor into an insulating layer in the present invention. In fig. 3(a) to 3(b), 11 denotes an insulating layer, and 12 denotes a conductor. When the conductor 12 (fig. 3(a)) formed on the front surface of the insulating layer 11 is mechanically pressed in the direction of the insulating layer 11, a part of the conductor 12 is buried in the front surface of the insulating layer 11 (fig. 3 (b)). Fig. 3(b) shows an example of the electronic component mounting board of the present invention. The mechanical press-fitting is performed by, for example, using a press having a flat surface as a press-fitting surface to press the conductor 12 formed on the front surface of the insulating layer 11 entirely or partially into the insulating layer 11.
By pressing the conductor 12 into the insulating layer 11, not only the bottom surface of the conductor 12 but also at least a part of the side surface of the conductor 12 is in close contact with the insulating layer 11, thereby increasing the peel strength between the insulating layer 11 and the conductor 12.
The method of realizing the electronic component mounting board in which the conductor 12 is embedded in the insulating layer 11 is not limited to the method in which the conductor 12 is mechanically embedded in the insulating layer 11. For example, in the press-fitting step, both or either one of the conductor 12 and the insulating layer 11 may be heated to sink the conductor 12 into the insulating layer 11. This allows the conductor 12 to be embedded in the insulating layer 11 without applying a force to the conductor 12.
In this case, although it is not necessary to press the conductor 12 into the insulating layer 11, the conductor 12 may be pressed into the insulating layer 11 with a weak force. In this way, the position of the upper end face, which is the top face of the conductor 12, can be easily controlled. As described above, the press-fitting in the present invention also includes press-fitting performed with a weak force. Next, as an example of the press-fitting step, an example including a heating step of heating both or one of the conductor 12 and the insulating layer 11 in addition to the step of mechanically press-fitting the conductor 12 into the insulating layer 11 in the press-fitting step will be described.
In the press-fitting step, when the conductor 12 is mechanically press-fitted into the insulating layer 11, both or either one of the conductor 12 and the insulating layer 11 may be heated. This is effective in the case where the insulating layer is too hard or the peel strength is desired to be further improved. Heating is achieved by pressing a heater, or irradiating LED light and infrared rays, or hot air blowing. The conductor 12 may be mechanically pressed by using a panel heated by a heater.
Fig. 4, 5, 6, 7, 8 show the heating step. In fig. 4, 5, 6, 7, and 8, 11 denotes an insulating layer, and 12 denotes a conductor. In fig. 4, 5, 6, 7, and 8, (a), (b), and (c) show the order. The heating step with heat may be a step of heating (fig. 4(b)) and mechanically pressing while heating (fig. 4 (c)). The heating may be performed first (fig. 5(b)), and the heating may be stopped and then mechanically pressed (fig. 5 (c)). It is also possible to carry out the heating simultaneously with the mechanical pressing (fig. 6 (b)). First, the press-fitting may be performed mechanically (fig. 7(b)), and the press-fitting may be performed while heating (fig. 7 (c)). The method may further include the steps of first performing mechanical pressing (fig. 8(b)), and then heating after stopping the mechanical pressing (fig. 8 (c)).
Fig. 9(a) shows a schematic view when heating. Since the conductor 12 is a metal and the insulating layer 11 is a resin, the conductor 12 has a larger expansion ratio than the insulating layer 11. Therefore, by heating at an appropriate temperature, the conductor 12 is in close contact with the insulating layer 11, and an anchor effect can be obtained. After that, even if heat is removed (fig. 9(b)), the adhesion between the conductor 12 and the insulating layer 11 is improved compared to before heating. Therefore, the peel strength between the insulating layer 11 and the conductor 12 is increased.
In the press-fitting step, a state of the conductor after press-fitting will be described with reference to fig. 10(a), 10(b), 11(a), 11(b), and 11 (c). Fig. 10(a), 10(b), 11(a), 11(b), and 11(c) are examples of the electronic component mounting board of the present invention. In fig. 10(a), 10(b), 11(a), 11(b), and 11(c), 11 denotes an insulating layer, and 12 denotes a conductor. In these descriptions, as shown in fig. 10 a, a surface of the conductor 12 on a side of the insulating layer 11 (not shown) (a side close to the insulating layer 11) is referred to as a bottom surface, a surface on a side opposite to the bottom surface (a side far from the insulating layer 11) is referred to as an upper end surface (a top surface), a side surface sandwiched between the upper end surface and the bottom surface is referred to as a side surface, a surface on the insulating layer 11 on which the conductor 12 is mounted is referred to as a front surface, and a surface on the opposite side is referred to as a back surface.
The conductor 12 may be pressed until the bottom surface and a part of the side surface of the conductor 12 are located lower than the front surface of the insulating layer 11 (fig. 10 (a)). Since the entire bottom surface and a part of the side surface of the conductor 12 are in close contact with the insulating layer 11, the peel strength between the insulating layer 11 and the conductor 12 is improved. The conductor 12 may be press-fitted until the upper end surface of the conductor 12 is flush with the front surface of the insulating layer 11 (fig. 10 (b)). Since the entire bottom surface and the entire side surface of the conductor 12 are in close contact with the insulating layer 11, the peel strength between the insulating layer 11 and the conductor 12 is further improved.
In fig. 10(a), the side surfaces disposed on both sides of the bottom surface are collectively embedded in the insulating layer 11, but the present invention is not limited thereto, and only one side surface disposed on both sides of the bottom surface may be embedded in the insulating layer 11, for example. Although the upper end surface of the conductor 12 is extended in the x-axis direction in fig. 10(a), the present invention is not limited thereto, and the upper end surface of the conductor 12 may be inclined in the x-axis direction.
In fig. 10(a) and 10(b), the conductor 12 has a rectangular cross-sectional shape, but the conductor 12 according to the present invention may have any cross-sectional shape. For example, the upper end face of the conductor 12 may be curved, and the boundary between the side face and the upper end face may also constitute a continuous curve.
Not only the bottom surface and the side surface of the conductor 12, but also the conductor 12 may be press-fitted to a position where the upper end surface thereof is lower than the front surface of the insulating layer 11 (fig. 11a, 11 b, and 11 c). In fig. 11(a), the conductor 12 is pressed until its upper end surface is positioned lower than the front surface of the insulating layer 11, but the upper end surface of the conductor 12 is exposed. Since the entire bottom surface and the entire side surface of the conductor 12 are in close contact with the insulating layer 11, the peel strength between the insulating layer 11 and the conductor 12 is further improved. In fig. 11(b), the conductor 12 is pressed until its upper end surface is positioned lower than the front surface of the insulating layer 11, but a part of the upper end surface of the conductor 12 is exposed. Since the entire bottom surface, the entire side surface, and a part of the upper end surface of the conductor 12 are in close contact with the insulating layer 11, the peel strength between the insulating layer 11 and the conductor 12 is further improved. In fig. 11(c), the conductor 12 is press-fitted until the upper end surface of the conductor 12 is positioned lower than the front surface of the insulating layer 11, and the upper end surface of the conductor 12 is embedded in the insulating layer 11. Since the entire bottom surface, the entire side surface, and the entire upper end surface of the conductor 12 are in close contact with the insulating layer 11, the peel strength between the insulating layer 11 and the conductor 12 is further improved.
In fig. 10(a), 10(b), and 11(a), three surfaces of the conductor 12 are in close contact with the insulating layer 11. In the case of the same structure in the y-z plane, five sides of the conductor 12 are in close contact with the insulating layer 11. Therefore, in addition to the bottom surface of the conductor 12 extending in the x-axis direction, since a part or the entire side surface of the conductor 12 extending in the y-axis direction is in close contact with the insulating layer 11, the peel strength can be improved against the loads in the x-and z-axis directions applied to the conductor 12.
In fig. 11(b) and 11(c), four surfaces of the conductor 12 are in close contact with the insulating layer 11. In the case of the same structure in the y-z plane, six faces of the conductor 12 are in close contact with the insulating layer 11. Therefore, in addition to the bottom surface of the conductor 12 extending in the x-axis direction, since a part or the entire side surface of the conductor 12 extending in the y-axis direction and a part or the entire upper end surface of the conductor 12 extending in the x-axis direction are in close contact with the insulating layer 11, the peeling strength can be improved against the load in the x-, y-, and z-axis directions applied to the conductor 12.
Although fig. 10 and 11 illustrate the bottom surface of the conductor 12 being in close contact with the insulating layer 11, the present invention is not limited thereto. For example, in fig. 10(a), 10(b), and 11(a), the present invention also includes a configuration in which a part or the entire bottom surface of the conductor 12 is exposed on the back surface of the insulating layer 11, and both surfaces of the conductor 12 are in close contact with the insulating layer 11. In the case of the same structure in the y-z plane, the four sides of the conductor 12 are in close contact with the insulating layer 11. In this case, since a part or the whole of the side surface of the conductor 12 extending in the y-axis direction is in close contact with the insulating layer 11, the peeling strength can be improved against the loads in the x-and z-axis directions applied to the conductor 12.
Fig. 11(b) also includes a configuration in which the entire bottom surface of the conductor 12 is exposed on the back surface of the insulating layer 11, and three surfaces of the conductor 12 are in close contact with the insulating layer 11. In the case of the same structure in the y-z plane, five sides of the conductor 12 are in close contact with the insulating layer 11. In this case, since the upper end surface of a part of the conductor 12 extending in the x-axis direction and a part or the entire side surface of the conductor 12 extending in the y-axis direction are in close contact with the insulating layer 11, the peel strength can be improved against the load in the x, y, and z-axis directions applied to the conductor 12.
Fig. 11(b) also includes a configuration in which a bottom surface of a part of the conductor 12 is exposed on the back surface of the insulating layer 11, and four surfaces of the conductor 12 are in close contact with the insulating layer 11. In the case of the same structure in the y-z plane, six faces of the conductor 12 are in close contact with the insulating layer 11. In this case, since the upper end surface of a part of the conductor 12 extending in the x-axis direction, the entire side surface of the conductor 12 extending in the y-axis direction, and the bottom surface of a part of the conductor 12 extending in the x-axis direction are in close contact with the insulating layer 11, the peeling strength can be improved against the loads in the x-, y-, and z-axis directions applied to the conductor 12.
Next, a multilayer substrate in which an electronic component mounting substrate is formed on an insulating layer as a combined layer of the insulating layer and a conductor will be described as an example. The insulating layer in the following examples is included in a combined layer of at least one layer, and at least a part of a conductor included in the combined layer of at least one layer is buried in the insulating layer. Specifically, an electronic component mounting board to be described below includes: an insulating layer; a conductor formed on the insulating layer; and a combination of at least one set of an insulating layer on the conductor and the insulator substrate and a conductor formed on the insulating layer, wherein at least one of the conductors is buried in the insulating layer or the insulating layer.
In fig. 12(a), 12(b), 12(c), 13(a), 13(b), and 13(c), 11a denotes a stacked insulating layer, 12 denotes a conductor, and 14 denotes a stacked insulating layer. In fig. 12 and 13, as an example of a combination of the laminated insulating layer 14 and the conductor 12, shown are: a combination of stacked insulating layer 14-1 and conductor 12-1, a combination of stacked insulating layer 14-2 and conductor 12-2, and a combination of stacked insulating layer 14-3 and conductor 12-3. The stacked insulating layers 11a, 14 constitute an insulating layer.
In the conductor forming step or the second conductor forming step, a conductor is formed in the insulating multilayer layer 11a or each insulating multilayer layer 14 (fig. 12(a), 12(b), 12(c), 13(a), 13(b), and 13 (c)). In order to form a conductor on the buildup layer, a conductor 12 is formed on the stacked insulating layer 11a (conductor forming step). Further, after the insulating laminated layer 14 is formed on the conductor 12 and the insulating laminated layer 11a, a conductor is further formed on the insulating laminated layer 14 (second conductor forming step), and the second conductor forming step is repeated as many times as necessary.
The material of the stacked insulating layer 14 may be the same as that which can be applied to the stacked insulating layer 11 a. This is the same in any of the following embodiments.
In the press-fitting step of press-fitting or sinking the conductor 12 into the multilayer insulating layer 14 located at the uppermost layer, after the formation of the uppermost multilayer insulating layer 14 (fig. 12(b)), the conductor 12 at the uppermost layer is press-fitted or sunk into the multilayer insulating layer 14 (fig. 12 (c)).
In the press-fitting step of press-fitting or immersing the conductor 12 into the laminated insulating layer 14, or in the press-fitting step of press-fitting or immersing the conductor 12 into the laminated insulating layer 14 located in an intermediate layer, after the conductor 12 is formed on the laminated insulating layer 11a, or after the conductor 12 is formed after the laminated insulating layer 14 is formed, the conductor 12 is mechanically pressed into the laminated insulating layer 11a or the laminated insulating layer 14 (fig. 13 (a)). In the final second conductor forming step, the conductor 12 is formed on the uppermost insulating laminate layer 14 (fig. 13(b)), and in the press-fitting step, the uppermost conductor 12 is mechanically press-fitted into or sunk into the uppermost insulating laminate layer 14 (fig. 13 (c)).
The conductor 12 can be formed by applying the steps shown in fig. 1(a) to 1(c) or the steps shown in fig. 2(a) to 2(d) to a conductor forming step or a second conductor forming step.
In the press-fitting step, when the conductor 12 is press-fitted or sunk into the multilayer insulating layer 11a or the multilayer insulating layer 14, at least one of the multilayer insulating layer 11a, the multilayer insulating layer 14, and the conductor 12 may be heated. Heating can be achieved by pressing a heater, or irradiating infrared rays, or hot air blowing. The conductor 12 may also be mechanically pressed in using a panel heated by a heater. The heating step can be the same as the steps illustrated in fig. 4, 5, 6, 7, 8.
In the electronic component mounting substrate of the present invention, the multilayer insulating layer 11a and the multilayer insulating layer 14 may be integrated. Or integrated when a plurality of stacked insulating layers 14 are adjacent to each other.
In the press-fitting step, the state after the conductor 12 is press-fitted into the multilayer insulating layer 14 is the same as that in fig. 10(a), 10(b), 11(a), 11(b), and 11 (c).
Fig. 14(a), 14(b), 15(a), 15(b), and 15(c) show the state in which the conductor 12 is pressed into the laminated insulating layer 14. Fig. 14(a), 14(b), 15(a), 15(b), and 15(c) are examples of the electronic component mounting board of the present invention. In fig. 14(a), 14(b), 15(a), 15(b), and 15(c), 12 denotes a conductor, and 14 denotes a stacked insulating layer. In these descriptions, as shown in fig. 14 a, a surface on a side close to the multilayer insulating layer 11a (a side close to the multilayer insulating layer 11 a) on the conductor 12 is referred to as a bottom surface, a surface on a side opposite to the bottom surface (a side far from the multilayer insulating layer 11 a) is referred to as an upper end surface, a surface on a side sandwiched between the upper end surface and the bottom surface is referred to as a side surface, and a surface on a side far from the multilayer insulating layer 11a on the multilayer insulating layer 14 is referred to as an upper end surface.
The conductor 12 may be press-fitted until the bottom surface and a part of the side surface of the conductor 12 are lower than the upper end surface of the multilayer insulating layer 14 (fig. 14 (a)). Since the entire bottom surface and a part of the side surface of the conductor 12 are in close contact with the laminated insulating layer 14, the peel strength between the laminated insulating layer 14 and the conductor 12 is improved. The conductor 12 may be press-fitted to a position where its upper end face is flush with the upper end face of the insulating multilayer layer 14 (fig. 14 (b)). Since the entire bottom surface and the entire side surface of the conductor 12 are in close contact with the laminated insulating layer 14, the peel strength between the laminated insulating layer 14 and the conductor 12 is further improved.
Not only the bottom surface and the side surface of the conductor 12, but also the conductor 12 may be pressed until the upper end surface thereof becomes lower than the upper end surface of the multilayer insulating layer 14 (fig. 15 a, 15 b, and 15 c). In fig. 15(a), the conductor 12 is pressed until its upper end surface is lower than the upper end surface of the multilayer insulating layer 14, but the upper end surface of the conductor 12 is exposed. Since the entire bottom surface and the entire side surface of the conductor 12 are in close contact with the laminated insulating layer 14, the peel strength between the laminated insulating layer 14 and the conductor 12 is further improved. In fig. 15(b), the conductor 12 is pressed until the upper end surface of the conductor 12 is lower than the upper end surface of the insulating laminate layer 14, but a part of the upper end surface of the conductor 12 is exposed. Since the entire bottom surface, the entire side surface, and a part of the upper end surface of the conductor 12 are in close contact with the laminated insulating layer 14, the peel strength between the laminated insulating layer 14 and the conductor 12 is further improved. In fig. 11(c), the conductor 12 is pressed until the upper end surface of the conductor 12 is lower than the upper end surface of the multilayer insulating layer 14, and is embedded in the multilayer insulating layer 14 to the upper end surface of the conductor 12. Since the entire bottom surface, the entire side surface, and the entire upper end surface of the conductor 12 are in close contact with the laminated insulating layer 14, the peel strength between the laminated insulating layer 14 and the conductor 12 is further improved.
By pressing or sinking the conductor 12 of the uppermost layer into the laminated insulating layer 14, the peeling strength between the laminated insulating layer 14 and the conductor 12 can be improved in the electronic component mounting substrate as a final product. By pressing or sinking the conductors other than the uppermost conductor into the multilayer insulating layer 11a or the multilayer insulating layer 14, the peeling strength between the multilayer insulating layer 11a or the multilayer insulating layer 14 and the conductor 12 can be increased in the manufacturing process of the electronic component mounting board, and the peeling of the conductor in the manufacturing process can be prevented.
The conductor forming step or the second conductor forming step includes a press-fitting step. The press-fitting step may include a VIA formation step of forming VIA, which electrically connects the conductors 12 formed on different layers among the conductors 12 formed on the buildup layer, as a part of the conductor portion. After the VIA formation process, the conductor 12 is pressed or sunk into the laminated insulating layer 14.
A VIA, which electrically connects conductors 12 formed on different layers among the conductors 12 formed on the combined layer by the stacked insulating layers 14, will be described below as a part of the conductor section. Fig. 16(a), 16(b), 16(c), and 16(d) show a VIA formation step. In fig. 16(a), 16(b), 16(c), and 16(d), 11a denotes a stacked insulating layer, 12 denotes a conductor, 14 denotes an insulating layer, and 15 denotes VIA.
In the conductor forming step or the second conductor forming step, the conductor 12, the insulating laminate layer 14, and the conductor 12 are formed on the insulating laminate layer 11a in this order (fig. 16 a and 16 b). The conductors 12 formed on the different layers are electrically connected by VIA15 (fig. 16 (c)). After that, if the conductor 12 is mechanically pressed or sunk into the laminated insulating layer 14, the VIA15 is compressed, thereby improving the anchoring effect and the peel strength between the laminated insulating layer 14 and the conductor 12. Although VIA for electrically connecting the conductor 12 on the laminated insulating layer 11a and the conductor 12 on the laminated insulating layer 14 to each other is described here, this is also the same for VIA15 for electrically connecting the conductor 12 on the laminated insulating layer 14 and the conductor 12 on the laminated insulating layer 14. The same applies to VIA in which the conductor 12 on the uppermost layer and the conductor 12 on the lower layer are electrically connected to each other.
In the above description, the conductor 12 is mechanically pressed into the laminated insulating layer 11a and the laminated insulating layer 14 after the VIA formation step, but the VIA15 may be formed after the conductor 12 is mechanically pressed into the laminated insulating layer 11a and the laminated insulating layer 14.
In the above embodiments, although the description has been given in the case where one side of the stacked insulating layer is shown, the present description is not limited to the single-sided substrate, and the technique of the present invention can be applied to both sides of the stacked insulating layer in the case of a double-sided substrate or a multilayer substrate. In the case of a double-sided substrate or a multilayer substrate, the upper layer or the upper end surface in this embodiment may be regarded as the layer or the surface on the side away from the stacked insulating layer.
In the case of a multilayer substrate, any of the conductors on the laminated insulating layer, the outermost conductor farthest from the laminated insulating layer, and any of the conductors between the laminated insulating layer and the outermost layer may be pressed or sunk into the laminated insulating layer. For example, the conductor may be pressed or sunk into the outermost layer, or the conductor of the intermediate layer between the laminated insulating layer and the outermost layer may be pressed or sunk into the intermediate layer between the laminated insulating layer and the outermost layer.
In the case of a double-sided substrate or a multilayer substrate, when conductors on both sides are pressed or sunk, the conductors may be pressed by simultaneously applying pressure to the conductors from both sides.
Further, in the case of manufacturing a thin printed circuit board, there is a current situation that a copper foil with a carrier is inevitably used because the copper foil is easily damaged, and these problems also exist: the first is high price of the copper foil with carrier, the second is high defective rate, and the third is high demand for the degree of management of the manufacturing process. According to the present invention, a single-layer printed board or a multilayer printed board having a small board thickness can be manufactured without using a copper foil with a carrier. In addition, the technique of the present invention may use a Build-up process (Build-up process) which is a process for manufacturing VIA or a VIA process which is a process for manufacturing a through hole.
(second embodiment)
In the first embodiment, an adhesion layer (not shown) having high adhesion may be provided on the front surface of the insulating layer 11 in contact with the conductor 12. The adhesion layer is a layer of any insulating material that exhibits high adhesion between the insulating layer 11 and the conductor 12. In this case, the method for manufacturing an electronic component mounting board according to the present invention further includes an adhesion layer forming step.
In the adhesion layer forming step, an adhesion layer is formed on the insulating layer 11. In the conductor forming step, the conductor 12 is formed on the upper end surface of the adhesion layer. The adhesion layer is formed on at least a part of the region where the conductor 12 is disposed on the insulating layer 11. The adhesion layer is preferably formed over the entire region where the conductor 12 is disposed, and may be formed over the entire insulating layer 11.
The adhesion layer is any insulating substance having higher adhesion to the conductor 12 than the insulating layer 11. The adhesion layer is disposed at least partially between the insulating layer 11 and the conductor 12. The adhesion layer can be disposed over at least a part of the space between the insulating layer 11 and the conductor 12, so that the adhesion strength between the insulating layer 11 and the conductor 12 can be increased, and the adhesion layer can be disposed over the entire space between the insulating layer 11 and the conductor 12. The adhesion layer contains a substance that enhances the adhesion strength between the insulating layer 11 and the conductor 12. The substance for increasing the adhesion strength may be any one of the substances using chemical interaction, physical interaction, and mechanical bonding. As the mechanical bonding, for example, the irregularities described in the third embodiment described later can be exemplified.
The adhesive layer may contain a substance used as an adhesive in part or the whole of the adhesive layer as a substance for enhancing the adhesive strength by chemical interaction. For example, the resin material of the adhesion layer partially or entirely made of an insulating material may be any material having high adhesion to both the conductor 12 and the insulating layer 11, such as an inorganic material, in addition to polyimide resin, epoxy resin, phenol resin, cyanate resin, and the like. The inorganic substance may be a part or all of metal oxides, metal nitrides, metal carbides, oxidizing agents, reducing agents, and the like.
As the substance that enhances the adhesion strength by physical interaction, at least either one of a reducing agent having a reducing action and an oxidizing agent having an oxidizing action may be contained in a part of or the whole of the adhesion layer. The reducing agent has an action of reducing a substance contained in at least one of the conductor 12, the insulating layer 11, and the adhesion layer. The oxidizing agent has an action of oxidizing a substance contained in at least one of the conductor 12, the insulating layer 11, and the adhesion layer. The reducing agent and the oxidizing agent may react with not only the conductor 12, the insulating layer 11, and the adhesion layer but also the surrounding environment such as air or water, and other catalysts, alone or in combination with each other.
The reducing agent may be contained in the entire adhesion layer, may be contained only on the front surface of the adhesion layer on the conductor 12 side, or may be contained only on the front surface of the insulating layer 11 side. The same is true for the oxidizing agent. For example, the reducing agent may be contained on the surface of the adhesion layer on the conductor 12 side, and the oxidizing agent may be contained on the surface of the adhesion layer on the insulating layer 11 side. The reducing agent contained in the adhesion layer may be contained in any proportion, and may be in a trace amount as long as it has a reducing property. The same is true for the oxidizing agent.
The reducing agent contained in the front surface of the adhesion layer on the insulating layer 11 side may be different from or the same as the reducing agent contained in the front surface of the adhesion layer on the conductor 12 side. As a different example, for example, such a configuration can be adopted: the reducing agent suitable for reduction of the conductor 12 is contained on the conductor 12 side of the adhesion layer, and the reducing agent suitable for reduction of the insulating layer 11 is contained on the insulating layer 11 side of the adhesion layer. As a similar example, the adhesion layer according to the present invention is provided, for example, if a substance functioning as a reducing agent is contained between the insulating layer 11 and the conductor 12. The same is true for the oxidizing agent.
In the multilayer substrate examples in fig. 12 to 13, an adhesion layer can be provided on the buildup layer. For example, an adhesion layer (not shown) is provided between the insulating layer 11 and the conductor 12 formed on the insulating layer, and between the insulating layer 14-1 and the conductor 12-1 constituting a composite layer. An adhesion layer (not shown) may be provided between the conductor 12-1 formed on the insulating layer 14-1 for constituting the composite layer and the insulating layer 14-2 formed on the conductor 12-1. In this case, a combined layer of the adhesion layer and the conductor 12-2 may be formed instead of the combined layer of the insulating layer 14-2 and the conductor 12-2.
The method for manufacturing the electronic component mounting board according to the present embodiment may further include the press-fitting step described in the first embodiment after the conductor forming step. This can further improve the peel strength.
(third embodiment)
Fig. 17 shows an example of the electronic component mounting board according to the embodiment of the present invention. The electronic component mounting board according to the present embodiment has a conductor 12 formed on an insulating layer 11. The conductor 12 includes an electroless-plated layer 21 in the lowermost layer on the insulating layer 11 side. For example, the conductor 12 includes an electroless-plated layer 21 and an electrolytic-plated layer 22 stacked in this order from the lowermost layer on the insulating layer 11 side. In this way, since the insulating layer 11 is in contact with the electroless plating layer 21, the adhesion strength between the insulating layer 11 and the conductor 12 can be increased.
The electroless plated layer 21 is an arbitrary conductor formed by an arbitrary electroless plating method. In fig. 17, the electrolytic plating layer 22 is laminated on the electroless plating layer 21, but the electrolytic plating layer 22 may not be provided and the entire conductor 12 may be formed of the electroless plating layer 21.
Fig. 18 shows an enlarged view of the boundary portion of the insulating layer 11 and the conductor 12. Fig. 18(b) shows the sectional shape of the front surface 11U of the insulating layer 11, and fig. 18(a) shows the sectional shape a-a'. The insulating layer 11 has irregularities on the front surface 11U on the conductor 12 side. The concave-convex portions may be concave portions or convex portions, or both.
In the present invention, irregularities are formed on the front surface 11U of the insulating layer 11, and the electroless-plated layer 21 is formed thereon. Therefore, as shown in fig. 19, the electroless-plated layer 21 grows from the lower portion of the conductor 12 disposed on the insulating layer 11 side, and is in direct contact with the front surface 11U of the insulating layer 11. Here, the convex portions shown by the symbols 112-6 and 112-9 may be formed, or the convex portions shown by the symbols 112-6 and 112-9 may not be formed.
When the conductor 12 is formed with a convex shape to obtain an anchoring effect, a particulate substance such as Ni or Fe for forming the convex shape is contained between the front surface of the adhesion layer and the electroless plating layer 21. On the other hand, in the present invention, since the surface of the adhesion layer is uneven, the granular material for forming a convex shape in the conductor 12 is not included. Therefore, the content of the substance different from the electroless plating layer 21 in the lowermost layer of the conductor 12 is 30% or less. For example, the electroless-plated layer 21 of the lowermost layer of the conductor 12 in the present invention may be formed of a single substance. Here, [ single substance ] includes metals and alloys. In the conductor projection from the conductor 12 side toward the adhesion layer side in the present invention, as shown by the channel 133 in fig. 18, a conduction portion is not formed in the adhesion layer. That is, the electroless-plated layer 21 is formed only on the front surface side of the adhesion layer.
When the anchor is formed using the convex shape formed on the conductor 12, the conductor 12 grows from its own position toward the center of the adhesion layer. Therefore, the conductor 12 is tapered from the vicinity of the front surface 1 of the adhesion layer on which it is disposed toward the center of the adhesion layer. In contrast, in the present invention, since the irregularities are formed on the front surface of the adhesion layer, the conductor 12 is not only tapered from the vicinity of the front surface of the adhesion layer toward the center of the insulating layer 11, but also is expanded from the vicinity of the front surface of the adhesion layer toward the center of the insulating layer 11 as shown in the recesses 111-1, 111-3, and 111-6 in fig. 18.
As shown in fig. 20, the concave portions 111-8 and 111-9 of fig. 18 may be formed obliquely from the vicinity of the front surface 11U of the insulating layer 11 toward the center of the insulating layer 11. In this case, the distance between the concave portion 111-8 and the concave portion 111-9 is preferably set so that the deeper the insulating layer 11, the smaller the distance between the concave portion 111-8 and the concave portion 111-9 is than the distance near the front surface 11U of the insulating layer 11. By this, the insulating layer 11 can be caught by the recesses 111-8 and 111-9, and the peel strength between the conductor 12 and the insulating layer 11 can be further improved.
In the present invention, since the unevenness is formed on the front surface 11U of the insulating layer 11, the arrangement of the unevenness on the front surface 11U of the insulating layer 11 has regularity by the unevenness forming method.
When the unevenness is formed using the unevenness formed on a plane or a roller, the unevenness of the plane or the roller may directly appear on the front surface 11U. For example, when the concave-convex pattern includes straight lines having a constant width or a constant interval, concave portions or convex portions having a constant width or a constant interval as shown by reference numerals 111-8 and 111-9 in fig. 18 and fig. 21(a) are left. When the unevenness is formed on the cut front surface 11U, as shown in fig. 21(b) and 21(c), a linear trace is left in the cutting direction.
When the unevenness is formed by using a foamable chemical, a trace of circular bubbles remains as shown by reference numerals 111-1 to 111-7 in FIG. 18 and FIG. 21 (d). The inner diameters of the recesses 111-1 to 111-7 may be constant or different. Further, as shown in the concave portion 111-1, there is also a double circle shape in which a convex portion 112-1 is formed in the concave portion 111-1. The convex portion 112-1 may be formed in the concave portions 111-2 to 111-7. The circular shape included in the concave and convex portions may be formed not only in the concave portion but also in the convex portion. The cross-sectional shape of the irregularities shown in fig. 18(a) and 18(b) is not limited to the above shape, and includes any shape formed when the irregularities are formed. For example, wedges, hooks, trapezoids, pendulums, trapezoids with double peaks, etc. can be exemplified.
Even if the regularity of the unevenness cannot be found in a narrow range, the regularity can be found if the range is wide. In particular, since the electronic component mounting board is separated into chips and mounted on an electronic component or the like, the regularity of the irregularities may not be exhibited in one chip depending on the method of forming the irregularities. In this case, traces of the concave-convex forming substance start to be exhibited only on an arbitrary number of chips equal to or greater than two.
A method for manufacturing an electronic component mounting board according to the present invention will be described with reference to fig. 26. The method for manufacturing an electronic component mounting substrate according to the present embodiment includes a step of forming irregularities before a conductor forming step.
In the unevenness forming step, the insulating layer 11 is prepared (fig. 22 a), and then unevenness is formed on the front surface 11U of the insulating layer 11 (fig. 22 b). The formation of the irregularities is performed over the entire area of the front surface 11U where the wiring pattern of the conductor 12 can be formed. When the irregularities are formed on the entire front surface 11U, the irregularities shown in fig. 18 are also formed on the insulating layer 11 in the region where the conductor 12 is not arranged on the front surface 11U side where the conductor 12 is present.
The unevenness can be formed using any method, and for example: these forming methods may be combined, for example, by physical formation such as transferring the concave-convex shape formed on a plane or a roller to the front surface 11U, embedding an insulating sheet having the concave-convex shape in the front surface 11U, mechanical formation such as cutting the front surface 11U with a brush, or chemical formation such as dissolving or swelling the front surface 11U with a chemical. The uneven shape of the front surface 11U of the insulating layer 11 may be different between a region where the conductor 12 is disposed and a region where the conductor 12 is not disposed.
The conductor forming step is the same as that described in the first embodiment, but the present embodiment is different in that it includes the electroless plating layer 21. This is to form the electroless-plated layer 21 (fig. 22 c), form the electrolytic-plated layer 22 (fig. 22 d), and remove the electroless-plated layer 21 (fig. 22 e). The electroless plating layer 21 can be formed by electroless plating, and can be formed by liquid or paste conductor coating. The electroless plating layer 21 is formed over the entire area of the front surface 11U where the wiring pattern of the conductor 12 can be formed. The electrolytic plating layer 22 is formed in the shape of a wiring pattern. The electroless plated layer 21 is removed by leaving the electrolytic plated layer 22 and removing the electroless plated layer 21 formed in the region other than the wiring pattern. At this time, the corners (reference numeral 12E shown in fig. 17) of the conductor 12 are rounded. In the present invention, since the conductor 12 is grown from the insulating layer 11 side, in a cross section perpendicular to the insulating layer 11, an angle of an upper end face facing a surface of the conductor 12 on the insulating layer 11 side is rounded.
The area of the front surface 11U of the insulating layer 11 where the irregularities are formed and the area of the electroless-plated layer 21 are formed may be only the area of the front surface 11U where the wiring pattern of the conductor 12 is formed.
Instead of forming the electrolytic plating layer 22, the electroless plating layer 21 may be formed directly in the shape of a wiring pattern. In this case, the entire conductor 12 is formed of the electroless-plated layer 121.
In the present embodiment, a single-sided substrate is exemplified as an example of the electronic component mounting substrate according to the present invention, but the present invention is not limited to this. For example, the electronic component mounting substrate according to the present invention may be a double-sided substrate. In this case, the structure of the insulating layer 11 and the conductor 12 described in the present embodiment may be formed only on one side, or may be formed on both sides. The electronic component mounting substrate according to the present invention may be a multilayer substrate. In this case, the structure of the insulating layer 11 and the conductor 12 described in this embodiment may be included in at least one layer of the multilayer substrate.
As described above, the conductor 12 of the present embodiment includes the electroless-plated layer 21 in the lowermost layer on the insulating layer 11 side, and the insulating layer 11 is in contact with the electroless-plated layer 121. Therefore, the present embodiment can provide an electronic component mounting board having a high peel strength.
Although this embodiment has been described as an application example applied to the first embodiment, this embodiment can be applied to the second embodiment. In this case, the irregularities may be formed on the front surface contacting the conductor 12, or may be formed on the front surface of the adhesion layer contacting the insulating layer 11, or on the front surface 11U of the insulating layer 11 contacting the adhesion layer.
(fourth embodiment)
Next, a fourth embodiment will be explained. In the present embodiment, the side surface of the conductor 12 has a conductor recess (recess) 200.
The conductor recess 200 may be formed by using a resist containing a particulate substance 250. Specific examples are described below.
First, a resist layer 290 is formed using a resist containing the particulate matter 250 (see fig. 23 a).
Thereafter, the portions of the resist layer 290 where the conductors 12 are to be provided are removed by etching or the like (see fig. 23 b). At this time, the etchant is selected so as not to remove the particulate matter 250 together. The particulate matter 250 contained in the resist layer 29 is removed together with the resist layer 290.
Then, electroless plating or electrolytic plating is performed in a state where the granular substance 250 is exposed from the side surface of the opening 295 provided in the resist layer 290, thereby forming the conductor 12. Thus, the conductor 12 having the conductor recess 200 can be formed (see fig. 23 c).
Then, the resist layer 290 and the particulate matter 250 are removed by etching. At this time, the particulate matter 250 contained in the resist 290 is removed together with the resist 290 (see fig. 23 d).
Next, the conductor 12 having the conductor recess 200 is press-fitted into the insulating layer 11 in a semi-cured state (see fig. 23(e)), and then the insulating layer 11 is cured.
By performing the above steps, a part of the insulating layer 11 is positioned in the conductor recess 200 of the conductor 12, and the adhesion between the conductor 12 and the insulating layer 11 can be improved.
(fifth embodiment)
Next, a fifth embodiment will be explained. In the present embodiment, the side surface of the conductor 12 has a conductor convex portion (convex portion) 210. Further, the conductor convex portion 210 and the conductor concave portion 200 may be fitted to the side surface of the conductor 12 at the same time.
The conductor convex portion 210 can be formed by using a resist containing a particulate substance 250. Specific examples are described below.
First, a resist layer 290 is formed using a resist containing the particulate matter 250 (see fig. 24 a).
Thereafter, the portions of the resist 290 where the conductors 12 are to be provided are removed by etching or the like (see fig. 24 (b)). At this time, the etchant is selected so as not to remove the particulate matter 250 together. The particulate matter 250 contained in the resist layer 29 is removed together with the resist layer 290.
Then, electroless plating or electrolytic plating is performed to form the conductor 12 (see fig. 24 c). Thus, the conductor 12 having the conductor convex portion 210 can be formed.
Then, the resist layer 290 and the particulate matter 250 are removed by etching (see fig. 24 d). At this time, the particulate matter 250 contained in the resist 290 is removed together with the resist 290.
Next, the conductor 12 having the conductor convex portion 210 is press-fitted into the insulating layer 11 in a semi-cured state (see fig. 24(e)), and then the insulating layer 11 is cured.
By performing the above steps, the conductor protrusion 210 is positioned in the insulating layer 11, and the adhesion between the conductor 12 and the insulating layer 11 can be improved.
(sixth embodiment)
In the present embodiment, an application example of the electronic component mounting board according to the present invention will be described. The electronic component according to the present embodiment includes the electronic component mounting substrate according to the present invention, and performs a predetermined process using the electronic component mounting substrate according to the present invention. The processing is arbitrary processing performed using an electronic component.
In the electronic module according to the present embodiment, the electronic component according to the present description is used for at least one of the electronic components mounted thereon. In the mounting device according to the present embodiment, the electronic component or the electronic component according to the present invention is used for at least one of the electronic component and the electronic component mounted thereon.
The present invention can be applied to all devices provided with a substrate for mounting an electronic component. An example of an apparatus to which the present description can be applied can be, for example: automobiles, home electric appliances, communication devices, control devices, sensors, robots, unmanned planes, airplanes, spacecraft, ships, production instruments, engineering instruments, test instruments, measuring instruments, computer-related products, digital devices, game devices, clocks, and the like.
The device is equipped with any function corresponding to the device. The electronic component mounting board according to the present description is used for an electronic module such as an electronic chip used for implementing the function. Since the electronic component mounting board according to the present invention can improve the peel strength, the reliability of the electronic component, the electronic module, and the device can be improved.
[ possibility of Industrial utilization ]
The electronic component mounting board and the method for manufacturing the same according to the present invention can be mounted on various electronic devices or applied to the manufacture of electronic devices.
Description of the symbols
11 insulating layer
12 conductor
121 metal foil
122 metal plating
13 Pattern resist
14 insulating layer
15 VIA
11U front
111-1 to 111-9 recesses
112-1, 112-6, 112-9 protrusions
113 channel
21 electroless plating layer
22 electrolytic plating layer
Claims (12)
Applications Claiming Priority (5)
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JP2017-099580 | 2017-05-19 | ||
JP2017099580 | 2017-05-19 | ||
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JP2017-221807 | 2017-11-17 | ||
PCT/JP2018/017502 WO2018211991A1 (en) | 2017-05-19 | 2018-05-02 | Board for mounting electronic component, and manufacturing method therefor |
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CN110915307A true CN110915307A (en) | 2020-03-24 |
CN110915307B CN110915307B (en) | 2023-02-03 |
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JP (1) | JP7048593B2 (en) |
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- 2018-05-02 KR KR1020197037396A patent/KR102631808B1/en active Active
- 2018-05-02 JP JP2019519175A patent/JP7048593B2/en active Active
- 2018-05-02 CN CN201880032995.6A patent/CN110915307B/en active Active
- 2018-05-02 WO PCT/JP2018/017502 patent/WO2018211991A1/en active Application Filing
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CN110915307B (en) | 2023-02-03 |
KR102631808B1 (en) | 2024-01-31 |
JP7048593B2 (en) | 2022-04-05 |
WO2018211991A1 (en) | 2018-11-22 |
KR20200010363A (en) | 2020-01-30 |
JPWO2018211991A1 (en) | 2020-04-09 |
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