CN110890349B - A three-dimensional packaging structure of an optoelectronic chip with an optical interconnection interface and a manufacturing method thereof - Google Patents
A three-dimensional packaging structure of an optoelectronic chip with an optical interconnection interface and a manufacturing method thereof Download PDFInfo
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- CN110890349B CN110890349B CN201911326887.2A CN201911326887A CN110890349B CN 110890349 B CN110890349 B CN 110890349B CN 201911326887 A CN201911326887 A CN 201911326887A CN 110890349 B CN110890349 B CN 110890349B
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- 230000003287 optical effect Effects 0.000 title claims abstract description 236
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 56
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910000679 solder Inorganic materials 0.000 claims abstract description 17
- 238000007789 sealing Methods 0.000 claims abstract description 6
- 230000008878 coupling Effects 0.000 claims description 48
- 238000010168 coupling process Methods 0.000 claims description 48
- 238000005859 coupling reaction Methods 0.000 claims description 48
- 239000013307 optical fiber Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 235000012431 wafers Nutrition 0.000 claims 10
- 238000005476 soldering Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 230000002708 enhancing effect Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 241001124569 Lycaenidae Species 0.000 description 1
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- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 238000004891 communication Methods 0.000 description 1
- 235000014987 copper Nutrition 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000011368 organic material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus compound Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4295—Coupling light guides with opto-electronic elements coupling with semiconductor devices activated by light through the light guide, e.g. thyristors, phototransistors
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4296—Coupling light guides with opto-electronic elements coupling with sources of high radiant energy, e.g. high power lasers, high temperature light sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Optical Couplings Of Light Guides (AREA)
Abstract
本发明公开了一种带有光互连接口的光电芯片三维封装结构，包括：光芯片，所述光芯片的一端具有光互连结构和凹槽；导电通孔，所述导电通孔贯穿所述光芯片；第一布线层，所述第一布线层设置在所述光芯片的正面，且与所述导电通孔电连接；第二布线层，所述第二布线层设置在所述光芯片的背面，且与所述导电通孔电连接；电芯片，所述电芯片设置在所述光芯片正面上方，且电连接所述第一布线层；盖板，所述盖板设置的所述光芯片的光互结构和凹槽的上方；塑封层，所述塑封层一体塑封所述光芯片的正面、电芯片和盖板；以及外接焊球，所述外接焊球设置在所述光芯片背面下方，且电连接所述第二布线层。
The present invention discloses a three-dimensional packaging structure of an optoelectronic chip with an optical interconnection interface, comprising: an optical chip, one end of which is provided with an optical interconnection structure and a groove; a conductive through hole, which runs through the optical chip; a first wiring layer, which is arranged on the front side of the optical chip and is electrically connected to the conductive through hole; a second wiring layer, which is arranged on the back side of the optical chip and is electrically connected to the conductive through hole; an electric chip, which is arranged above the front side of the optical chip and is electrically connected to the first wiring layer; a cover plate, which is arranged above the optical interconnection structure and the groove of the optical chip; a plastic sealing layer, which integrally seals the front side of the optical chip, the electric chip and the cover plate; and an external solder ball, which is arranged below the back side of the optical chip and is electrically connected to the second wiring layer.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a three-dimensional packaging structure of an optoelectronic chip with an optical interconnection interface and a manufacturing method thereof.
Background
With the increasing amount of communication data, the transmission rate of optical modules is required to be higher and higher, and the standard rate of the next generation optical interconnection is 56Gbps and 112Gbps at present. In the case of high-speed interconnects, transmission loss, crosstalk, and reflection caused by interconnect leads between chips are not negligible, and parasitic inductance of the interconnect leads also greatly affects performance. The shorter and better the interconnection of the optical and electrical chips should be, the better it can be, preferably, the interconnection by flip-chip bonding.
At present, the existing packaging mode of the photoelectric chip is to flatly lay the silicon photoelectric chip and the electric chip on a substrate, interconnect the silicon photoelectric chip and the electric chip in a wire bonding or flip-chip mode, and not perform plastic packaging. Or the electric chip is stacked on the silicon optical chip to form a three-dimensional interconnection structure, the optical coupling part is still adhered on the electric chip in a mode of optical fiber or FA, and the whole package is not subjected to plastic package.
With the development of silicon optical technology, an optical device and an electrode can be manufactured on one silicon optical chip through a CMOS process at the same time, and are easier to interconnect with an electric chip, and the packaging interconnection reliability can be ensured by plastic packaging. It is desirable to package the silicon optical chip and the electrical chip by a common plastic packaging method, but the optical coupling position of the silicon optical chip cannot be polluted, and a coupling space needs to be reserved, which is another problem.
Aiming at the problems that the existing photoelectric chip packaging mode cannot be subjected to plastic packaging, the packaging interconnection reliability is poor, the packaging area is large, the performance is poor and the like, the invention provides a photoelectric chip three-dimensional packaging structure with an optical interconnection interface and a manufacturing method thereof.
Disclosure of Invention
Aiming at the problems of incapability of plastic packaging, poor reliability of packaging interconnection, large packaging area, poor performance and the like of the traditional photoelectric chip packaging mode, according to one embodiment of the invention, a three-dimensional packaging structure of a photoelectric chip with an optical interconnection interface is provided, which comprises the following components:
the optical chip is provided with an optical interconnection structure and a groove at one end;
The conductive through hole penetrates through the optical chip;
The first wiring layer is arranged on the front surface of the optical chip and is electrically connected with the conductive through hole;
The second wiring layer is arranged on the back surface of the optical chip and is electrically connected with the conductive through hole;
An electrical chip disposed over the front surface of the optical chip and electrically connected to the first wiring layer;
the cover plate is arranged above the optical mutual structure of the optical chip and the groove;
A plastic layer for integrally molding the front surface of the optical chip, the electric chip and the cover plate, and
And the external solder balls are arranged below the back surface of the optical chip and are electrically connected with the second wiring layer.
In one embodiment of the present invention, one end of the cover plate leaks out of the plastic sealing layer, and forms a hollow optical coupling structure together with the optical interconnection structure and the groove.
In one embodiment of the invention, the optical chip is a laser or modulator or detector or an integrated optical chip with optical interconnect structure.
In one embodiment of the invention, the optical interconnect structure is a grating, a mode spot-size converter, or a waveguide structure.
In one embodiment of the invention, the electrical chip is flip-chip bonded to the first wiring layer, or the electrical chip is mounted on the front side of the optical chip and electrically connected to the first wiring layer by wire bonding.
In one embodiment of the invention, the hollow optical coupling structure is further provided with an optical fiber coupling efficiency enhancing structure in coupling connection with the optical interconnect structure.
In one embodiment of the present invention, the fiber coupling efficiency enhancing structure is a lens or an isolator.
In another embodiment of the present invention, there is provided a method for manufacturing a three-dimensional package structure of an optoelectronic chip with an optical interconnection interface, including:
forming an optical interconnection structure at a position of the optical chip wafer, which is required to be optically coupled, and manufacturing a groove between two adjacent chips;
Preparing a metal through hole and a rewiring layer on the optical chip wafer;
assembling an electric chip and a cover plate on the top surface of the optical chip wafer;
performing plastic package on the top surface of the optical chip wafer;
Forming external solder balls under the wiring layer on the back surface of the optical chip wafer, and
The singulation forms individual package structures.
In another embodiment of the present invention, the preparing metal vias and rewiring layers on a photo-chip wafer further comprises:
Forming a blind hole downwards from the front surface of the optical chip wafer;
forming metal through hole filling in the blind hole;
Thinning the back of the optical chip wafer to realize back leakage of the conductive through hole;
forming a wiring layer on the front surface of the optical chip wafer, and
A wiring layer is formed on the back surface of the optical chip.
In another embodiment of the present invention, the top surface of the optical chip wafer is assembled with an electrical chip, which is flip-chip bonded to the wiring layer, or the electrical chip is mounted directly over the front surface of the optical chip and electrically connected to the wiring layer by wire bonding.
The invention provides a photoelectric chip three-dimensional packaging structure with optical interconnection interface and a manufacturing method thereof, firstly, manufacturing an optical interconnection structure and a groove at the edge of a silicon optical chip; then, the electric chip and the cover plate patch are stacked on the silicon optical chip, and a hollow optical coupling structure is formed between the electric chip and the cover plate, and then, the packaging structure on the upper surface of the silicon optical chip is subjected to plastic packaging, and external solder balls electrically connected with the wiring layer on the lower surface of the silicon optical chip are formed, so that the three-dimensional packaging structure of the photoelectric chip with an optical interconnection interface is formed. The three-dimensional packaging structure of the photoelectric chip with the optical interconnection interface adopts the plastic packaging after stacking the electric chip and the optical chip, ensures the reliability of packaging interconnection, can realize the optical coupling of the optical chip, realizes shorter electric interconnection and smaller packaging area, and further realizes higher performance.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
Fig. 1 shows a schematic cross-sectional view of a three-dimensional package structure 100 for an optoelectronic chip with an optical interconnect interface, in accordance with one embodiment of the present invention.
Fig. 2 shows a schematic cross-sectional view 200 of an optical coupling between an optical interconnect interface and an external optical fiber based on the three-dimensional package structure 100 of an optoelectronic chip according to an embodiment of the present invention.
Fig. 3A to 3F are schematic cross-sectional views illustrating a process of forming the three-dimensional package structure 100 with the optical interconnection interface according to an embodiment of the present invention.
Fig. 4 illustrates a flowchart 400 of forming the three-dimensional package structure 100 of an optoelectronic chip with an optical interconnect interface, according to one embodiment of the invention.
Fig. 5 shows a schematic cross-sectional view of a three-dimensional package structure 500 for an optoelectronic chip with an optical interconnect interface, in accordance with yet another embodiment of the present invention.
Fig. 6 shows a schematic cross-sectional view 600 of an optoelectric chip three-dimensional package structure 500 with optical interconnect interface optically coupled to an external optical fiber according to yet another embodiment of the invention.
Fig. 7 shows a schematic cross-sectional view of a three-dimensional package structure 700 of an optoelectronic chip with an optical interconnect interface, in accordance with yet another embodiment of the present invention.
Fig. 8 shows a schematic cross-sectional view 800 of an optical coupling between an optical fiber and an external optical fiber based on the three-dimensional package structure 700 with optical interconnection interface according to still another embodiment of the present invention.
Detailed Description
In the following description, the present invention is described with reference to the embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without the specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and not for limiting the order of the steps, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a photoelectric chip three-dimensional packaging structure with optical interconnection interface and a manufacturing method thereof, firstly, manufacturing an optical interconnection structure and a groove at the edge of a silicon optical chip; then, the electric chip and the cover plate patch are stacked on the silicon optical chip, and a hollow optical coupling structure is formed between the electric chip and the cover plate, and then, the packaging structure on the upper surface of the silicon optical chip is subjected to plastic packaging, and external solder balls electrically connected with the wiring layer on the lower surface of the silicon optical chip are formed, so that the three-dimensional packaging structure of the photoelectric chip with an optical interconnection interface is formed. The three-dimensional packaging structure of the photoelectric chip with the optical interconnection interface adopts the plastic packaging after stacking the electric chip and the optical chip, ensures the reliability of packaging interconnection, can realize the optical coupling of the optical chip, realizes shorter electric interconnection and smaller packaging area, and further realizes higher performance.
A three-dimensional package structure of an optoelectronic chip with an optical interconnect interface according to an embodiment of the present invention is described in detail below with reference to fig. 1. Fig. 1 shows a schematic cross-sectional view of a three-dimensional package structure 100 for an optoelectronic chip with an optical interconnect interface, in accordance with one embodiment of the present invention. As shown in fig. 1, the three-dimensional package structure 100 with optical interconnection interface further includes an optical chip 110, a conductive via 120, a first wiring layer 130, a second wiring layer 140, an electrical chip 150, a cover plate 160, a molding layer 170, an external solder ball 180, an optical interconnection structure 111, and an optical coupling structure 190.
The optical chip 110 may be an active optical chip such as a laser, a modulator, a detector, or the like, or an optical integrated chip with multiple structures, and the material may be a silicon optical chip, or an indium, gallium, arsenic, phosphorus compound semiconductor material, or a silicon carbide, silicon nitride material. Also at the edge of the optical chip 110 is an optical interconnect structure 111, and the optical interconnect structure 111 may be a grating, a mode spot converter, or a waveguide structure.
The conductive via 120 is penetratingly disposed in the optical chip 110. In one embodiment of the present invention, the standard TSV conductive via of conductive via 120, the via fill material is a galvanically formed metallic copper.
The first wiring layer 130 is disposed above the optical chip 110 and electrically connected to the conductive via 120 to redistribute the chip pad positions. In one embodiment of the present invention, the first wiring layer 130 may be a single-layer wiring layer or a multi-layer wiring layer, and dielectric layers are further disposed between the same-layer wiring layer and between adjacent layers for insulation and protection.
The second wiring layer 140 is disposed under the optical chip 110, electrically connected to the conductive via 120, and an external pad is disposed on the outermost wiring layer. In one embodiment of the present invention, the second wiring layer 140 is similar to the first wiring layer 130, and may be a single-layer wiring layer or a multi-layer wiring layer, and dielectric layers are further disposed between the same-layer wiring layer and adjacent layers for insulation and protection.
The electrical chip 150 is a chip related to the optical chip 110, which needs interconnection, including a driving chip, an amplifying chip, a signal processing chip, an ASIC chip, a power chip, and the like. The electrical chip 150 is assembled on the first wiring layer 130 of the upper surface of the optical chip in a flip-chip or wire bonding manner.
The cover plate 160 is fixedly disposed over the optical interconnect structure 111 at the edge of the optical chip 110. In one embodiment of the present invention, the material of the cover plate 160 may be glass, silicon, an organic material, or the like.
The plastic layer 170 covers the upper surface of the optical chip 110, and covers the first wiring layer 130, the electrical chip 150, and the cover plate 160.
The external solder balls 180 are disposed on the external pads of the second wiring layer 140 under the optical chip 110. In one embodiment of the present invention, the external solder balls 180 may be BGA solder balls formed by a ball-mounting process, or may be conductive Copper pillars (coppers).
The optical coupling structure 190 is a hollow structure, and is formed by a groove at an edge of the optical chip 110, the optical interconnection structure 111, and the cover plate 160 together. For alignment and connection with an external optical fiber to achieve optical coupling.
Fig. 2 shows a schematic cross-sectional view 200 of an optical coupling between an optical interconnect interface and an external optical fiber based on the three-dimensional package structure 100 of an optoelectronic chip according to an embodiment of the present invention. As shown in fig. 2, the optical coupling structure 200 between the three-dimensional package structure 100 with optical interconnection interface and the external optical fiber further includes the three-dimensional package structure 210/100 with optical interconnection interface, the substrate 220, the optical fiber 230, and the optical fiber coupler 240. The three-dimensional package structure 210/100 of the photoelectric chip with the optical interconnection interface and the optical fiber coupler 240 are fixedly arranged on the substrate 220, and the optical fiber 230 is aligned and coupled in the optical coupling structure 190 of the three-dimensional package structure 210/100 of the photoelectric chip with the optical interconnection interface through the optical fiber coupler 240, so that high-efficiency optical signal coupling connection is realized.
A method of forming the three-dimensional package structure 100 with an optical interconnect interface according to an embodiment of the present invention is described in detail below with reference to fig. 3A through 3F and fig. 4. Fig. 3A to 3F are schematic cross-sectional views illustrating a process of forming the three-dimensional package structure 100 for an optoelectronic chip with an optical interconnection interface according to an embodiment of the present invention, and fig. 4 is a flowchart 400 illustrating a process of forming the three-dimensional package structure 100 for an optoelectronic chip with an optical interconnection interface according to an embodiment of the present invention.
First, at step 410, as shown in FIG. 3A, an optical interconnect structure is formed at a location where optical coupling of an optical chip wafer is desired, and a recess is created between two adjacent chips. The optical interconnection structure can be a grating, a spot-size converter or a waveguide structure, and the grooves are etched according to the arrangement and are part of an optical coupling structure of the packaging structure.
Next, at step 420, metal vias and rewiring layers are prepared on the photo-chip wafer as shown in fig. 3B. In one embodiment of the invention, blind holes downwards from the front surface of the optical chip wafer are formed through laser through holes, mechanical through holes or through hole etching processes, metal through hole filling is formed through electroplating filling, back surface leakage of the conductive through holes is realized through thinning of the back surface of the optical chip wafer, and wiring layers on the front surface and the back surface are manufactured. In yet another embodiment of the present invention, the wiring layers on the front and back sides of the optical chip wafer may be single-layered or multi-layered.
Then, at step 430, as shown in FIG. 3C, the electrical chips and cover plate are assembled on the top surface of the photo chip wafer. In one embodiment of the invention, the electrical chip is soldered, attached to the top surface of the wafer of the optical chip by flip-chip or wire bonding processes, and electrically connected to the wiring layer, and further electrically connected to the metal vias inside the optical chip. The cover plate can be fixedly arranged at a corresponding position above the groove of the optical chip through technologies such as adhesion, bonding and the like.
Next, at step 440, as shown in fig. 3D, the top surface of the photo chip wafer is encapsulated. The plastic layer covers the upper surface of the optical chip and covers the top wiring layer, the electric chip and the cover plate.
Then, at step 450, as shown in fig. 3E, external solder balls are formed under the wiring layer on the back surface of the photo chip wafer. In one embodiment of the present invention, bumps (bumps) or conductive copper pillars (bumps) may be formed by electroplating, and BGA solder balls may also be formed by a ball-mounting process.
Finally, in step 460, the individual package structures are singulated, as shown in fig. 3F.
A three-dimensional package structure of an optoelectronic chip with an optical interconnect interface according to yet another embodiment of the present invention is described in detail below with reference to fig. 5. Fig. 5 shows a schematic cross-sectional view of a three-dimensional package structure 500 for an optoelectronic chip with an optical interconnect interface, in accordance with yet another embodiment of the present invention. As shown in fig. 5, the three-dimensional package structure 500 for an optoelectronic chip with an optical interconnection interface further includes an optical chip 510, a conductive via 520, a first wiring layer 530, a second wiring layer 540, an electrical chip 550, a cover plate 560, a molding layer 570, an external solder ball 580, an optical interconnection structure 511, and an optical coupling structure 590.
The three-dimensional package structure 500 for an optoelectronic chip with an optical interconnect interface is different from the three-dimensional package structure 100 for an optoelectronic chip with an optical interconnect interface described above only in the shape of the cover plate 560, resulting in a different shape of the optical coupling structure.
Fig. 6 shows a schematic cross-sectional view 600 of an optoelectric chip three-dimensional package structure 500 with optical interconnect interface optically coupled to an external optical fiber according to yet another embodiment of the invention. As shown in fig. 6, the optical-to-electrical chip three-dimensional package structure with optical interconnection interface 500 and the structure 600 for coupling optical with external optical fiber further includes an optical-to-electrical chip three-dimensional package structure with optical interconnection interface 610/500, a substrate 620, an optical fiber 630, and an optical fiber coupler 640. The three-dimensional package structure 610/500 of the optoelectronic chip with the optical interconnection interface and the optical fiber coupler 640 are fixedly arranged on the substrate 620, and the optical fiber 630 is aligned to the optical coupling structure 590 of the three-dimensional package structure 610/500 of the optoelectronic chip with the optical interconnection interface through the optical fiber coupler 640, but does not enter the optical coupling structure 590, so that high-efficiency optical signal coupling connection is realized.
A three-dimensional package structure of an optoelectronic chip with an optical interconnect interface according to yet another embodiment of the present invention is described in detail below with reference to fig. 7. Fig. 7 shows a schematic cross-sectional view of a three-dimensional package structure 700 of an optoelectronic chip with an optical interconnect interface, in accordance with yet another embodiment of the present invention. As shown in fig. 7, the three-dimensional package structure 700 with optical interconnection interface further includes an optical chip 710, a conductive via 720, a first wiring layer 730, a second wiring layer 740, an electrical chip 750, a cover plate 760, a molding layer 770, an external solder ball 780, an optical interconnection structure 711, an optical coupling structure 790, and an optical fiber coupling efficiency enhancing structure 795.
The three-dimensional package structure 700 for an optoelectronic chip with an optical interconnection interface is different from the three-dimensional package structure 100 for an optoelectronic chip with an optical interconnection interface described above only in that an optical fiber coupling efficiency enhancing structure 795 is added to the optical coupling structure 790, and the optical fiber coupling efficiency enhancing structure 795 may be a lens or an isolator.
Fig. 8 shows a schematic cross-sectional view 800 of an optical coupling between an optical fiber and an external optical fiber based on the three-dimensional package structure 700 with optical interconnection interface according to still another embodiment of the present invention. As shown in fig. 8, the optical coupling structure 800 of the three-dimensional package structure 700 of the optoelectronic chip with optical interconnection interface and the external optical fiber further includes the three-dimensional package structure 810/700 of the optoelectronic chip with optical interconnection interface, a substrate 820, an optical fiber 830 and an optical fiber coupler 840. The three-dimensional package structure 810/700 of the optoelectronic chip with the optical interconnection interface and the optical fiber coupler 840 are fixedly arranged on the substrate 820, and the optical fiber 830 is aligned to the optical fiber coupling efficiency enhancing structure 795 and the optical coupling structure 790 of the three-dimensional package structure 810/700 of the optoelectronic chip with the optical interconnection interface through the optical fiber coupler 840, but does not enter the optical coupling structure 790, so that high-efficiency optical signal coupling connection is realized.
Based on the three-dimensional packaging structure of the photoelectric chip with the optical interconnection interface and the manufacturing method thereof, firstly, the optical interconnection structure and the groove are manufactured at the edge of the silicon optical chip; then, the electric chip and the cover plate patch are stacked on the silicon optical chip, and a hollow optical coupling structure is formed between the electric chip and the cover plate, and then, the packaging structure on the upper surface of the silicon optical chip is subjected to plastic packaging, and external solder balls electrically connected with the wiring layer on the lower surface of the silicon optical chip are formed, so that the three-dimensional packaging structure of the photoelectric chip with an optical interconnection interface is formed. The three-dimensional packaging structure of the photoelectric chip with the optical interconnection interface adopts the plastic packaging after stacking the electric chip and the optical chip, ensures the reliability of packaging interconnection, can realize the optical coupling of the optical chip, realizes shorter electric interconnection and smaller packaging area, and further realizes higher performance.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
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| CN112034567B (en) * | 2020-09-04 | 2022-07-05 | 华进半导体封装先导技术研发中心有限公司 | Photoelectric chip packaging structure and packaging method thereof |
| CN113589449A (en) * | 2021-06-21 | 2021-11-02 | 北京协同创新研究院 | Hybrid integrated system applied to photoelectric interconnection |
| CN116264223A (en) * | 2021-12-14 | 2023-06-16 | 中兴通讯股份有限公司 | Chip packaging structure and photoelectric device thereof |
| CN114355520A (en) * | 2021-12-30 | 2022-04-15 | 华进半导体封装先导技术研发中心有限公司 | Optical chip and electric chip packaging structure and preparation method thereof |
| CN114512589B (en) * | 2022-04-21 | 2022-06-17 | 威海三维曲板智能装备有限公司 | Photoelectric hybrid packaging structure and manufacturing method thereof |
| CN117408210A (en) * | 2022-07-06 | 2024-01-16 | 南京光智元科技有限公司 | Photoelectric packaging structure and photon computing system |
| CN115084046B (en) * | 2022-07-20 | 2022-11-08 | 威海市泓淋电力技术股份有限公司 | Hybrid integrated semiconductor package and manufacturing method thereof |
| CN115149394B (en) * | 2022-09-05 | 2022-11-15 | 山东中清智能科技股份有限公司 | Photoelectric device integrated packaging structure and manufacturing method thereof |
| CN115542478B (en) * | 2022-11-25 | 2023-04-07 | 之江实验室 | Three-dimensional packaging structure and packaging method based on photoelectric chip double-sided process |
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