CN108091629B - Photoelectric chip integrated structure - Google Patents

Abstract

The invention discloses an optoelectronic chip integrated structure, comprising: an optoelectronic chip and an electrical chip; one of the optoelectronic chip and the electrical chip is installed in a positive position, and the other is installed in a flip chip; at least one first part of the optoelectronic chip is installed A pad is arranged corresponding to at least one second pad of the electrical chip. In the present invention, the pads of the optoelectronic chip and the electric chip are placed oppositely and in corresponding positions through different methods of forward mounting and flipping, so that the corresponding pads can be connected by solder balls, or the pads can be directly bonded or contacted. The cross-sectional area of the solder ball or the contact area of the direct bond is larger than that of a bond wire connection, so the inductance is smaller, according to the formula

The smaller the inductance, the higher the frequency. Therefore, the frequency that can be achieved by solder ball connection or direct bonding of pads is higher, which can broaden the bandwidth of signal transmission between optoelectronic chips and electrical chips, and its relative bandwidth can reach 8% of traditional packaging. to 50 times.

Description

An optoelectronic chip integrated structure

technical field

The invention relates to the technical field of chip integration, in particular to an optoelectronic chip integration structure.

Background technique

Optical communication is a communication method that uses light waves as carriers. With the development of technology, the amount of communication data is getting larger and larger, so the requirements for the transmission rate of optical communication modules are getting higher and higher. Currently, 56Gbps and 112Gbps are the next-generation optical interconnect standards. The optoelectronic chip integrated structure is the core component of the optical communication module. The optoelectronic chip integration structure integrates optoelectronic chips (such as active optoelectronic chips such as lasers, modulators, detectors, or optoelectronic integrated chips with multiple structures) and the electrical chips of its peripheral circuits (such as the driver chips of optoelectronic chips) to realize optical The function of converting signals and electrical signals. The amount of communication data itself is increasing, and the optoelectronic chip and the electrical chip need to frequently convert the optical signal and the electrical signal, making the electrical characteristics of the interconnection between the two become a bottleneck in the bandwidth design of the integrated structure of the optoelectronic chip.

In the existing methods, optoelectronic chips and electrical chips are often organized on a dielectric substrate, and their pads are connected to the wiring layer of the dielectric substrate by means of bonding wires commonly used by those skilled in the art during chip integration, so that the unified wiring.

However, the inventors found that the bonding wires used in realizing the integrated structure of the optoelectronic chip in the existing way limit the bandwidth of the interconnection of the optoelectronic chip and it is difficult to widen it.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present invention provide an optoelectronic chip integrated structure to solve the problem that the bandwidth of the optoelectronic chip interconnection is limited and difficult to widen.

A first aspect of the present invention provides an optoelectronic chip integrated structure, comprising: an optoelectronic chip and an electrical chip; one of the optoelectronic chip and the electrical chip is installed in a front-mounted manner, and the other is installed in a flip-chip manner; At least one first pad is arranged corresponding to at least one second pad of the electrical chip.

Optionally, the optoelectronic chip integrated structure further includes: a package body; the optoelectronic chip is installed and embedded in the package body, and the first surface of the optoelectronic chip is flush with the first surface of the package body; The electrical chip is flip-chip disposed on the first surface of the package body.

Optionally, the optical functional components of the optoelectronic chip are located on the first surface of the optoelectronic chip.

Optionally, the package body is provided with at least one first via hole, which is respectively connected to at least one third pad of the electrical chip, and the first via hole extends from the first surface of the package body to the first via hole. Second surface.

Optionally, a hard block body is also embedded in the package body, and the exposed surface of the hard block body is flush with the surface of the package body; at least one first via hole is provided in the hard block body , respectively connected to at least one third pad of the electrical chip; the first via hole extends from the first surface to the second surface of the hard block.

Optionally, the first via hole is directly connected to the third pad.

Optionally, the optoelectronic chip integrated structure further includes: a first wiring layer disposed on the first surface of the package body; one end of the wire of the first wiring layer is respectively connected with at least one third part of the electrical chip. The pads are connected, or one end of the wire of the first wiring layer is respectively connected to at least one fourth pad of the optoelectronic chip; the other end is connected to the first via hole.

Optionally, the optoelectronic chip integrated structure further includes: a second wiring layer disposed on the second surface of the package body, one end of the wire of the second wiring layer is connected to the first via hole, and the other end is disposed solder balls.

Optionally, at least one fifth pad of the optoelectronic chip is exposed on the second surface of the package body, and solder balls are provided on the second surface of the package body at positions corresponding to the fifth pads .

Optionally, a second via hole is provided inside the optoelectronic chip, one end of the second via hole is connected to the pad of the optoelectronic chip, and the other end extends to the second surface of the optoelectronic chip to connect to solder balls or Wires of the wiring layer.

In the optoelectronic chip integrated structure provided by the embodiment of the present invention, the pads of the optoelectronic chip and the optoelectronic chip are placed relative to each other and the positions correspond to each other by different methods of front loading and flipping, so that the corresponding pads can be connected by solder balls, or the pads between the pads can be connected by solder balls. direct bond connections or contact connections. The cross-sectional area of the solder ball or the contact area of the direct bond is larger than that of a bond wire connection, so the inductance is smaller, according to the formula The smaller the inductance, the higher the frequency. Therefore, the frequency that can be achieved by solder ball connection or direct bonding of pads is higher, which can broaden the bandwidth of signal transmission between optoelectronic chips and electrical chips, and its relative bandwidth can reach 8% of traditional packaging. to 50 times. The above-mentioned optoelectronic chip integrated structure greatly shortens the trace length, reduces the signal delay and loss,

Description of drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are schematic and should not be construed as limiting the invention in any way, in which:

FIG. 1 shows a schematic diagram of an integrated structure of an optoelectronic chip according to an embodiment of the present invention;

FIG. 2 shows a schematic diagram of yet another optoelectronic chip integrated structure according to an embodiment of the present invention;

FIG. 3 shows a schematic diagram of yet another optoelectronic chip integrated structure according to an embodiment of the present invention;

FIG. 4 shows a schematic diagram of yet another optoelectronic chip integrated structure according to an embodiment of the present invention;

FIG. 5 shows a schematic diagram of yet another optoelectronic chip integrated structure according to an embodiment of the present invention.

Detailed ways

In order to make the purpose, advantages and preparation method of the present invention clearer, the following will describe the embodiments of the present invention in detail with reference to the accompanying drawings. In view of preferred materials of construction, it is apparent that the described embodiments are some, but not all, of the embodiments of the present invention. It should be noted that the embodiments described with reference to the accompanying drawings are exemplary, and the structural materials shown in the embodiments are also exemplary, and are only used to explain the present invention, but not to limit the present invention. The drawings are for illustrative purposes only and are not necessarily drawn to scale. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

Example 1

The embodiment of the present invention provides an optoelectronic chip integrated structure, and the integrated structure includes an optoelectronic chip 10 and an electrical chip 20 . One of the optoelectronic chip 10 and the electrical chip 20 is mounted on the front side, and the other is mounted on the flip side. The at least one first pad of the optoelectronic chip 10 is arranged corresponding to the at least one second pad of the electrical chip 20 . The first pad and the second pad may be connected by solder balls or by direct bonding of the pads, and the present application does not limit the connection method.

电感越小，频率越高，因此，通过焊球连接或焊盘直接键合所能达到的频率较高，从而能够拓宽光电芯片与电芯片信号传输的带宽，其相对带宽可达传统封装的8至50倍。上述光电芯片集成结构大大缩短了走线长度，降低了信号延迟与损耗。The above-mentioned optoelectronic chip integrated structure makes the pads of the optoelectronic chip and the electrical chip are placed relative to each other and the positions correspond to each other by different methods of forward loading and flipping, so that the corresponding pads can be connected by solder balls, or the pads can be directly bonded or connected. Contact connection. The cross-sectional area of the solder ball or the contact area of the direct bond is larger than that of a bond wire connection, so the inductance is smaller, according to the formula

The smaller the inductance, the higher the frequency. Therefore, the frequency that can be achieved by solder ball connection or direct bonding of pads is higher, which can broaden the bandwidth of signal transmission between optoelectronic chips and electrical chips, and its relative bandwidth can reach 8% of traditional packaging. to 50 times. The above-mentioned optoelectronic chip integrated structure greatly shortens the wiring length and reduces signal delay and loss.

The optoelectronic chip 10 in this application can be an active optoelectronic chip such as a laser, a modulator, a detector, or an optoelectronic integrated chip with multiple structures, and the material can be a silicon optoelectronic chip or a compound semiconductor such as indium, gallium, arsenic, and phosphorus. material, or silicon carbide, silicon nitride material.

As an optional implementation manner of this embodiment, as shown in FIG. 1 , the optoelectronic chip integrated structure includes a package body 30 , such as a plastic package body. The "encapsulation body" mentioned in this application is a block formed after the soft encapsulating colloid is cured. The optoelectronic chip 10 is installed and embedded in the package body 30 , and the first surface of the optoelectronic chip 10 is flush with the first surface of the package body 30 . For example, a soft encapsulant can be coated on the substrate first, then the optoelectronic chip 10 can be embedded in the encapsulant, and the optoelectronic chip 10 can be covered by the encapsulant. Level the first surface before curing. The package body 30 can be directly and seamlessly bonded to the optoelectronic chip 10 , so that the position and level of the optoelectronic chip 10 can be accurately fixed, so that other components can be accurately mounted based on the optoelectronic chip 10 .

As a modification of using the plastic package 30 to fix the optoelectronic chip 10 , a groove can be formed in the rigid block, and then colloid is applied to the bottom of the groove, and the optoelectronic chip 10 is pasted on the bottom of the groove. However, this embodiment has high requirements on the depth and bottom level of the grooves, and it is difficult for the general process to achieve very precise requirements; in addition, the optoelectronic chip 10 has only the bottom fixed, which is not stable enough in subsequent process steps.

The electrical chip 20 is flip-chip mounted on the first surface of the package body 30 . In this application, "flip-chip" refers to an arrangement with the pads facing down, and "front-loading" refers to an arrangement with the pads facing up.

The optoelectronic chip 10 has optical functional components 11 such as an optical coupling structure, which may be, for example, a grating, a mode-spot converter, or a waveguide structure. Optionally, the optical functional component 11 of the optoelectronic chip 10 is located on the first surface of the optoelectronic chip 10 , so as to facilitate the connection of the optical functional component 11 with other components (eg, the optical fiber 40 ).

The electrical chip 20 also has a third pad, which is located on the same surface of the electrical chip 20 as the second pad. The third pad can be drawn out through the wires of the wiring layer on the first surface of the package body 30, and solder balls are arranged at the ends of the wires. Or, as an optional implementation of this embodiment, the package body 30 is provided with at least one first via hole 50, which is respectively connected to at least one third pad of the electrical chip 20, and the first via hole 50 extends from the package body The first surface of 30 extends to the second surface. The first via hole 50 may be directly connected to the third pad through solder balls.

The "via hole" in this application is also called a metallized hole, which is a printed wire connecting the first surface and the second surface. A common hole is drilled at the intersection of the wires that need to be connected on the surface or at the position of the solder ball, and then a common hole is drilled on the surface. A layer of metal is plated on the cylindrical surface of the hole wall of the hole by chemical deposition.

As a side-by-side optional embodiment of the above-mentioned optional embodiments, as shown in FIG. 2 , the package body 30 is further embedded with a hard block body 60 , and the exposed surface of the hard block body 60 is flush with the surface of the package body 30 . flat. The hard block 60 is provided with at least one first via hole 50 , which is respectively connected to at least one third pad of the electrical chip 20 . The first via 50 extends from the first surface to the second surface of the hard block 60 . The first via hole 50 can be connected to the third pad, and a solder ball auxiliary connection can be provided therebetween.

Optionally, the optoelectronic integrated structure further includes a first wiring layer 70 , as shown in FIG. 4 , disposed on the first surface of the package body 30 . One ends of the wires of the first wiring layer 70 are respectively connected with at least one third pad of the electrical chip 20 (the case is not shown in the figure); A fourth pad (shown at 12 in Figure 4) is connected. The other ends of the wires of the first wiring layer 70 are connected to the first via holes 50 . Optionally, the first wiring layer 70 can also be replaced by the wiring block 120 shown in FIG. 5 , that is, the wiring structure is pre-arranged on the wiring block 120 , and the wiring block 120 is directly used for the fabrication of the optoelectronic chip integrated structure. Just assemble. Through the first wiring layer or the wiring block, the optoelectronic chip or the pads of the optoelectronic chip are fan-out designed, which can facilitate the wiring of the optoelectronic integrated structure. An insulating layer 80 may also be provided on the surface of the first wiring layer 70 .

Optionally, the optoelectronic chip integrated structure further includes a second wiring layer 90 disposed on the second surface of the package body 30 , one end of the wire of the second wiring layer 90 is connected to the first via hole 50 , and the other end is provided with solder balls. Through the second wiring layer, the solder balls can be more evenly distributed on the second surface of the package body, so as to balance the overall electrical characteristics. An insulating layer 100 may also be provided on the surface of the second wiring layer 90 .

As an optional implementation of this embodiment, as shown in FIG. 3 , at least one fifth pad of the optoelectronic chip 10 is exposed on the second surface of the package body 30 through a thinning process, and the second surface of the package body 30 exposes at least one fifth pad of the optoelectronic chip 10 . Solder balls are provided at the positions corresponding to the fifth pads, so that the signals (eg, low-frequency signals) on the second surface of the optoelectronic chip 10 can be directly drawn out, which facilitates the wiring of the optoelectronic chip integrated structure.

Optionally, a second via hole 110 is provided inside the optoelectronic chip 10 , one end of the second via hole 110 is connected to the pad of the optoelectronic chip 10 , and the other end extends to the second surface of the optoelectronic chip 10 to connect to the solder ball or the wiring layer. wire. By arranging the second via hole inside the optoelectronic chip 10, the signal on the first surface of the optoelectronic chip 10 can be directly drawn out, which facilitates the wiring of the optoelectronic chip integrated structure.

Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art can make various changes, substitutions and alterations in these embodiments without departing from the spirit of the invention and the scope of protection defined by the appended claims, Such modifications and variations are within the scope defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of the process steps may be varied while remaining within the scope of the present invention.

Furthermore, the scope of application of the present invention is not limited to the process, mechanism, manufacture, composition of matter, means, method and steps of the specific embodiments described in the specification. From the disclosure of the present invention, as those of ordinary skill in the art, it will be easily understood by those of ordinary skill in the art that there are currently existing or will be developed in the future for the process, mechanism, manufacture, composition of matter, means, method or step, wherein they perform the same as the present invention. Corresponding embodiments described that function substantially the same or achieve substantially the same results can be applied in accordance with the present invention. Accordingly, the appended claims of this invention are intended to include within their scope such processes, mechanisms, manufacture, compositions of matter, means, methods, or steps.

Claims (9)

1. a photoelectric chip integrated structure, is characterized in that, comprises: photoelectric chip and electric chip; One of the optoelectronic chip and the electrical chip is disposed in a front-mounted manner, and the other is disposed in a flip-chip manner; at least one first pad of the optoelectronic chip is disposed corresponding to at least one second pad of the electrical chip; Wherein, a second via hole is provided inside the optoelectronic chip, one end of the second via hole is connected to the pad of the optoelectronic chip, and the other end extends to the second surface of the optoelectronic chip to connect to the solder ball or wiring layer wire. 2. The optoelectronic chip integrated structure according to claim 1, further comprising: a package body; The optoelectronic chip is mounted and embedded in the package body, and the first surface of the optoelectronic chip is flush with the first surface of the package body; the electrical chip is flip-chip mounted on the first surface of the package body . 3 . The optoelectronic chip integrated structure according to claim 2 , wherein the optical functional components of the optoelectronic chip are located on the first surface of the optoelectronic chip. 4 . 4 . The optoelectronic chip integrated structure according to claim 3 , wherein at least one first via hole is provided in the package body, which is respectively connected to at least one third pad of the electrical chip, and the first via hole is formed in the package body. 5 . Vias extend from the first surface to the second surface of the package body. 5 . The optoelectronic chip integrated structure according to claim 3 , wherein a hard block is embedded in the package body, and the exposed surface of the hard block body is flush with the surface of the package body; 6 . The hard block is provided with at least one first via hole, which is respectively connected with at least one third pad of the electrical chip; the first via hole extends from the first surface of the hard block to the first via hole. Second surface. 6 . The optoelectronic chip integrated structure according to claim 4 , wherein the first via hole is directly connected to the third pad. 7 . 7. The optoelectronic chip integrated structure according to claim 4 or 5, characterized in that, further comprising: The first wiring layer is arranged on the first surface of the package body; one end of the wires of the first wiring layer is respectively connected to at least one third pad of the electrical chip, or the wires of the first wiring layer are respectively connected One end is respectively connected with at least one fourth pad of the optoelectronic chip; the other end is connected with the first via hole. 8. The optoelectronic chip integrated structure according to claim 4 or 5, characterized in that, further comprising: The second wiring layer is disposed on the second surface of the package body, one end of the wire of the second wiring layer is connected to the first via hole, and the other end is provided with a solder ball. 9 . The optoelectronic chip integrated structure according to claim 2 , wherein at least one fifth pad of the optoelectronic chip is exposed on the second surface of the package body, and is on the second surface of the package body. 10 . Solder balls are provided at positions corresponding to the fifth pads.

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