CN110858565B - Semiconductor device and method of forming the same - Google Patents

Abstract

The invention discloses a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate and a fin part, wherein the semiconductor substrate is divided into a PMOS area and an NMOS area, the fin part comprises a P area fin part and an N area fin part, and the P area fin part and the N area fin part are respectively and correspondingly formed above the PMOS area and the NMOS area; forming a first protective layer covering the surface of the fin part; forming an interlayer dielectric layer between the adjacent fin parts; and removing part of the interlayer dielectric layer and part of the first protection layer to expose the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part, wherein the width dimension of the P-region fin part at the exposed side wall is smaller than that of the N-region fin part at the exposed side wall. The smaller width of the P region fin part increases the control capability of a subsequent grid structure on a device, effectively inhibits the short channel effect and improves the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming the same.

Background technique

The emergence of FinFET technology and structure has made semiconductor devices develop in the direction of smaller size. However, due to the reduction of the structure size and the compactness between the structures, short-channel effects are easily generated, and accompanied by the occurrence of leakage, the control ability of the gate structure is weakened, and the performance of the semiconductor device is reduced.

Therefore, there is an urgent need for a method for forming a semiconductor device with improved controllability of a gate structure and a corresponding semiconductor device.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a method for forming a semiconductor device, so that the width of the fins in the P region and the widths of the fins in the N region are different, thereby improving the controllability of the gate structure.

The invention discloses a method for forming a semiconductor device, comprising: providing a semiconductor substrate and a fin, the semiconductor substrate includes a PMOS region and an NMOS region, the fin includes a P-region fin and an N-region fin, the P-region fin and The N-region fins are respectively formed over the PMOS region and the NMOS region; a first protective layer covering the surface of the fins is formed; an interlayer dielectric layer is formed between adjacent fins; part of the interlayer dielectric layer and part of the first protective layer are removed layer to expose the upper sidewalls of the P region fins and the upper sidewalls of the N region fins, and the width dimension of the P region fins at the exposed sidewalls is smaller than the width dimension of the N region fins at the exposed sidewalls.

According to one aspect of the present invention, the process step of exposing the sidewalls of the upper part of the fins of the P region and the sidewalls of the upper part of the fins of the N region includes: etching a part of the interlayer dielectric layer to expose the first layer formed on the upper part of the fins of the P region. protective layer; etching the exposed first protective layer on the upper part of the fins in the P region; etching part of the interlayer dielectric layer formed in the NMOS region to expose the first protective layer formed on the upper part of the fins in the N region; and etching and removing the NMOS The exposed first protective layer and the remaining first protective layer or the P-region fins on the upper part of the P-region fins are etched.

According to one aspect of the present invention, the process step of exposing the upper sidewall of the P-region fin part and the sidewall of the N-region fin part upper part includes: etching part of the interlayer dielectric layer to expose the upper part of the N-region fin part and the P-region fin part upper part; etching part of the first protective layer formed on the upper part of the fin part of the P region; and etching and removing the first protective layer formed on the upper part of the fin part of the N region and etching the remaining first protective layer or P on the upper part of the fin part of the P region District fins.

According to an aspect of the present invention, after exposing the sidewalls of the upper part of the fins of the P region and the sidewalls of the upper part of the fins of the N region, the width of the upper part of the fins of the P region is smaller than the width of the lower part of the fins of the P region.

According to one aspect of the present invention, after forming the first protective layer and before forming the interlayer dielectric layer, the method further includes: forming a sacrificial layer between adjacent fins; removing part of the sacrificial layer to expose part of the first protective layer formed in the PMOS region A protective layer; removing the exposed first protective layer of the PMOS region to expose part of the P-region fins; removing the remaining sacrificial layer to expose the remaining first protective layer; and on the surface of the first protective layer and the exposed P-region fins A second protective layer is formed on the surface, and the protective layer includes a first protective layer and a second protective layer;

According to an aspect of the present invention, the process steps of exposing part of the sidewall of the P-region fin and part of the N-region fin part include: removing part of the interlayer dielectric layer to expose part of the second protective layer; and removing the exposed part by etching a second protective layer to expose the P-region fins and the first protective layer on the N-region fins; and etch and remove the exposed first protective layer and the exposed P-region fins formed on the N-region fins.

According to one aspect of the present invention, the material of the protective layer includes one or more combinations of SiN _x , SiO ₂ or α-Si .

According to one aspect of the present invention, the thickness dimension of the first protective layer or the second protective layer ranges from

According to an aspect of the present invention, after the interlayer dielectric layer is formed, the thickness of the protective layer on the upper surface of the fin portion of the P region is smaller than the thickness of the protective layer on the upper surface of the fin portion of the N region.

According to an aspect of the present invention, after the interlayer dielectric layer is formed, the thickness of the protective layer on the upper surface of the fins in the P region is smaller than the thickness of the protective layer on the lower surface of the fins in the P region, and the thickness of the protective layer on the lower surface of the fins in the P region is the same as the thickness of the protective layer on the lower surface of the fins in the N region. The thickness of the protective layer on the lower surface of the part is equal.

According to one aspect of the present invention, the process of forming the interlayer dielectric layer includes a fluid chemical vapor deposition process.

According to an aspect of the present invention, after forming the interlayer dielectric layer, the method further includes performing an annealing process on the interlayer dielectric layer.

According to one aspect of the present invention, the steps of the annealing process include: firstly performing a water vapor annealing process, and then performing a rapid thermal annealing process.

According to one aspect of the present invention, the process parameters of the water vapor annealing process include: the annealing temperature ranges from 550°C to 750°C, the annealing time ranges from 30min to 200min, and the process parameters of the rapid thermal annealing process include: the annealing temperature ranges from 950°C to 1050°C ℃, the annealing time ranges from 15min to 100min.

According to an aspect of the present invention, the width dimension of the N-region fin at the exposed sidewall is l ₂ , and the P-region fin at the exposed side wall has a width dimension of l ₁ , so 0.7≤l ₁ : l ₂ ≤0.9.

According to one aspect of the present invention, 1 nm≤l2-l1≤2.5nm.

Correspondingly, the present invention also provides a semiconductor device, comprising: a semiconductor substrate and a fin, the semiconductor substrate includes a PMOS region and an NMOS region, the fin includes a P-region fin and an N-region fin, and the P-region fin and N-region fins The area fins are respectively arranged above the PMOS area and the NMOS area, the width dimension of the upper part of the fin part of the P area is smaller than the width dimension of the upper part of the fin part of the N area; the protective layer, the protective layer is arranged on the surface of the lower part of the fin part; and the interlayer dielectric layer , the interlayer dielectric layer is formed between adjacent fins.

According to an aspect of the present invention, the width dimension of the upper portion of the fins in the N region is l ₂ , and the width dimension of the upper portion of the fins in the P region is l ₁ , so 0.7≦l ₁ : l ₂ ≦0.9.

According to one aspect of the present invention, 1 nm≦1 _{2 −1 1} ≦2.5 nm.

According to one aspect of the present invention, the protective layer includes a first protective layer and a second protective layer, and the second protective layer is disposed between the interlayer dielectric layer and the first protective layer.

According to one aspect of the present invention, the width dimension of the upper portion of the fin portion of the P region is smaller than the width dimension of the lower portion of the fin portion of the P region.

Compared with the existing technical solutions, the technical solutions of the present invention have the following advantages:

In the method for forming a semiconductor device according to an embodiment of the present invention, the width of the P-region fins at the exposed sidewalls is smaller than the width of the N-region fins at the exposed sidewalls. The width of the exposed sidewalls of the fins in the P region is small, so that a fully depleted electron layer can be formed in the channel of the P region, the control ability of the gate structure is improved, and the short channel effect is suppressed at the same time.

Further, the interlayer dielectric layer is formed by a fluid chemical vapor deposition process. This process can ensure that the formed interlayer dielectric layer structure is relatively dense and reduces defects.

Further, the annealing process of the interlayer dielectric layer includes first performing a water vapor annealing process, and then performing a rapid thermal annealing process. The water vapor annealing process can eliminate hydrogen bonds or nitrogen bonds in the interlayer dielectric layer and reduce impurities. At the same time, the rapid thermal annealing process can accelerate the formation of the interlayer dielectric layer.

Correspondingly, an embodiment of the present invention further provides a semiconductor device, wherein the width of the upper portion of the fin portion of the P region is smaller than the width dimension of the upper portion of the fin portion of the N region. The smaller width dimension of the fins in the P region can form a full electron depletion layer in the subsequent channel, which improves the control ability of the gate structure and suppresses the short channel effect.

Description of drawings

1-5 are schematic diagrams of process structures of a method for forming a semiconductor device according to an embodiment of the present invention;

6-8 are schematic structural diagrams of a process of a method for forming a semiconductor device according to another embodiment of the present invention;

9-10 are schematic diagrams of process structures of a method for forming a semiconductor device according to still another embodiment of the present invention.

Detailed ways

As mentioned above, the existing semiconductor devices have the problems that the gate structure control ability is weak, and the short channel effect exists at the same time.

After research, it was found that the reason for the above problem is: when no voltage is applied, there are still a small number of carriers in the channel, and the accumulation of carriers is likely to cause short channel effects, and leakage occurs at the same time, reducing the control of the gate structure on the device. Ability.

In order to solve this problem, the present invention provides a method for forming a semiconductor device and a semiconductor device. A fully depleted layer of electrons is formed in the channel of the fin portion of the P region to consume all the excess electrons. When no voltage is applied, no The existence of excess carriers solves the above problem.

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the scope of the invention unless specifically stated otherwise.

In addition, it should be understood that, for ease of description, the dimensions of various components shown in the drawings are not necessarily drawn to an actual scale relationship, for example, the thickness or width of some layers may be exaggerated relative to other layers.

The following description of exemplary embodiments is illustrative only and is not intended to limit the invention, its application or use in any way.

Techniques, methods, and apparatuses known to those of ordinary skill in the relevant art may not be discussed in detail, but where applicable, these techniques, methods, and apparatuses should be considered part of this specification.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined or described in one figure, it will not need to be further explained in the description of subsequent figures discuss.

first embodiment

Referring to FIG. 1 , a semiconductor substrate 100 is provided with fins.

The semiconductor substrate 100 serves as a process basis for forming semiconductor devices. The material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), and silicon-on-insulator (S-SiGeOI) Silicon germanium (SiGeOI), etc. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon. In addition, the semiconductor substrate 100 may also include other structures, such as structures such as metal plugs, metal connection layers, and dielectric layers, or other semiconductor devices including these structures, which are not specifically limited here.

In the embodiment of the present invention, the semiconductor substrate 100 includes a PMOS region and an NMOS region, and a fin is disposed above the semiconductor substrate 100, as shown in the figure. P-region fins 101 and N-region fins 102 are respectively provided above the PMOS region and the NMOS region. In the embodiment of the present invention, the material of the fin is the same as the material of the semiconductor substrate 100 .

The embodiment of the present invention further includes forming a first protective layer 110 covering the surface of the fin. The first protective layer 110 is used to protect the fins to avoid excessive wear of the fins in subsequent processes. At the same time, when the interlayer dielectric layer is subsequently formed, the fins are also prevented from being pulled by stress.

The material of the first protective layer 110 includes one or more combinations of SiN _x , SiO ₂ or α-Si. Specifically, in the embodiment of the present invention, the material of the first protective layer 110 is SiN _x .

(在这里，厚度范围为大于等于

小于等于

即范围包括端点数值，下文的范围表述与此处的意义相同)。具体的，在本发明实施例中，第一保护层 110的厚度为

在本发明的另一个实施例中，第一保护层110的厚度为

在本发明的又一个实施例中，第一保护层110的厚度为

The thickness range of the first protective layer 110 is

(Here, the thickness range is greater than or equal to

less than or equal to

That is, the range includes the endpoint values, and the following range expressions have the same meaning as herein). Specifically, in the embodiment of the present invention, the thickness of the first protective layer 110 is

In another embodiment of the present invention, the thickness of the first protective layer 110 is

In yet another embodiment of the present invention, the thickness of the first protective layer 110 is

In the embodiment of the present invention, the first protective layer 110 also covers the surface of the semiconductor substrate 100 . Covering both the semiconductor substrate 100 and the surface of the fins at the same time can facilitate the implementation of the process. In other embodiments of the present invention, the first protective layer 110 may only cover the surface of the fin, which is not specifically limited here.

Referring to FIG. 2 , a sacrificial layer 120 is formed between adjacent fins, and then a part of the surface of the P-region fins 101 is exposed.

The sacrificial layer 120 is formed to etch and remove the first protective layer 110 at a specific position, thereby exposing the fin in a specific area. As in the embodiment of the present invention, after the sacrificial layer 120 is formed, part of the sacrificial layer 120 above the fins 101 in the P region is etched and removed to expose part of the first protection layer 110 in the PMOS region. In the embodiment of the present invention, after exposing part of the first protective layer 110 in the PMOS region, the method further includes removing the exposed first protective layer 110 to expose part of the fins in the P region.

The purpose of exposing the P-region fins 101 is to make the thicknesses of the protective layers at the positions of the N-region fins 102 and the P-region fins 101 not equal.

It should be noted that, in the embodiment of the present invention, when the exposed first protective layer 110 is removed to expose the P-region fins 101 , the P-region fins 101 may be appropriately etched, so that the width dimension of the exposed portion of the P-region fins 101 smaller than the N-region fins 102 . In other embodiments of the present invention, the P-region fins 101 may not be etched here, which is not specifically limited here.

Referring to FIG. 3 , the remaining sacrificial layers are removed, and a second protective layer 130 is formed on the surfaces of the first protective layer 110 and the exposed P-region fins 101 .

The second protective layer 130 is formed to further protect the fins from being over-etched subsequently.

The thickness dimension of the second protective layer 130 may be equal to or not equal to that of the first protective layer 110 . Specifically, in the embodiment of the present invention, the thickness dimension of the second protective layer 130 is equal to that of the first protective layer 110 . The material of the second protective layer 130 may be the same as or different from that of the first protective layer 110 . Specifically, in the embodiment of the present invention, the material of the second protective layer 130 is different from the material of the first protective layer 110 , and the material of the second protective layer 130 is a combination of SiN _x and α-Si .

In the embodiment of the present invention, the protective layer includes a first protective layer 110 and a second protective layer 130. Controlling the material types or thicknesses of the two protective layers facilitates subsequent partial etching of the P-region fins 101 , and more precisely controls the end point of the etching to avoid making the width of the P-region fins 101 exceed a specific range and affect the final semiconductor device performance.

Likewise, since the first protective layer 110 covers over the semiconductor substrate 100 , the second protective layer 130 is also formed over the semiconductor substrate 100 . In other embodiments of the present invention, the second protective layer 130 may also be formed only on the fin, which is not specifically limited here.

Referring to FIG. 4 , an interlayer dielectric layer 140 is formed between adjacent fins.

The interlayer dielectric layer 140 is formed to etch the protective layers on the surfaces of the P-region fins 101 and the N-region fins 102 at the same time, so as to control the synchronous degree of etching and to make the height dimensions of the exposed fins consistent.

The process of forming the interlayer dielectric layer 140 includes a fluid chemical vapor deposition process (Flowable Chemical Vapor Deposition, FCVD). The FCVD process can flow and fill the required materials, so that the formed interlayer dielectric layer 140 is relatively dense and has fewer defects.

In the embodiment of the present invention, the method further includes performing an annealing process on the formed interlayer dielectric layer 140 . The annealing process can make the interlayer dielectric layer 140 more dense, and simultaneously shape the interlayer dielectric layer 140 and relieve stress.

Specifically, in the embodiment of the present invention, the process steps of annealing the interlayer dielectric layer 140 include: first performing a water vapor annealing process, and then performing a rapid thermal annealing process. Since there are redundant hydrogen bonds or nitrogen bonds in the liquid material, water vapor is introduced at a relatively low temperature to introduce oxygen into the unformed interlayer dielectric layer 140 to eliminate hydrogen bonds or nitrogen bonds and ensure the final interlayer dielectric. Layer 140 contains less impurities. Rapid thermal annealing can accelerate the formation of the interlayer dielectric layer 140 .

In the embodiment of the present invention, the process parameters of the water vapor annealing process include: the annealing temperature ranges from 550° C. to 750° C. and the annealing time ranges from 30 min to 200 min. The process parameters of the rapid thermal annealing process include: the annealing temperature ranges from 950° C. to 1050° C. and the annealing time ranges from 15 min to 100 min. Specifically, in the embodiment of the present invention, the temperature of the water vapor annealing is 750° C., and the annealing time is 30 min. The temperature of the rapid thermal annealing process was 1050° C., and the annealing time was 15 min. In another embodiment of the present invention, the temperature of the water vapor annealing is 550°C, and the annealing time is 200 minutes. The temperature of the rapid thermal annealing process was 950° C., and the annealing time was 100 min. In yet another embodiment of the present invention, the temperature of the water vapor annealing is 600°C, and the annealing time is 100 min. The temperature of the rapid thermal annealing process is 1000° C., and the annealing time is 60 min.

In the embodiment of the present invention, after the interlayer dielectric layer 140 is formed, the fin portion is divided into two parts: the upper portion of the fin portion and the lower portion of the fin portion. Here, the upper and lower parts of the fins are divided according to the standard of the P-region fins 101 : the range of the P-region fins 101 not in contact with the first protective layer 110 is called the upper part of the fins, on the contrary, it is in contact with the first protective layer 110 The area of is called the lower part of the fin, and the meaning of the upper part of the fin and the lower part of the fin is the same as the meaning here. In the embodiment of the present invention, the ranges specified by the upper part of the fin part and the lower part of the fin part are also applicable to the N-region fin part 102 .

Obviously, in the embodiment of the present invention, since the first protective layer 110 and the second protective layer 130 are formed on the upper part of the N-region fins 102 , and only the second protective layer 130 is formed on the upper part of the P-region fins 101 , so when forming After the interlayer dielectric layer 140 , the thickness of the protective layer on the upper surface of the fin portion 101 in the P region is smaller than the thickness of the protective layer on the upper surface of the fin portion 102 in the N region. The thickness of the upper protective layer of the N-region fins 102 and the P-region fins 101 is inconsistent, so that when the protective layer is subsequently removed to expose the upper part of the fins, the width of the exposed part of the P-region fins 101 and the exposed part of the N-region fins 102 are reached. Purpose of unequal widths.

In addition, in the embodiment of the present invention, since only the first protective layer 110 is formed on the upper surface of the fin portion 101 in the P region, and the first protective layer 110 and the second protective layer 130 are formed on the lower surface of the fin portion 101 in the P region, the P region The thickness of the protective layer on the upper surface of the region fins 101 is smaller than the thickness of the protective layer on the lower surface of the P region fins 101 . Obviously, the thickness of the protective layer on the lower surface of the fin portion 101 in the P region is equal to the thickness of the protective layer on the lower surface of the fin portion 102 in the N region. The thickness of the protective layer on the lower surface of the P-region fin 101 and the lower surface of the N-region fin 102 is equal, so that when the interlayer dielectric layer 140 is formed, the pulling of the interlayer dielectric layer 140 to the lower part of the fin part is weakened, and the formation of the interlayer dielectric is buffered. The stress generated by layer 140 protects the fins. At the same time, there is a thicker protective layer at the lower part of the fin, which further improves the control ability of the fin.

Referring to FIG. 5 , part of the interlayer dielectric layer 140 and part of the protective layer are removed to expose the upper part of the fin.

In the embodiment of the present invention, the step of exposing the fins includes: after removing part of the interlayer dielectric layer 140 , exposing part of the second protective layer 130 , and then removing the exposed second protective layer 140 by etching to expose the P-region fins portion 101 and the first protective layer 110 on the N-region fins 102, and then the exposed first protective layer 110 and the exposed P-region fins 101 on the N-region fins 102 are removed by etching, exposing the N-region fins Part of the sidewall of 102 and part of the sidewall of the P-region fin 101 .

Obviously, when starting to etch and remove the first protective layer 110 on the N-region fins 102, part of the side surfaces of the P-region fins 101 have been exposed, so the first protective layer 110 on the N-region fins 102 is etched During the process, the fins 101 of the P region are also partially etched. Therefore, after the first protective layer 110 on the N-region fins 102 is finally removed, the width dimension _l1 of the P-region fins 101 at the exposed sidewalls is smaller than the width _l2 of the N-region fins 102 at the exposed sidewalls .

Obviously, after the sidewalls of the P-region fins 101 and the N-region fins 102 are exposed, the width of the upper part of the P-region fins 101 is smaller than the width of the lower part of the P-region fins 101.

In the embodiment of the present invention, after the gate structure, the source/drain and the channel are subsequently formed on the exposed P-region fins 101 and N-region fins 102 , the narrower P-region fins 101 can make the source/drain intermediate The holes diffuse to the channel, and the electrons in the channel are depleted, that is, a fully depleted layer of electrons is formed. The control ability of the semiconductor device effectively suppresses the short channel effect and improves the performance of the semiconductor device. At the same time, the leakage phenomenon is avoided when no voltage is applied. Further, compared with the upper part of the P-region fin part 101 , the upper part of the N-region fin part 102 has a larger width ₁₂ , which can reduce parasitic resistance and improve the performance of the semiconductor device after the subsequent structure is formed.

Since the materials of the fin portion and the protective layer are different, the etching rate and the etching degree of the fin portion 101 in the P region and the first protective layer 110 are different from each other in the etching process. Therefore, in the embodiment of the present invention, 0.7≤l ₁ :l ₂ ≤0.9, and 1nm≤l ₂ -l ₁ ≤2.5nm. Specifically, in the embodiment of the present invention, l ₁ :l ₂ =0.7, and l ₂ -l ₁ =1 nm.

To sum up, in the method for forming a semiconductor device disclosed in the present invention, the width of the fins in the P region is smaller than the width of the fins in the N region at the channel, so a fully depleted electron layer is formed in the channel of the P region, which improves the gate The control ability of the pole structure on the semiconductor device can effectively suppress the short channel effect and improve the performance of the semiconductor device.

Correspondingly, please continue to refer to FIG. 5 , an embodiment of the present invention further provides a semiconductor device including: a semiconductor substrate 100 and a fin.

The semiconductor substrate 100 includes a PMOS region and an NMOS region, the fins include a P-region fin and an N-region fin, and the P-region fins and the N-region fins are respectively disposed above the PMOS region and the NMOS region.

The semiconductor substrate 100 serves as a process basis for forming semiconductor devices. The material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), and silicon-on-insulator (S-SiGeOI) Silicon germanium (SiGeOI), etc. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon. In addition, the semiconductor substrate 100 may also include other structures, such as structures such as metal plugs, metal connection layers, and dielectric layers, or other semiconductor devices including these structures, which are not specifically limited here.

In the embodiment of the present invention, the material of the fin is the same as that of the semiconductor substrate 100 .

In the embodiment of the present invention, the width dimension l ₁ of the upper portion of the fin portion 101 in the P region is smaller than the width dimension l ₂ of the upper portion of the fin portion 102 in the N region. After the channel is subsequently formed on the fin, the narrower P-region fin 101 can allow holes to diffuse into the channel and form a fully depleted layer of electrons in the channel, which improves the control capability of the gate structure and effectively suppresses short circuits. The channel effect improves the performance of semiconductor devices. Meanwhile, the wider N-region fins 102 can reduce parasitic resistance and improve the performance of the semiconductor device.

In the embodiment of the present invention, 0.7≤l ₁ :l ₂ ≤0.9, and 1nm≤l ₂ -l ₁ ≤2.5nm. Specifically, in the embodiment of the present invention, l ₁ :l ₂ =0.7, and l ₂ -l ₁ =1 nm.

The embodiment of the present invention further includes a protective layer. The protective layer is arranged on the surface of the lower part of the fin. The protective layer is used to protect the fins and prevent the fins from being pulled by the stress of the interlayer dielectric layer 140 .

In the embodiment of the present invention, the protective layer includes a first protective layer 110 and a second protective layer 130. The second protective layer 130 is disposed between the interlayer dielectric layer 140 and the first protective layer 110 .

The material of the protective layer includes one or more combinations of SiN _x , SiO ₂ or α-Si. In the embodiment of the present invention, the materials of the first protective layer 110 and the second protective layer 130 are different, the material of the first protective layer 110 is SiN _x , and the material of the second protective layer 130 is a combination of SiN _x and α-Si . In other embodiments of the present invention, the materials of the first protective layer 110 and the second protective layer 130 may be the same.

具体的，在本发明实施例中，第一保护层110和第二保护层130的厚度相等，均为

在本发明的其他实施例中，第一保护层110和第二保护层130的厚度可以不相等。The thickness range of the first protective layer 110 or the second protective layer 130 is

Specifically, in the embodiment of the present invention, the thicknesses of the first protective layer 110 and the second protective layer 130 are equal, and both are

In other embodiments of the present invention, the thicknesses of the first protective layer 110 and the second protective layer 130 may not be equal.

Here, the lower part of the fin is the area where the fin is in contact with the first protective layer 110 , whereas the upper part of the fin is the area where the fin is not in contact with the first protective layer 110 , please refer to FIG. 5 .

Obviously, in the embodiment of the present invention, the width dimension of the upper portion of the fin portion of the P region is smaller than the width dimension of the lower portion of the fin portion of the P region.

The embodiment of the present invention further includes: an interlayer dielectric layer 140 . The interlayer dielectric layer 140 plays a role of isolation.

The interlayer dielectric layer 140 is formed between adjacent fins. And in the embodiment of the present invention, the interlayer dielectric layer 140 covers the lower part of the fin.

To sum up, in the semiconductor device provided by the embodiments of the present invention, the width of the fins in the P region is smaller than the width of the fins in the N region. Therefore, a full electron depletion layer is formed in the channel of the P region, which improves the gate structure to the semiconductor device. The control ability can effectively suppress the short channel effect and improve the performance of the semiconductor device.

Second Embodiment

Please refer to FIG. 6-FIG. 8. The difference between the second embodiment and the first embodiment is that the sacrificial layer and the second protective layer are not formed. An interlayer dielectric layer is formed therebetween. Other process steps are the same as in the first embodiment.

Referring to FIG. 6 , after an interlayer dielectric layer 240 is formed between adjacent fins, the P-region fins 201 are exposed by etching.

For the functions of the semiconductor substrate 200 and the fins and the selection of materials, please refer to the first embodiment.

The interlayer dielectric layer 240 makes the process steps of exposing the P-region fins and the N-region fins asynchronous, and also plays a role of isolation.

For the process steps of forming the interlayer dielectric layer 240 and the process steps of the subsequent annealing, please refer to the first embodiment, which will not be repeated here.

The embodiment of the present invention further includes: etching part of the interlayer dielectric layer 240 to expose the first protective layer 210 on the upper part of the P-region fins 201, and then etching the exposed first protective layer 210 on the upper part of the P-region fins 201. Etching only the first protective layer 210 on the upper part of the P-region fins 201 can ensure that in the subsequent process, the thickness of the first protective layer 210 on the upper part of the N-region fins 202 is always greater than the thickness of the first protective layer 210 on the upper part of the P-region fins 201 .

Specifically, in the embodiment of the present invention, the first protective layer 210 on the upper portion of the P-region fins 201 is completely removed, and the P-region fins 201 are exposed.

It should be noted that, in other embodiments of the present invention, only part of the first protective layer 210 on the upper part of the P-region fins 201 may be removed, as long as the thickness of the remaining first protective layer 210 on the upper part of the P-region fins 201 is less than N The thickness of the first protective layer 210 on the upper portion of the fin portion 202 is sufficient.

In the embodiment of the present invention, the division standard of the upper part of the fin part and the lower part of the fin part is the same as that of the first embodiment, which is not repeated here.

Referring to FIGS. 7-8 , the first protective layer 210 on the upper portion of the N-region fins 202 is exposed.

The embodiment of the present invention further includes: etching a part of the interlayer dielectric layer 240 formed in the NMOS region to expose the first protective layer 210 formed on the upper part of the fin portion 202 of the N region. Then, the exposed first protective layer 210 in the NMOS region is removed by etching, and the P region fins 201 are etched at the same time to expose the upper sidewalls of the P region fins 201 and the upper sidewalls of the N region fins 202 .

In the embodiment of the present invention, since the thickness of the first protective layer 210 on the upper part of the P-region fins 201 is smaller than the thickness of the first protective layer 210 on the upper part of the N-region fins 202 , after the etching is terminated, the P-region fins 201 are on the exposed side The width dimension l ₁ at the walls is smaller than the width dimension l ₂ of the N-region fins 202 at the exposed sidewalls. For the size relationship between _l1 and _l2 , please refer to the first embodiment. Specifically, in the embodiment of the present invention, l ₁ :l ₂ =0.9, and l ₂ -l ₁ =2.5 nm.

Correspondingly, please continue to refer to FIG. 8 , an embodiment of the present invention also provides a semiconductor device, the positional relationship of the structure, the material selection and function of each structure, please refer to the first embodiment, and will not be repeated here.

Since the second protective layer is not formed in the embodiment of the present invention, the interlayer dielectric layer 240 covers the surface of the first protective layer 210 .

Specifically, in the embodiment of the present invention, l ₁ :l ₂ =0.9, and l ₂ -l ₁ =2.5 nm.

Third Embodiment

Referring to FIGS. 9-10 , the difference between the third embodiment and the second embodiment is that after etching part of the interlayer dielectric layer, the first protective layer on the upper part of the N-region fins and the P-region fins is exposed at the same time. For the same, please refer to the second embodiment.

Referring to FIGS. 9-10 , a part of the interlayer dielectric layer 340 is etched, and at the same time, the first protective layer 310 on the upper part of the N-region fins and the P-region fins is exposed.

Then, a portion of the first protective layer 310 formed on the upper portion of the P-region fins 301 is etched. Similarly, the first protective layer 310 on the upper part of the P-region fins 301 may be completely removed here, or only a part of the first protective layer 310 may be removed. It only needs to satisfy the condition that the thickness of the first protective layer 310 on the upper part of the P-region fins 301 is smaller than the thickness of the first protective layer 310 on the upper part of the N-region fins 302 after the etching in this step.

Similarly, the division standard of the upper part of the fin part and the lower part of the fin part in the embodiment of the present invention is the same as that of the second embodiment, which is not repeated here.

The subsequent process steps are the same as those in the second embodiment, and are not repeated here.

Correspondingly, an embodiment of the present invention further provides a semiconductor device, and the structure and positional relationship thereof may refer to the second embodiment, which will not be repeated here.

So far, the present invention has been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concept of the present invention. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

While some specific embodiments of the present invention have been described in detail by way of example, those skilled in the art will appreciate that the above examples are provided for illustration only and not for the purpose of limiting the scope of the invention. Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the invention is defined by the appended claims.

Claims (33)

1. A method of forming a semiconductor device, comprising:

Providing a semiconductor substrate and a fin part, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, the fin part comprises a P area fin part and an N area fin part, and the P area fin part and the N area fin part are correspondingly formed above the PMOS area and the NMOS area respectively;

forming a first protective layer covering the surface of the fin part;

forming an interlayer dielectric layer between the adjacent fin parts;

removing part of the interlayer dielectric layer and part of the first protective layer to expose the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part;

the process step of exposing the side wall of the upper part of the P-area fin part and the side wall of the upper part of the N-area fin part comprises the following steps of:

etching part of the interlayer dielectric layer to expose the first protective layer formed on the upper part of the P-region fin part;

etching the first protection layer exposed at the upper part of the P-region fin part;

etching a part of the interlayer dielectric layer formed in the NMOS region to expose the first protective layer formed on the upper part of the N region fin part; and

and etching to remove the first protective layer exposed in the NMOS region, and etching the remaining first protective layer on the upper part of the P region fin part and part of the P region fin part, so that the width dimension of the upper part of the P region fin part on the exposed side wall is smaller than the width dimension of the upper part of the N region fin part on the exposed side wall.

2. The method as claimed in claim 1, wherein a width dimension of an upper portion of the P-region fin is smaller than a width dimension of a lower portion of the P-region fin after exposing sidewalls of the upper portion of the P-region fin and sidewalls of an upper portion of the N-region fin.

3. The method of claim 1, further comprising, after forming the first protective layer and before forming the interlevel dielectric layer:

forming a sacrificial layer between the adjacent fin parts;

removing a portion of the sacrificial layer to expose a portion of the first protection layer formed in the PMOS region;

removing the first protection layer exposed in the PMOS area to expose part of the P area fin part;

removing the remaining sacrificial layer to expose the remaining first protective layer; and

and forming a second protective layer on the surface of the first protective layer and the surface of the exposed P-region fin part, wherein the protective layer comprises the first protective layer and the second protective layer.

4. The method of claim 3, wherein the step of exposing the portion of the sidewall of the P-region fin and the portion of the sidewall of the N-region fin comprises:

Removing part of the interlayer dielectric layer to expose part of the second protective layer;

etching and removing the exposed second protective layer to expose the P-region fin portion and the first protective layer on the N-region fin portion; and

and etching and removing the first protective layer formed on the N-region fin portion and the exposed P-region fin portion.

5. The method according to claim 3, wherein a material of the protective layer comprises SiN_x、SiO₂Or one or more combinations of alpha-Si.

6. The semiconductor of claim 3A method of forming a bulk device, wherein the thickness dimension of the first protective layer or the second protective layer is in the range of

7. The method as claimed in claim 3, wherein after the interlayer dielectric layer is formed, a thickness of the protective layer on the upper surface of the P-region fin portion is smaller than a thickness of the protective layer on the upper surface of the N-region fin portion.

8. The method of claim 7, wherein after the inter-layer dielectric layer is formed, a thickness of the protective layer on the upper surface of the P-region fin is smaller than a thickness of the protective layer on the lower surface of the P-region fin, and the thickness of the protective layer on the lower surface of the P-region fin is equal to the thickness of the protective layer on the lower surface of the N-region fin.

9. The method of claim 1, wherein the process of forming the interlevel dielectric layer comprises a fluid chemical vapor deposition process.

10. The method as claimed in claim 9, further comprising performing an annealing process on the interlayer dielectric layer after the interlayer dielectric layer is formed.

11. The method of claim 10, wherein the annealing process comprises: firstly, carrying out water vapor annealing process treatment, and then carrying out rapid thermal annealing process treatment.

12. The method of claim 11, wherein the process parameters of the water vapor annealing process comprise: the annealing temperature range is 550-750 ℃, the annealing time range is 30-200 min, and the technological parameters of the rapid thermal annealing process comprise: the annealing temperature range is 950 ℃ to 1050 ℃, and the annealing time range is 15min to 100 min.

13. The method of claim 1, wherein the N-region fin has a width dimension of/, at exposed sidewalls₂The width dimension of the P region fin part at the exposed side wall is l ₁And then 0.7 is not more than l₁:l₂≤0.9。

14. The method of claim 13, wherein 1nm ≦ l₂-l₁≤2.5nm。

15. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate and a fin part, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, the fin part comprises a P area fin part and an N area fin part, and the P area fin part and the N area fin part are respectively and correspondingly formed above the PMOS area and the NMOS area;

forming a first protective layer covering the surface of the fin portion;

forming an interlayer dielectric layer between the adjacent fin parts;

removing part of the interlayer dielectric layer and part of the first protective layer to expose the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part;

the process step of exposing the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part comprises the following steps:

etching part of the interlayer dielectric layer to expose the upper parts of the N-region fin parts and the P-region fin parts;

etching a part of the first protective layer formed on the upper part of the P-region fin part; and

and etching to remove the first protective layer formed on the upper part of the N-region fin part, the first protective layer left on the upper part of the P-region fin part and part of the P-region fin part, so that the width dimension of the upper part of the P-region fin part at the exposed side wall is smaller than the width dimension of the upper part of the N-region fin part at the exposed side wall.

16. The method of claim 15, wherein a width dimension of an upper portion of the P-region fin is less than a width dimension of a lower portion of the P-region fin after exposing sidewalls of the upper portion of the P-region fin and sidewalls of the upper portion of the N-region fin.

17. The method as claimed in claim 15, further comprising, after forming the first passivation layer and before forming the interlayer dielectric layer:

forming a sacrificial layer between the adjacent fin parts;

removing a portion of the sacrificial layer to expose a portion of the first protection layer formed in the PMOS region;

removing the first protection layer exposed in the PMOS area to expose part of the P area fin part;

removing the remaining sacrificial layer to expose the remaining first protective layer; and

and forming a second protective layer on the surface of the first protective layer and the surface of the exposed P-region fin part, wherein the protective layer comprises the first protective layer and the second protective layer.

18. The method of claim 17, wherein the step of exposing the sidewalls of the P-region fins and the sidewalls of the N-region fins comprises:

Removing part of the interlayer dielectric layer to expose part of the second protective layer;

etching and removing the exposed second protective layer to expose the P-region fin portion and the first protective layer on the N-region fin portion; and

and etching to remove the exposed first protective layer formed on the N-region fin part and the exposed P-region fin part.

19. According to the rightThe method of forming a semiconductor device according to claim 17, wherein a material of the protective layer includes SiN_x、SiO₂Or one or more combinations of alpha-Si.

20. The method for forming a semiconductor device according to claim 17, wherein a thickness of the first protective layer or the second protective layer is in a range of

21. The method as claimed in claim 17, wherein after the formation of the interlayer dielectric layer, a thickness of the protection layer on the upper surface of the P-region fin portion is smaller than a thickness of the protection layer on the upper surface of the N-region fin portion.

22. The method of claim 21, wherein after the inter-layer dielectric layer is formed, a thickness of the protective layer on the upper surface of the P-region fin is smaller than a thickness of the protective layer on the lower surface of the P-region fin, and the thickness of the protective layer on the lower surface of the P-region fin is equal to the thickness of the protective layer on the lower surface of the N-region fin.

23. The method of claim 15, wherein the process of forming the interlevel dielectric layer comprises a fluid chemical vapor deposition process.

24. The method as claimed in claim 23, further comprising performing an annealing process on the interlayer dielectric layer after the interlayer dielectric layer is formed.

25. The method of claim 24, wherein the annealing process comprises: firstly, carrying out water vapor annealing process treatment, and then carrying out rapid thermal annealing process treatment.

26. The method of forming a semiconductor device according to claim 25, wherein the process parameters of the water vapor annealing process comprise: the annealing temperature range is 550-750 ℃, the annealing time range is 30-200 min, and the technological parameters of the rapid thermal annealing process comprise: the annealing temperature range is 950 ℃ to 1050 ℃, and the annealing time range is 15min to 100 min.

27. The method of claim 15, wherein the N-region fin has a width dimension of/, at exposed sidewalls₂The width of the P region fin portion at the exposed side wall is l ₁And then 0.7 is not more than l₁:l₂≤0.9。

28. The method of claim 27, wherein 1nm ≦ l₂-l₁≤2.5nm。

29. A semiconductor device formed by the method for forming a semiconductor device according to any one of claims 1 to 28, the semiconductor device comprising:

the semiconductor substrate comprises a PMOS (P-channel metal oxide semiconductor) region and an NMOS (N-channel metal oxide semiconductor) region, the fin part comprises a P region fin part and an N region fin part, the P region fin part and the N region fin part are respectively and correspondingly arranged above the PMOS region and the NMOS region, and the width size of the upper part of the P region fin part is smaller than that of the upper part of the N region fin part;

the protective layer is arranged on the surface of the lower part of the fin part; and

and the interlayer dielectric layers are formed between the adjacent fin parts.

30. The semiconductor device of claim 29, wherein a width dimension of an upper portion of the N-region fin is/₂The width dimension of the upper part of the P region fin partIs 1₁And then 0.7 is not more than l₁:l₂≤0.9。

31. The semiconductor device of claim 30, wherein 1nm ≦ l₂-l₁≤2.5nm。

32. The semiconductor device according to claim 29, wherein the protective layer comprises a first protective layer and a second protective layer, the second protective layer being provided between the interlayer dielectric layer and the first protective layer.

33. The semiconductor device of claim 29, wherein a width dimension of an upper portion of the P-region fin is less than a width dimension of a lower portion of the P-region fin.

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