CN110824326A

CN110824326A - MOSFET testing method

Info

Publication number: CN110824326A
Application number: CN201911116747.2A
Authority: CN
Inventors: 陈辉; 包智杰; 张秀晨
Original assignee: Nanjing Hongtai Semiconductor Technology Co Ltd
Current assignee: Nanjing Hongtai Semiconductor Technology Co Ltd
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2020-02-21
Also published as: JP2022031892A; JP7042542B2; JP6996786B2; JP2021081427A

Abstract

The invention provides a test scheme of a MOSFET, which comprises the following steps: the peripheral wiring of the base electrode, the collector electrode and the emitter electrode connected to the Matrix box is unchanged, and the source required by each pin is adjusted through a Matrix item; adjusting a Matrix channel, and normally testing functions between the first grid and the first source electrode and between the second grid and the second source electrode; the invention sets the first source electrode as zero potential, takes the second source electrode as the first drain electrode, sets electrical parameter conditions and tests functional parameters of the chip to obtain results, and takes a certain part of source electrode pins of the MOSFET as the other part of drain electrode pins, thereby avoiding the situation that the common double MOSFET chip test scheme can not be applied to the series of chips.

Description

MOSFET testing method

Technical Field

The invention belongs to the technical field of integrated circuit semiconductor discrete device testing, and particularly relates to a MOSFET testing method.

Background

In the current market, a MOSFET is a very common chip, including a single MOSFET, a dual MOSFET, etc., and the packaging forms thereof are also various, the common dual MOSFET seals a drain pin, a gate pin, and a source pin for performing related parameter tests, with the gradual development of the technology, some chip suppliers improve the internal structure of the dual MOSFET to not seal the drain pin of the chip, and change some test items and specifications from the viewpoint of saving cost and improving performance, so that the chip can also achieve similar functions, at this time, the test scheme of the conventional MOSFET cannot be normally applied to such a chip, the existing common dual MOSFET discrete device test scheme is only to call the drain pin, the gate pin, and the source pin of the corresponding MOSFET according to the test specifications respectively, and perform a function test by adding voltage and current parameters, but cannot be applied to a MOSFET whose drain pin is internally short-circuited and is not led out, the principle is complex, problems are not easy to be checked, and the MOSFET testing method has more testing items and poorer chip connectivity, so the principle is simple and convenient to be checked, the testing items are fewer, and the chip connectivity is good, thereby meeting urgent needs.

Disclosure of Invention

The invention provides a MOSFET (metal oxide semiconductor field effect transistor) testing method, which aims to solve the problems that the existing testing method is complex in principle, difficult to troubleshoot problems, more in testing items, poor in chip connectivity and incapable of being applied to the condition of short circuit inside a drain electrode pin, and comprises the following steps:

the peripheral wiring of the base electrode, the collector electrode and the emitter electrode connected to the Matrix box is unchanged, and the source required by each pin is adjusted through a Matrix item;

adjusting a Matrix channel, and normally testing functions between the first grid and the first source electrode and between the second grid and the second source electrode;

and setting the first source electrode as zero potential, taking the second source electrode as a first drain electrode, setting electrical parameter conditions, and performing functional parameter test on the chip by using a test bench to obtain a result.

The Matrix box is used for debugging chip function parameter tests on Matrix program items.

The pins of the MOSFET comprise a grid electrode, a drain electrode and a source electrode.

Wherein the gate and the source have specific electrical parameter conditions during testing.

The pins of the tester comprise a base electrode, a collector electrode and an emitter electrode.

The peripheral wiring means that the grid electrode corresponds to the base electrode, the drain electrode corresponds to the collector electrode, and the source electrode corresponds to the emitter electrode.

The measuring range of the method comprises the measurement of double MOSFET chips with unsealed drain pins and normal MOSFET chips.

Wherein, the peripheral wiring is unchanged, which means that the peripheral wiring of the 3-to-8 channel of the electrode of the tester connected to the matrix box is unchanged.

Setting the first source to zero potential means setting the first source to a collector channel and turning on a grounding relay.

Wherein, the functional parameter test uses BNC line to connect between the test bench and the matrix box for testing.

The invention takes a certain part of the source electrode pins of the MOSFET as the drain electrode pins of the other part, thereby avoiding the situation that the common double MOSFET chip test scheme can not be applied, the drain electrode pins are in short circuit in the chip and are not led out of the chip, and achieving the purposes of testing the products, reducing the test time and improving the test efficiency.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic flow structure diagram of a MOSFET testing method according to the present invention.

FIG. 2 is a schematic diagram of the principle structure of a MOSFET testing method of the present invention.

Fig. 3 is a comparison of test times for the present invention versus a conventional dual MOSFET, as well as a conventional semiconductor tester.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

Referring to fig. 1 and fig. 2, the present invention provides a technical solution:

s101, the peripheral wiring of a base electrode, a collector electrode and an emitter electrode connected to the Matrix box is unchanged, and a source required by each pin is adjusted through a Matrix item;

The gate, and source electrodes have specific electrical parameter conditions at the time of testing.

The peripheral wiring is unchanged, namely the peripheral wiring of the 3-to-8 channel of the electrode connected to the matrix box of the tester is unchanged.

The method comprises the step of measuring a double MOSFET chip with an unsealed drain pin and a normal MOSFET chip.

In the embodiment, the base of the tester corresponds to the gate of the MOSFET, the collector of the tester corresponds to the drain of the MOSFET, the emitter of the tester corresponds to the source of the MOSFET, and peripheral wiring is performed according to the corresponding relationship, and meanwhile, because the definition of pins corresponding to different test items is different, the source required by each pin is adjusted by using a Matrix item in software;

s102, adjusting a Matrix channel, and normally testing functions between a first grid and a first source electrode and between a second grid and a second source electrode;

the Matrix box is used for debugging the chip function parameter test of the Matrix program item.

In this embodiment, the gate pin and the source pin of the corresponding MOSFET are respectively used to call the corresponding test program according to the test specification, and the voltage and current parameters are added to perform the functional test, so as to obtain the test result.

S103, setting the first source electrode as a zero potential, using the second source electrode as a first drain electrode, setting an electrical parameter condition, and performing a functional parameter test on the chip to obtain a result.

The functional parameter test refers to the test by using BNC lines to connect between the test board and the matrix box.

Referring to fig. 3, in the present embodiment, a certain portion of source pins of the MOSFET are used as another portion of drain pins, and voltage and current parameters are applied to perform a test, so that test items are reduced to a certain extent, and the connectivity of the chip is increased, which is no longer a separate and independent test of the conventional MOSFET.

The invention provides a test scheme for a double MOSFET with a drain pin not sealed, and a certain part of source pins of the MOSFET are used as the drain pins of the other part, so that the situation that the common double MOSFET chip test scheme cannot be applied to the series of chips is avoided.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A MOSFET testing method is characterized by comprising the following steps:

2. A MOSFET test method as claimed in claim 1, characterized in that the Matrix box is used for debugging the chip functional parameter test on Matrix program items.

3. The method of claim 1, wherein the pins of the MOSFET include gate, drain, and source.

4. A MOSFET test method as claimed in claim 1 in which the gate, and source are tested for specific electrical parameter conditions.

5. The MOSFET test method of claim 1, wherein the pins of the tester comprise a base, a collector, and an emitter.

6. A MOSFET testing method as claimed in any one of claims 3 to 5, wherein said peripheral wiring is such that said gate corresponds to said base, said drain corresponds to said collector and said source corresponds to said emitter.

7. The method of claim 1, wherein the method measures ranges including measuring double MOSFET chips with unsealed drain leads and normal MOSFET chips.

8. The MOSFET testing method of claim 1, wherein the peripheral connection is unchanged, which means that the electrodes of the tester are connected to the 3-to-8-channel peripheral connection of the matrix box.

9. The MOSFET testing method of claim 1, wherein setting the first source to zero potential means setting the first source to collector channel and turning on a grounding relay.

10. The method of claim 1, wherein the functional parameter testing is performed using BNC wires connected between the test station and the matrix box.