JPH11211786A - Thermal resistance measuring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for measuring thermal resistance of any kind of semiconductor element extremely accurately through simple circuitry. SOLUTION: The method for measuring thermal resistance comprises 8 first step for feeding a microcurrent to a semiconductor element 108 and measuring the temperature characteristics of forward voltage drop across the element, a second step for feeding the micro current and a test current sufficiently larger than the micro current to the element and measuring the variation characteristics of forward voltage drop across the element, a third step for feeding the micro current and the test current to a dummy element 110 having inductance component substantially equivalent to that of the element and measuring the voltage characteristics across the dummy element, a fourth step for correcting the measurement error of the second step based on the results of the third step, and fifth step for determining the thermal resistance of the element based on the measurements of steps 1 and 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for measuring the thermal resistance of a semiconductor device.

[0002]

2. Description of the Related Art FIGS. 5 and 6 show Japanese Patent Publication No. 6-75091.
FIG. 1 is a circuit diagram for explaining a conventional method for measuring the thermal resistance of a MOS-type FET described in Japanese Unexamined Patent Application Publication No. H11-157,086. In this conventional method, there is an internal reverse diode (a diode whose forward direction is opposite to the normal load current direction) formed by the PN junction inside the FET, and the forward voltage drop of this internal reverse diode is present. However, the thermal resistance is measured by utilizing the fact that it changes uniquely according to the channel temperature of the FET. In FIG. 5, first, a very small current Id, which does not increase the channel temperature of the calibration FET 2 placed in the thermostat at the temperature T1, is adjusted from the variable resistor 4 to flow from the source to the drain. The drain voltage Vsd1 is measured. Next, the temperature of the constant temperature bath is changed to T2, and in this state, the variable resistor 4 is adjusted so that the same minute current Id flows through the FET 2 as before, and the source-drain voltage Vsd2 at this time is measured. As a result, the following equation 1
Holds. Here, the symbol “*” represents multiplication, and “/”
Represents division.

ΔVsd = Kd * (ΔT) Here, ΔVsd = Vsd2−Vsd1 ΔT = T2−T1 From this equation 1, the following equation 2 is obtained for the coefficient Kd.

1 / Kd = ΔT / ΔVsd

[0003] Next, in the circuit of FIG.
This is the MOS FET under test whose thermal resistance is to be measured.
The FET 6 is an element having the same structure as the FET 2 in FIG. Here, the terminal D is grounded, the terminal G is connected to the terminal S, and the terminal S is connected by the switches 10, 11 and 12.
Is connected to the variable resistor 4. Then, the variable resistor 4 is adjusted so that a current equal to the minute current Id in FIG. 5 flows from the source to the drain, and the source-drain voltage Vsd3 at that time is measured. Next, switch 1
0, 11 and 12, the terminal D is connected to the voltage source 8, the terminal G is connected to the gate driver 13, and the terminal S
Are respectively connected to the current sources 9. As a result, the current I from the voltage source 8 to the drain of the FET under test 6
Flows, power P is consumed by the FET 6, and the FE under test
The channel temperature of T6 increases. At this time, switch 1
Switch 0, 11 and 12 back to their original state,
6, the source-drain voltage Vsd4 of the FET under test 6 is quickly measured without causing the channel temperature of the FET under test 6 to drop under the condition that the same minute current Id as in the above case flows. As a result, the channel temperature rise value Δ
T is obtained by the following equation (3).

## EQU3 ## ΔT = (Vsd4−Vsd3) / Kd The rise value ΔT of the channel temperature and the power consumption P of the FET 6
From Equation (4), the thermal resistance Rth is obtained.

Rth = ΔT / P

According to the above procedure, the MOS FET
(Hereinafter, referred to as a conventional first method) utilizes the temperature dependence of the forward voltage drop of a reverse diode formed inside a MOS FET. As a result, as shown in FIG. 7, when trying to measure the thermal resistance of a semiconductor device in which a MOS FET and a transistor are combined, a reverse diode formed between the drain and source of the FET and the collector and base of the transistor are measured. Since the minute current Id is shunted to the reverse diode formed between them and the shunt ratio differs between these two diodes,
There was a problem that the thermal resistance could not be measured accurately. Furthermore, IGBT (Insulated Gate Bipolar Trans
When trying to measure the thermal resistance of a semiconductor element called istor), the structure is such that a p + semiconductor region is provided in a MOS FET. Reverse bias P composed of n-region
As a result, an N-junction is formed, and the minute current Id is blocked, so that there is a problem that the measurement of the thermal resistance becomes impossible.

As a method for solving the above-mentioned disadvantages, for example, there is a method disclosed in Japanese Patent Publication No. 6-75091 (this is conventionally referred to as a second method). 8 and 9 show a circuit according to the second conventional method. In FIG.
The calibration MOS type FET 5 is first placed in a constant temperature bath at a temperature T1 and the power supply 25 is adjusted so that the measured current Ig of a minute known value such that the channel temperature of the FET 5 does not rise.
Flow from the drain to the source.
The source-to-source voltage Vsg1 is measured. Next, the temperature of the constant temperature bath is changed to T2, and in this state, the power supply 25 is adjusted so that the same minute measurement current Ig flows between the drain and the source, and the gate-source voltage Vsg2 at this time is measured. I do. As a result, the following equation is obtained.

ΔVsg = Kg * (ΔT) where ΔVsg = Vsg2−Vsg1 ΔT = T2−T1

1 / Kg = ΔT / ΔVsg

Next, referring to FIG. 9, switches 26 and 2
7, the source terminal S of the FET under test 7 is connected to the fixed resistor 24, the gate terminal G is connected to the power supply 25, and the power supply 25 is connected so that the same minute current Ig flows from the drain to the source of the FET 7 as before. The voltage is adjusted, and the gate-source voltage Vsg3 at this time is measured. Next, the switches 26 and 27 connect the source terminal S to the current source 9 and the gate terminal G to the gate driver 13.
The gate is biased by the gate driver 13,
The test current I determined by the current source 9 flows from the drain to the source, the power P is consumed by the FET 7, and the F
The channel temperature of ET7 rises.

Next, the switches 26 and 27 are returned to the original positions,
Again, the power supply 25 is adjusted so that the minute current Ig flows from the drain to the source, and the drain-source voltage Vsg4 is measured while the channel temperature of the FET 7 does not decrease. At this time, the increase value ΔT of the channel temperature of the FET is obtained by the following equation (7).

ΔT = (1 / Kg) * (Vsg4−Vsg3) As a result, the thermal resistance Rth of the FET 7 is expressed by the following equation (8).

Rth = ΔT / P

In the second conventional method, the temperature dependency of the voltage between the gate and the source is not used, but the temperature dependency of the forward voltage drop of the internal reverse diode (PN junction) of the MOSFET. The channel temperature rise is measured. Furthermore, since the direction in which the minute current flows to the FET and the direction in which the test current causing the channel temperature rises match, not only a single MOSFET but also a MOSFET and a transistor are combined on the same chip. There is a feature that thermal resistance can be easily measured even for a MOS FET of a semiconductor device.

[0009]

The above-mentioned first conventional method utilizes the temperature dependence of a PN junction (internal reverse diode), so that a diode, a transistor, and a MOS type F are used.
Although thermal resistance such as ET can be measured, it cannot be applied to a combination chip of a MOS FET and a transistor or an IGBT. Further, the precondition of utilizing the fact that the forward voltage drop of the internal reverse diode changes uniquely according to the channel temperature of the FET, which is the measurement principle of the first conventional method, is not exactly correct. That is, as shown in FIG. 10, the internal reverse diode 30 of the FET is formed by a PN junction, and a very small current Id that does not cause a temperature rise from the source S to the drain D via the PN junction. Flows, while the current I with a temperature rise that subsequently flows from the drain D to the source S flows through the conductive channel caused by the bias of the gate. In other words, the region where the current that causes the temperature rise of the FET originally flows is not exactly the same as the region of the PN junction where the minute current that does not cause the temperature rise flows, and the forward voltage drop of the internal reverse diode is measured. However, this does not mean that the heating section was actually measured by the actual load current. Therefore, there is also a problem that the measurement accuracy of the thermal resistance is strictly inferior.

[0010] On the other hand, the second conventional method uses the gate of the FET.
Since the temperature dependency between sources is used, FET, FET
It is possible to measure the thermal resistance of a combination chip of a transistor and a transistor, an IGBT or the like, but cannot measure the thermal resistance of a diode or a transistor.

Further, in both the first method and the second method in the related art, there is a procedure in which, after a test current is applied and the channel temperature rises, measurement is performed after switching to a minute measurement current. A time delay inevitably occurs from the rise to the measurement, and a decrease in the channel temperature within the delay time makes it difficult to accurately measure the thermal resistance. In addition, a plurality of switches are required for switching the connection between the gate and the source, and the circuit configuration is complicated.

In a MOS FET, IGBT or the like,
Since a large test current is applied, the contact resistance of a switch and the like, the wiring resistance and the like cannot be ignored in many cases. However, the correction of these errors has not been considered in the conventional method.
Further, at the time of switching the current value, a spike-like voltage change occurs due to the remarkable influence of the voltage change L * (di / dt) due to the rapid change current flowing in the inductive reactance component (so-called L component). However, this was not considered at all.

[0013] Further, although capacitances exist between the gate and the source and between the gate and the drain of the FET, the influence of these capacitances has not been considered in the past. That is, for example, in FIG. 9, when the switch 27 is switched from the gate driver 13 to the power supply 25 and the switch 26 is switched from the current source 9 to the resistor 24, the operation state of the FET 7 is switched from the common source to the common drain. As a result, the voltage between the drain and the source changes remarkably abruptly. However, such a transient voltage change has not been considered at all in the conventional method.

An object of the present invention is to provide a novel thermal resistance measuring method which can solve the above-mentioned various problems.

[0015]

According to a first aspect of the present invention, there is provided a method for measuring a thermal resistance of a semiconductor device under test by supplying a small current to the semiconductor device under test in a forward direction and measuring a temperature characteristic of a forward voltage drop of the semiconductor device under test. And supplying a test current having a sufficiently large value compared to the minute current and the minute current to the semiconductor device under test in a forward direction, and a forward voltage of the semiconductor device under test immediately after the supply of the test current is stopped. A second step of measuring a change characteristic of the drop; supplying the small current and the test current to a dummy element having an inductance component substantially equal to that of the semiconductor element under test; and measuring a voltage characteristic between both ends of the dummy element. A third step, a fourth step of correcting an error of the measurement result of the second step from the result of the third step, and a step of correcting the error of the measurement result of the steps 1 and 4. Characterized by comprising the fifth step of obtaining the thermal resistance of the test semiconductor device.

According to the above procedure, it is possible to measure the thermal resistance extremely accurately regardless of the type of the semiconductor under test.

[0017]

FIG. 1 is a block diagram showing an example of a preferred embodiment of the present invention. An output terminal of the small current source 100 that generates the small current Id and an output terminal of the test current source 102 that generates the test current Itest are connected to the node 104. The minute current source 100 is connected between the nodes 104 and 105. The first switch 106 connected to the node 104 and the second switch 112 connected to the node 105 allow the semiconductor device under test (DU)
Either T) 108 or dummy element 110 is selectively connected between nodes 104 and 105. A voltage measurement circuit 114 is connected between nodes 104 and 105. Further, a current measuring circuit 116 is connected between the node 105 and the test current source 102.

The DUT 108 is connected so that the direction from the node 104 to the node 105 is forward. The DUT 108 is a two-terminal element such as a diode in FIG.
A three-terminal element such as an S-type FET or IGBT may be used.
In the case of such a three-terminal element, the control terminal of the DUT 108 (for example, the base terminal of a transistor, FET, I
An appropriate bias circuit 118 is connected to the gate terminal of the GBT, and a small current Id or a test current Itest is connected to the DUT 108.
When applying one or both of them, an appropriate bias is applied. As a result, the thermal resistance measuring method of the present invention can be applied not only to two-terminal devices such as diodes, but also to transistors, FEs, and the like.
It can be easily applied to three-terminal elements such as T and IGBT. The value of the minute current Id is, for example, about several hundred μA to several tens mA, and even when such a current flows, the temperature rise of the DUT 108 can be ignored. However, since the test current Itest is, for example, about several hundreds A, when the test current Itest flows, the temperature of the DUT 108 rapidly rises.

According to the first step of the thermal resistance measuring method of the present invention, the DUT 10 is controlled by the switches 106 and 112.
8 and the minute current Id from the minute current source 100 is
The test current source 102 is turned off at T108. In this state, the periphery of the DUT 108 is surrounded by a thermostat (not shown), and the relationship (temperature characteristic) between the temperature of the DUT 108 and the voltage between both ends is measured. As a result, the relationship between the temperature when the minute current Id is flowing and the forward voltage across the DUT 108 is obtained. An example of a graph of the obtained relationship is shown in FIG.

In the next step 2, the test current source 10
2 is turned on, a pulse-like test current Itest is superimposed on the minute current Id, and is supplied to the DUT 108. After a predetermined time (pulse width period), the forward voltage across the DUT 108 at the time when the test current Itest is turned off is set. Measure Vdut.

In the next step 3, the first switch 1
06 and the second switch 112, the dummy element 110 is connected between the nodes 104 and 105, and both the small current Id from the small current source 110 and the test current Itest from the test current source 102 flow through the dummy element 110. The voltage Idummy between both ends of the dummy element 110 at the time when the test current Itest is turned off is measured. This dummy element 110
The lead wires are formed to have the same thickness, length, material, and shape so as to have the same inductance L as the DUT. Further, the dummy element 110 and the DUT 10
8 is configured to have the same contact resistance and wiring resistance on the floor. Therefore, when a test current Itest which changes rapidly flows through this dummy element, DUT1
08, which has almost the same inductance as L (di / d
It is considered that a spike voltage due to t) occurs in the same manner as in the DUT 108, and an error due to contact resistance and wiring resistance also occurs in the same manner. Therefore, this dummy element 11
By measuring the voltage between both ends of 0, a spike voltage due to the inductance component L and an error due to contact resistance, wiring resistance, and the like can be obtained. That is, D
By subtracting the measurement result of the dummy element 110 from the measurement result of the UT 108, errors due to the inductance component L, contact resistance, wiring resistance, and the like can be corrected. That is, assuming that a true voltage characteristic of the DUT 108 from which errors such as an inductance component, a contact resistance, and a wiring resistance are removed is Vf, the following Expression 9 is established.

Vf = Vdut−Vdummy

FIG. 3 shows an example of a graph of the true voltage characteristic Vf obtained in this manner. From this graph, the transient heat voltage ΔVf can be easily obtained as shown. That is, the time point of the minimum value of the curve of Vf indicates the moment when the test current Itest transitions from the ON state to the OFF state, and the difference between the voltage value at this time point and the voltage value at which the curve of Vf converges to a constant value is shown. Represents a change in the forward voltage caused by a change in the channel temperature of the DUT 108 due to the generation of transient heat.

FIG. 4 shows the DUT 10 based on the above results.
8 is a graph showing a method for obtaining a transient thermal resistance Rth of FIG.
A substantially linear graph falling to the right shows the temperature characteristics of the forward voltage of the DUT 108 when a small current Id flows through the DUT 108, and is measured by the method of Step 1. On this graph, the above-mentioned transient heat voltage ΔV
The temperature change ΔT corresponding to f can be easily obtained. If the average value of the total current of the test current Itest and the small current Id during the pulse width of the test current Itest is Ic, and the average value of the forward voltage of the DUT 108 during this period is Vf, the average consumed by the DUT 108 Power P
Is expressed as Vf * Ic.
The thermal resistance Rth of the DUT 108 is obtained.

Rth = ΔT / P = ΔT / (Vf * Ic) [° C./W]

As described above, the thermal resistance measuring method of the present invention can be applied irrespective of the type of semiconductor device under test, and by superimposing a pulse-like test current on a minute current, the test current can be turned off. The voltage at the moment when it becomes (falling time of the pulse-like test current) can be measured,
It is possible to prevent an error due to a decrease in temperature, and it is possible to correct an error in a spike voltage due to the inductance component L and an error due to a contact resistance, a wiring resistance, and the like using a dummy element. In addition, since a small current and a test current are not selectively switched using a switch as in the related art, a switch is not required and the circuit configuration can be simplified. Furthermore, unlike the conventional method, there is no need to switch between a very small current and a test current with a switch, so that there is a problem of a transient voltage change at the time of switch switching caused by the capacitance existing between the terminals of the device under test. Also does not occur.

The preferred embodiment of the present invention has been described above.
It will be apparent to those skilled in the art that the present invention is not limited to only the above-described embodiments, and that various changes and modifications can be made without departing from the spirit of the present invention. For example, although a switch is employed for switching between the DUT 108 and the dummy element 110 in FIG. 1, the DUT or the dummy element may be replaced with a socket for a large current in consideration of the flow of a large current test current. good. In this case, a manual operation increases, but a switch is unnecessary, and a problem such as an error caused by a contact resistance of the switch can be avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a circuit suitable for applying the present invention.

FIG. 2 is a block diagram showing a connection example of a device under test and a bias circuit suitable for applying to a three-terminal semiconductor device in FIG. 1;

FIG. 3 is an example of a graph showing a forward voltage Vf of a true DUT according to the present invention.

FIG. 4 is a DU showing a procedure for obtaining a thermal resistance in the present invention.
7 is an example of a graph showing temperature characteristics of a forward voltage of T.

FIG. 5 is a circuit diagram showing a part of a circuit for a thermal resistance measuring method according to a first conventional method.

FIG. 6 is a circuit diagram showing another part of the circuit for the conventional first method.

FIG. 7 is a circuit diagram showing an example of a combination circuit of a MOS FET and a transistor.

FIG. 8 is a circuit diagram showing a part of a circuit for a second conventional method.

FIG. 9 is a circuit diagram showing another part of the circuit for the second conventional method.

FIG. 10 is a cross-sectional view illustrating an example of a structure of a MOS-type FET.

[Explanation of symbols]

 Reference Signs List 100 small current source 102 test current source 106 first switch 108 semiconductor device under test (DUT) 110 dummy device 112 second switch

Claims (4)

[Claims] A first step of supplying a small current in a forward direction to a semiconductor device under test and measuring a temperature characteristic of a forward voltage drop of the semiconductor device under test; and a value sufficiently larger than the small current. Supplying the test current and the minute current to the semiconductor device under test in the forward direction,
A second step of measuring the characteristics of the forward voltage drop of the semiconductor device under test immediately after the supply of the test current is stopped, and applying the small current and test to the dummy device having an inductance component substantially equal to that of the semiconductor device under test. A third step of supplying a current and measuring a voltage characteristic between both ends of the dummy element; a fourth step of correcting an error of the measurement result of the second step based on a result of the third step; A fifth step of obtaining the thermal resistance of the semiconductor device under test from the measurement result of step 4. 2. The method according to claim 1, wherein the semiconductor device under test is a diode or other two-terminal device. 3. The semiconductor device under test is a bipolar transistor, MOSFET, IGBT or other three-terminal device. When supplying the small current and the test current to the semiconductor device under test, the semiconductor device under test includes 2. The method according to claim 1, wherein an appropriate bias is supplied to each of the control terminals. 4. A voltage characteristic between both ends of the dummy element obtained in the third step includes L * (di / dt) noise caused by an inductance component and resistance loss caused by a contact resistance, a wiring resistance and the like. 2. The method according to claim 1, further comprising correcting the error of the L * (di / dt) noise and the resistance loss by the fourth step.