CN107369632A - A reliability testing method and system for an unpackaged power device chip - Google Patents

Abstract

The invention provides a reliability test method and system for an unpackaged power device chip. The reliability test method of the unpackaged power device chip comprises the following steps: the method comprises the following steps: (A) after the power device is manufactured, performing a first performance test on the unpackaged power device; (B) after the first test of the unpackaged power device is qualified, forming a reliability test system through conductive connection; (C) applying voltage to the drain electrode of the unpackaged power device under a first temperature condition, keeping for a preset time, and then carrying out a second performance test on the unpackaged power device under a second temperature condition; (D) and judging whether the unpackaged power device passes the reliability test or not according to the test results of the first performance test and the second performance test. The reliability test method and the system for the unpackaged power device chip can shorten the test time and reduce the test cost.

Description

A reliability testing method and system for an unpackaged power device chip

【Technical field】

The invention relates to the technical field of semiconductor chip testing, in particular to a reliability testing method and system for unpackaged power device chips.

【Background technique】

The most important performance of a semiconductor power device is to block high voltage. The device is designed to withstand high voltage on the depletion layer of the PN junction, metal-semiconductor contact interface, and MOS interface; however, as the applied voltage increases, the electric field of the depletion layer Strength also increases, eventually exceeding the material limit with avalanche breakdown.

The drain and source poles of the trench type vertical double diffused field effect transistor (VDMOS) are on both sides of the device, which can make the current flow vertically inside the device, increase the current density, improve the rated current, and the on-resistance per unit area is also improved. Smaller, it is a very versatile power device.

During the application process of the device, mobile ion migration, water vapor infiltration outside the chip, current injection, potential disturbance, and impurity diffusion will all affect the ability of the device to block high voltage, resulting in device failure. Therefore, it is particularly important to test the reliability of the device.

At present, the commonly used reliability testing methods are as follows: After the device is manufactured, performance testing is performed, and after the test is passed, slicing and packaging steps are performed. After the packaging is completed, the device performance test is carried out under specific reliability test conditions. If the device performance before and after the reliability test drops within the allowable range, the reliability of the device is considered to pass the test. The disadvantage of this method is that the reliability test can only be performed after packaging, the packaging process takes a long time, and the reliability test cannot be performed immediately after the device is manufactured. Moreover, the packaging cost is high, which increases the development cost of the device.

In view of this, it is necessary to provide a reliability testing method and system for unpackaged power device chips to solve the above-mentioned problems in the prior art.

【Content of invention】

One object of the present invention is to provide a reliability testing method and system for unpackaged power device chips to solve the above problems.

The method for testing the reliability of an unpackaged power device chip provided by the present invention includes: (A) performing a first performance test on the unpackaged power device after the power device is manufactured; (B) performing a first performance test on the unpackaged power device After the first test is passed, a reliability test system is formed by conductive connection; (C) applying a voltage to the drain of the unpackaged power device under the first temperature condition and keeping it for a predetermined time, then under the second temperature condition Carrying out a second performance test on the unpackaged device; (D) judging whether the unpackaged power device passes the reliability test according to the test results of the first performance test and the second performance test.

As an improvement of the reliability testing method for unpackaged power device chips provided by the present invention, in a preferred embodiment, the unpackaged power device includes an active area and a voltage division area; the active area is located at In the middle area of the unpackaged power device, the voltage division area is arranged around the active area and surrounds the active area; the active area includes a gate, a source, and a drain, wherein the The gate and the source are arranged on the front side of the active area, and the drain is arranged on the back side of the active area.

As an improvement of the method for testing the reliability of unpackaged power device chips provided by the present invention, in a preferred embodiment, the unpackaged power device further includes a scribe line, and the scribe line is provided on the unpackaged Peripheral area of power devices.

As an improvement of the reliability testing method of the unpackaged power device chip provided by the present invention, in a preferred embodiment, the step (B) includes: the gate and source of the unpackaged power device pass through The metal conductive adhesives are short-circuited to each other, and the metal conductive adhesives are connected by the first metal wire; the drain of the unpackaged power device is connected to the second metal wire by the metal conductive adhesive.

As an improvement of the reliability testing method for unpackaged power device chips provided by the present invention, in a preferred embodiment, the step (C) includes: passing the second metal Apply a voltage to the drain of the unpackaged power device by wires and keep it for 500 hours; cool down the unpackaged power device to about 20° C., and then perform a second performance test on the unpackaged power device.

As an improvement of the reliability testing method for unpackaged power device chips provided by the present invention, in a preferred embodiment, the step (D) includes: after the second performance test is completed, the The second performance test parameters obtained from the second performance test are compared and analyzed with the first performance parameters obtained from the first performance test to determine whether the performance degradation of the unpackaged power device before and after the reliability test exceeds the preset scope.

As an improvement of the method for testing the reliability of unpackaged power device chips provided by the present invention, in a preferred embodiment, if the performance degradation of the unpackaged power device does not exceed the preset range, it is considered that the If the unpackaged power device passes the reliability test, otherwise, it is considered that the unpackaged power device fails the reliability test.

The reliability testing system for unpackaged power device chips provided by the present invention is applied to the reliability testing method as described above, and the reliability testing system includes unpackaged power devices, first metal wires and second metal wires, wherein, The unpackaged power device includes an active area and a voltage division area; the voltage division area is arranged around the active area; the active area includes a gate, a source, and a drain, wherein the gate and the source are arranged on the front of the active region, and the drain is arranged on the back of the active region; the gate and the source are short-circuited with each other through metal conductive glue, and the first metal wire connected to the source and gate through the metal conductive glue; the second metal wire is connected to the drain through the metal conductive glue.

As an improvement of the method for testing the reliability of unpackaged power device chips provided by the present invention, in a preferred embodiment, the first metal wire is used as the gate-source connection wire of the unpackaged power device, and the The second metal wire serves as a drain connection wire of the unpackaged power device.

As an improvement of the reliability testing method for unpackaged power device chips provided by the present invention, in a preferred embodiment, the reliability connection system includes multiple unpackaged power devices at the same time, and the same column or row Unpackaged power devices can be connected to the same gate-source connection line through metal conductive glue.

Compared with the prior art, the reliability testing method of the unpackaged power device chip provided by the present invention forms a reliability testing system through a special conductive connection design when the power device chip is in an unpackaged state and performs corresponding reliability testing , so that the test time can be shortened and the test cost can be reduced.

【Description of drawings】

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort, wherein:

Fig. 1 is a schematic flow chart of an embodiment of a reliability testing method for an unpackaged power device chip provided by the present invention;

2 is a schematic plan view of an unpackaged power device chip;

Fig. 3 is a schematic cross-sectional structure diagram of the unpackaged power device chip shown in Fig. 2;

FIG. 4 is a schematic structural diagram of an embodiment of a reliability testing system for unpackaged power device chips provided by the present invention.

【detailed description】

The following will clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In order to solve the problem that the power device chip in the prior art needs to be packaged before the reliability test can be performed, the present invention provides a reliability test method for an unpackaged power device chip, which is mainly performed when the power device chip is in an unpackaged state A reliability test system is formed through a special conductive connection design and corresponding reliability tests are performed, thereby shortening test time and reducing test costs.

Please refer to FIG. 1 , which is a flowchart of an embodiment of a reliability testing method for an unpackaged power device chip provided by the present invention. The reliability testing method of the unpackaged power device chip can be applied to the reliability test of the power device chip, such as trench type vertical double diffused field effect transistor (VDMOS). Specifically, the reliability testing method of the unpackaged power device chip mainly includes the following steps:

Step S1, after the power device is manufactured, perform a first performance test on the unpackaged power device;

Specifically, please refer to FIG. 2 and FIG. 3 , which are respectively a schematic plan view of the unpackaged power device after fabrication. The unpackaged power device includes an active area, a voltage dividing area and a scribe lane; the active area is located in the middle area of the unpackaged power device, and the voltage dividing area is arranged around the active area and surrounds The active area; the scribing lanes are arranged in the peripheral area of the power device. Wherein, the active region includes a gate, a source and a drain, wherein the gate and the source are arranged on the front side of the active region, and the drain is arranged on the back side of the active region.

In step S1, the first performance test of the unpackaged power device can be performed according to the traditional performance test method, which will not be repeated here; and, after the first performance test of step S1 is completed, the corresponding The first performance test parameters, the first new performance test parameters may be saved for subsequent reliability test analysis.

Step S2, after the unpackaged power device passes the first test, a reliability test system is formed through conductive connection, wherein the gate and source of the unpackaged power device are shorted through metal conductive glue and connected to the first a metal wire, and its drain is connected to a second metal wire through metal conductive glue;

Specifically, after passing the first performance test of the unpackaged power device in step S1, a reliability test system as shown in FIG. 4 is formed on the basis of the unpackaged power device through conductive design.

Specifically, first, the gate and the drain on the front side of the active region are short-circuited to each other through metal conductive glue, and the metal conductive glue can be specifically formed as a strip-shaped conductive strip extending from the source to the gate. glue; then, connect the metal conductive glue through the first metal wire, wherein the first metal wire can be used as the gate-source connection wire of the unpackaged power device; and, connect the second metal wire to the The drain of the active region, wherein the second metal wire can be used as a drain connection wire of the unpackaged power device. Through the above-mentioned conductive connection, a reliability test system as shown in FIG. 4 can be formed.

It should be noted that since the reliability test system is connected after the power device is manufactured, and the power device has not been sliced and packaged at this time, the reliability connection system can also include Multiple unpackaged power devices, and unpackaged power devices in the same column (or row) can be connected to the same gate-source connection line through metal conductive glue.

Step S3, after applying a voltage to the drain of the unpackaged power device through the second metal wire under the first temperature condition and keeping it for a predetermined time, performing a second temperature test on the unpackaged device under the second temperature condition. Performance Testing;

Specifically, in step S3, the first temperature condition may be about 150°C, the second temperature condition may be about 20°C, and the predetermined time may generally be about 500 hours. That is to say, in step S3, firstly, under the condition of 150°C, a voltage is applied to the drain of the unpackaged power device through the second metal wire and kept for about 500 hours; then, the unpackaged The temperature of the power device is lowered to about 20° C., and then a second performance test is performed on the unpackaged power device and second performance test parameters are obtained.

Step S4, judging whether the unpackaged power device passes the reliability test according to the test results of the first performance test and the second performance test.

Specifically, after the second performance test in step S3 is completed, compare and analyze the second performance test parameters with the first performance test parameters obtained in step S1 to determine whether the unpackaged package before and after the reliability test Whether the performance degradation of the power device exceeds the preset range, for example, whether the performance degradation exceeds 5%-10%; if it does not exceed the preset range, it is considered that the unpackaged power device has passed the reliability test; The unpackaged power device fails the reliability test.

Compared with the prior art, the reliability testing method of the unpackaged power device chip provided by the present invention forms a reliability testing system through a special conductive connection design when the power device chip is in an unpackaged state and performs corresponding reliability testing , so that the test time can be shortened and the test cost can be reduced.

What has been described above is only the embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, improvements can be made without departing from the creative concept of the present invention, but these all belong to the present invention. scope of protection.

Claims (10)

1. A reliability testing method for an unpackaged power device chip, characterized in that it comprises: (A) After the power device is manufactured, perform the first performance test on the unpackaged power device; (B) After passing the first test of the unpackaged power device, forming a reliability test system through conductive connection; (C) Applying a voltage to the drain of the unpackaged power device under the first temperature condition and keeping it for a predetermined time, performing a second performance test on the unpackaged device under the second temperature condition; (D) judging whether the unpackaged power device passes the reliability test according to the test results of the first performance test and the second performance test. 2. The reliability testing method of an unpackaged power device chip according to claim 1, wherein the unpackaged power device includes an active area and a voltage division area; In the middle region of the device, the voltage division region is arranged around the active region and surrounds the active region; the active region includes a gate, a source and a drain, wherein the gate and the source The drain is arranged on the front of the active region, and the drain is arranged on the back of the active region. 3. The reliability testing method of an unpackaged power device chip according to claim 1, wherein the unpackaged power device further comprises a dicing lane, and the dicing lane is arranged on a peripheral area of the unpackaged power device . 4. the reliability testing method of unpackaged power device chip according to claim 2, is characterized in that, described step (B) comprises: The gate and the source of the unpackaged power device are short-circuited to each other through a metal conductive glue, and the metal conductive glue is connected to the metal conductive glue with a first metal wire; The drain of the unpackaged power device is connected to the second metal wire through metal conductive glue. 5. the reliability testing method of unpackaged power device chip according to claim 1, is characterized in that, described step (c) comprises: Applying a voltage to the drain of the unpackaged power device through the second metal wire under the condition of 150°C and keeping it for 500 hours; The temperature of the unpackaged power device is lowered to about 20° C., and then a second performance test is performed on the unpackaged power device. 6. the reliability testing method of unpackaged power device chip according to claim 1, is characterized in that, described step (D) comprises: After the second performance test is completed, compare and analyze the second performance test parameters obtained from the second performance test with the first performance parameters obtained from the first performance test to determine the reliability before and after the reliability test. Whether the performance degradation of the unpackaged power device exceeds a preset range. 7. The reliability testing method of an unpackaged power device chip according to claim 6, wherein if the performance degradation of the unpackaged power device does not exceed the preset range, the unpackaged power device is considered to be Pass the reliability test; otherwise, it is considered that the unpackaged power device fails the reliability test. 8. A reliability testing system of an unpackaged power device chip, applied to the reliability testing method as claimed in claim 1, wherein the reliability testing system includes an unpackaged power device, a first metal wire and The second metal wire, wherein the unpackaged power device includes an active area and a voltage division area; the voltage division area is arranged around the active area; the active area includes a gate, a source, and a drain electrode, wherein the gate and source are arranged on the front of the active region, and the drain is arranged on the back of the active region; the gate and the source are short-circuited to each other through metal conductive glue, And the first metal wire is connected to the source and the gate through the metal conductive glue; the second metal wire is connected to the drain through the metal conductive glue. 9. The reliability testing system for unpackaged power device chips according to claim 8, wherein the first metal wire is used as a gate-source connecting wire of the unpackaged power device, and the second metal wire is used as a gate-source connection wire of the unpackaged power device. The drain connection wire of the unpackaged power device. 10. The reliability test system for unpackaged power device chips according to claim 9, wherein the reliability connection system includes a plurality of unpackaged power devices at the same time, and unpackaged power devices in the same column or row It can be connected to the same gate-source connection line through metal conductive glue.