CN105810733A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN105810733A CN105810733A CN201410851443.1A CN201410851443A CN105810733A CN 105810733 A CN105810733 A CN 105810733A CN 201410851443 A CN201410851443 A CN 201410851443A CN 105810733 A CN105810733 A CN 105810733A
- Authority
- CN
- China
- Prior art keywords
- grid
- semiconductor device
- groove
- layer
- conduction type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000000463 material Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 239000012774 insulation material Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device. The semiconductor device comprises a groove arranged at a top portion of an epitaxial layer in a first conductive type, wherein the groove is internally provided with a first grid and a second grid which are relatively independent, the first grid and the second grid are isolated through a grid oxide layer attached to a side wall of the groove and the epitaxial layer, the first grid and the second grid realize insulation through an insulation material filled in the groove, the top portion of the epitaxial layer is doped with a body layer, a first source region in the first conductive type is doped at the top portion of the body layer and is close to the upper portion of one side of the groove, a second source region in the first conductive type is doped at the top portion of the body layer and is close to the upper portion of the opposite another side of the groove, and the body layer is arranged above the bottom portion of the groove. Through the semiconductor device, areas of chips can be reduced.
Description
Technical field
The present invention relates to semiconductor applications, specifically, the invention particularly relates to a kind of novel semiconductor device.
Background technology
Since first transistor of AT&T Labs of U.S. invention comes out, quasiconductor obtains development at full speed, transistor has the ability that by and large a highly automated process can be used to carry out large-scale production, penetrate into the every field of life at present gradually, upper to aerospace field, arriving down medical communication field, a lot of accurate devices all be unable to do without based semiconductor material.
Along with people are more and more higher to the requirement of semiconductor device, die size is particularly important.Die size is more little means that the precise treatment program of device is more high, and more little the also implying that of device size can place more transistor under equal area simultaneously, and then brings more excellent device performance.
With reference to shown in Fig. 1, it illustrates the sectional view of a kind of semiconductor device, epitaxial layer 10 top surface in P type is formed with some N+ type doped regions 11 and some P+ type doped regions 12；Part N+ type doped region 11 is drawn in order to as source electrode (source) electrode 13 by metal or wire, and another part N+ type doped region 11 is drawn in order to as drain electrode (drain) electrode 14 by metal or wire；Between source electrode 13 and drain electrode 14, it is additionally provided with grid 15 simultaneously.Device shown in this figure can share a drain electrode, therefore can be considered two transistors being cascaded, as shown in Figure 2.
But the area that above-mentioned this common planar device takies chip is bigger, and the area of chip can directly influence device performance and cost, therefore how to reduce device area shared in the chips further and endeavoured the direction of research always for those skilled in the art.
Summary of the invention
The invention provides a kind of semiconductor device, it is possible to well reduce chip area, further boost device integrated.In order to realize this technical scheme, the technical solution used in the present invention is:
A kind of semiconductor device, wherein, including:
The epitaxial layer top of the first conduction type is provided with a groove, relatively independent first grid and second grid it is provided with in described groove, described first grid and described second grid are isolated by the grid oxic horizon of attachment and described epitaxial layer on trenched side-wall, and are insulated by the insulant of filling in groove between described first grid and described second grid；
At the top of described epitaxial layer doped with body layer, first source area of described first conduction type is entrained in the top of body layer and near the adjacent upper part of groove side, and the second source area of described first conduction type is entrained in the top of body layer and near the adjacent upper part of the relative opposite side of groove；
Described body layer is positioned at more than described channel bottom.
Above-mentioned semiconductor device, wherein, is additionally provided with the semiconductor layer of the first conduction type, in order to the drain region as described semiconductor device bottom this semiconductor layer bottom described epitaxial layer.
Above-mentioned semiconductor device, wherein, closes on described first source area and described second source class district, and is formed with the diffusion region of the second conduction type at the top of described body layer.
Above-mentioned semiconductor device, wherein, described first conduction type is N-type, and described second conduction type is P type.
Above-mentioned semiconductor device, wherein, the ion doping concentration of described semiconductor layer is more than the ion doping concentration of described epitaxial layer.
Above-mentioned semiconductor device, wherein, the ion doping concentration of described diffusion region is more than the ion doping concentration of described body layer.
Above-mentioned semiconductor device, wherein, described grid oxic horizon material is SiO2。
Above-mentioned semiconductor device, wherein, the material of described first grid and described second grid is polysilicon.
Technique scheme effectively saves chip area, improves device performance simultaneously, and preparation technology is comparatively ripe, it may be achieved property is stronger.
Accompanying drawing explanation
By reading detailed description non-limiting example made with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent upon.The part that labelling instruction identical in whole accompanying drawings is identical.Deliberately it is not drawn to scale accompanying drawing, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1 is the schematic diagram of a kind of planar-type semiconductor device in prior art；
Fig. 2 is the circuit diagram of semiconductor device shown in corresponding diagram 1；
Fig. 3 is for the invention provides a kind of semiconductor device schematic diagram；
Fig. 4 is the circuit diagram of corresponding diagram 3.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, in order to explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions, the present invention can also have other embodiments.
The invention provides a kind of novel semiconductor device design, prior art of comparing can strengthen reduction chip area, and then the elaboration for further boost device provides foundation.
With reference to, shown in Fig. 3, the invention provides a kind of novel semiconductor device, as it can be seen, include:
Epitaxial layer 101 top of the first conduction type is provided with a groove, relatively independent first grid 106 and second grid 107 it is provided with in groove, first grid 106 and second grid 107 are isolated with epitaxial layer 101 by the grid oxic horizon 105 of attachment on trenched side-wall, and are insulated by the interior insulant 110 filled of groove between first grid and second grid；
At the top of epitaxial layer 101 doped with body layer 102, simultaneously body layer 102 preferably ensures to be positioned at more than the bottom of groove.First source area 108 of the first conduction type is entrained in the top of body layer 102 and near the adjacent upper part of groove side, and the second source area 109 of the first conduction type is entrained in the top of body layer 102 and near the adjacent upper part of the relative opposite side of groove.
The present invention one preferred but in unrestriced embodiment, be additionally provided with the semiconductor layer 100 of the first conduction type bottom epitaxial layer 101, bottom this semiconductor layer 100, be used as the drain region of semiconductor device.Wherein, channel bottom preferably and has certain distance between semiconductor layer 100, and then avoids channel resistance excessive thus affecting device performance.
In the present invention, above-mentioned first grid 106 is drawn as grid (gate) G1, first source area 108 is drawn as source electrode (source) S1, and second grid 107 is drawn as grid G 2, the second source area 109 is drawn as source S 2；Grid G 1, source S 1 and grid G 2, source S 2 can drain electrode (drain) D bottom common semiconductor layer 100, can refer to shown in Fig. 4.
The present invention one preferred but in unrestriced embodiment, close on the first source area 108 and the second source class district 109, and be formed with the diffusion region 103 of the second conduction type at the top of body layer 102.
The present invention one preferred but in unrestriced embodiment, above-mentioned grid oxic horizon 105 can be completely covering on channel bottom and sidewall, can also be only arranged between first grid 106, second grid 107 and epitaxial layer 101, namely mean that the insulant 110 filled in groove directly can contact with between epitaxial layer 101, or isolated by grid oxic horizon 105 and epitaxial layer 101.
The present invention one is preferred but in unrestriced embodiment, previously described first conduction type is N-type, and the second conduction type is P type.
The present invention one is preferred but in unrestriced embodiment, the ion doping concentration of semiconductor layer 100 is more preferably greater than the ion doping concentration of epitaxial layer 101.Optionally, semiconductor layer 100 and epitaxial layer 101 are homotype epitaxial layer.
The present invention one is preferred but in unrestriced embodiment, the ion doping concentration of diffusion region 103 is more preferably greater than the ion doping concentration of body layer 102.
The present invention one is preferred but in unrestriced embodiment, above-mentioned grid oxic horizon 105 material can be SiO2。
The present invention one is preferred but in unrestriced embodiment, the material of first grid 106 and second grid 107 is polysilicon (poly silicon).
In sum, owing to present invention employs as above technical scheme, by being provided with two relatively independent gate electrodes in a groove at epitaxial layer top, and source contact area it is respectively formed with in the both sides of this gate electrode, and the drain region bottom common parts, based on this technical scheme, make grid structure area occupied less and electric current flowing can accomplish true vertical, to minimize elementary cell area, in identical footprint can integrated more unit thus reducing conducting resistance Rdson and maintaining electric capacity and remain unchanged, prior art of comparing greatly reduces chip area.The present invention is little to existing structure variation, can be easier to point out according to existing processing procedure, is suitable for promoting producing and applying.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned particular implementation, the equipment and the structure that are not wherein described in detail to the greatest extent are construed as and are practiced with the common mode in this area；Any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all may utilize the method for the disclosure above and technology contents and technical solution of the present invention is made many possible variations and modification, or it being revised as the Equivalent embodiments of equivalent variations, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.
Claims (8)
1. a semiconductor device, it is characterised in that including:
The epitaxial layer top of the first conduction type is provided with a groove, relatively independent first grid and second grid it is provided with in described groove, described first grid and described second grid are isolated by the grid oxic horizon of attachment and described epitaxial layer on trenched side-wall, and are insulated by the insulant of filling in groove between described first grid and described second grid；
At the top of described epitaxial layer doped with body layer, first source area of described first conduction type is entrained in the top of body layer and near the adjacent upper part of groove side, and the second source area of described first conduction type is entrained in the top of body layer and near the adjacent upper part of the relative opposite side of groove；
Described body layer is positioned at more than described channel bottom.
2. semiconductor device as claimed in claim 1, it is characterised in that be additionally provided with the semiconductor layer of the first conduction type bottom described epitaxial layer, as the drain region of described semiconductor device bottom this semiconductor layer.
3. semiconductor device as claimed in claim 1, it is characterised in that close on described first source area and described second source class district, and be formed with the diffusion region of the second conduction type at the top of described body layer.
4. the semiconductor device as described in Claim 1-3 any one, it is characterised in that described first conduction type is N-type, described second conduction type is P type.
5. semiconductor device as claimed in claim 1, it is characterised in that the ion doping concentration of described semiconductor layer is more than the ion doping concentration of described epitaxial layer.
6. semiconductor device as claimed in claim 1, it is characterised in that the ion doping concentration of described diffusion region is more than the ion doping concentration of described body layer.
7. semiconductor device as claimed in claim 1, it is characterised in that described grid oxic horizon material is SiO2。
8. semiconductor device as claimed in claim 1, it is characterised in that the material of described first grid and described second grid is polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410851443.1A CN105810733A (en) | 2014-12-30 | 2014-12-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410851443.1A CN105810733A (en) | 2014-12-30 | 2014-12-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105810733A true CN105810733A (en) | 2016-07-27 |
Family
ID=56420643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410851443.1A Pending CN105810733A (en) | 2014-12-30 | 2014-12-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105810733A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809148A (en) * | 2020-06-12 | 2021-12-17 | 新唐科技股份有限公司 | Power element and method of manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6237965A (en) * | 1985-08-13 | 1987-02-18 | Tdk Corp | Longitudinal semiconductor device and manufacture thereof |
| DE10250175B4 (en) * | 2002-10-28 | 2005-02-17 | Infineon Technologies Ag | power transistor |
| CN102956640A (en) * | 2011-08-22 | 2013-03-06 | 大中积体电路股份有限公司 | Double-conduction semiconductor component and manufacturing method thereof |
-
2014
- 2014-12-30 CN CN201410851443.1A patent/CN105810733A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6237965A (en) * | 1985-08-13 | 1987-02-18 | Tdk Corp | Longitudinal semiconductor device and manufacture thereof |
| DE10250175B4 (en) * | 2002-10-28 | 2005-02-17 | Infineon Technologies Ag | power transistor |
| CN102956640A (en) * | 2011-08-22 | 2013-03-06 | 大中积体电路股份有限公司 | Double-conduction semiconductor component and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809148A (en) * | 2020-06-12 | 2021-12-17 | 新唐科技股份有限公司 | Power element and method of manufacturing the same |
| CN113809148B (en) * | 2020-06-12 | 2023-09-29 | 新唐科技股份有限公司 | Power element and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9070713B2 (en) | Power semiconductor device and methods for fabricating the same | |
| US8999789B2 (en) | Super-junction trench MOSFETs with short terminations | |
| CN108428740B (en) | An IGBT chip with a composite gate structure with a virtual gate | |
| JP2017084998A (en) | Super junction mosfet device and semiconductor chip | |
| US9412810B2 (en) | Super-junction trench MOSFETs with closed cell layout having shielded gate | |
| US20070132016A1 (en) | Trench ld structure | |
| CN110896104B (en) | Multiple Gate Power MOSFET Components | |
| CN105810733A (en) | Semiconductor device | |
| CN108054195A (en) | Semiconductor power device and preparation method thereof | |
| TW201409692A (en) | Semiconductor device and fabricating method thereof | |
| CN107994067B (en) | Semiconductor power device, terminal structure of semiconductor power device and manufacturing method thereof | |
| US11189698B2 (en) | Semiconductor power device | |
| CN105576022B (en) | Semiconductor devices and preparation method thereof with super-junction structure | |
| CN102867848B (en) | Trench type power semiconductor element and manufacturing method thereof | |
| CN203038926U (en) | Semiconductor power device possessing terminal protection structure | |
| KR20100067874A (en) | Mosfet device | |
| KR101790818B1 (en) | Semiconductor device | |
| CN109994549B (en) | Semiconductor Power Devices | |
| US9337328B1 (en) | Super-junction trench MOSFETs with closed cell layout | |
| CN109994470A (en) | A semiconductor power device | |
| CN104810398B (en) | Semiconductor device and method for manufacturing the same | |
| CN102184911A (en) | Miller parasitic capacitance shielding structure of high-power and high-frequency device | |
| TWI467765B (en) | Semiconductor device and fabricating method thereof | |
| WO2025073074A1 (en) | Pillar trench power mosfet and forming method thereof | |
| CN109994468B (en) | Semiconductor super junction power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160727 |