CN110796975B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN110796975B CN110796975B CN201911168213.4A CN201911168213A CN110796975B CN 110796975 B CN110796975 B CN 110796975B CN 201911168213 A CN201911168213 A CN 201911168213A CN 110796975 B CN110796975 B CN 110796975B
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- transistor
- test pad
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a display panel and a display device. According to the invention, at least one test pad is arranged on the flip chip film and the printed circuit board, and the electrical connection with the grid electrode of the transistor is realized through the wiring connected to the golden finger area, so that the GOA circuit of the display panel can be simply, rapidly and accurately tested to output the grid electrode waveform of the transistor in the display panel, the development efficiency is improved, and the reliability of the product is improved.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display panel and a display device.
Background
With the progressive improvement of the design maturity of the liquid crystal panel, the narrow frame and low cost become more and more the main consideration factors of the panel design. The GOA (Gate Driver on Array) design of the panel can meet customer requirements for narrow frame, low cost. The GOA technology directly manufactures the gate scan driving circuit of the thin film transistor on the display substrate, so as to save the scan driving chip, reduce Bonding time and reduce the usage amount of anisotropic conductive film (Anisotropic Conductive Film, abbreviated as ACF). In order to integrate the scan driving on the glass substrate array, the timing controller is required to provide signals such as a frame start signal STV, field shift pulse signals CKV 1-2N (N is greater than or equal to 1), and the levels of the analog ground voltage VSSD and the analog working voltage VDDD are converted into a gate-off voltage VGL and a gate-on voltage VGH by a Level Shifter (Level Shifter). However, the waveforms of the gate electrodes of the transistors of the display panel to be turned on or turned off by the GOA circuit are not simply and quickly measured and obtained, and the performance of the GOA circuit and the performance of the GOA output waveforms in the display panel cannot be quickly judged in the early stage, so that the precious development time is wasted due to errors in the later stage of the project.
In order to eliminate the related risk of the GOA circuit as much as possible, the prior proposal is to test the time sequence of external control signals such as STV, CK and the like which are output to the inside of the display panel (or in the plane for short, hereinafter the same) through a time sequence controller, then simulate the output waveform of the GOA circuit through software, or indirectly test the output waveform of the GOA circuit through laser bridging on an in-plane circuit. The simulation parameters are different from the parameters of the GOA circuit period of the actual panel and the environment parameters, so that the actual GOA circuit output waveform cannot be obtained. By means of laser bridging, laser points are often found by splitting the liquid crystal box under the high-power microscope, so that more manpower is consumed and high-end equipment is needed. The success rate is relatively low, the effect of laser point positions cannot be guaranteed, and large difference of output results can be caused. Above, there are uncontrollable factors, so that accurate data cannot be acquired.
Therefore, how to simply, rapidly and accurately test the waveform of the gate electrode of the transistor in the display panel output by the GOA circuit of the display panel is an important issue in the display technology.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, wherein at least one test pad is arranged on a flip chip film and a printed circuit board, and the electrical connection with a grid electrode of a transistor is realized through a wiring connected to a golden finger area, so that a GOA circuit of the display panel can be simply, quickly and accurately tested to output a grid electrode waveform of the transistor in the display panel, the development efficiency is improved, and the reliability of a product is improved.
According to an aspect of the present invention, there is provided a display panel including: a printed circuit board provided with a first golden finger area; the flip chip film is provided with a second golden finger area and at least one test pad, wherein the at least one test pad of the flip chip film is electrically connected with the second golden finger area; the substrate wire area is provided with at least one wire and a plurality of substrate wires, wherein the at least one wire is electrically connected with the first golden finger area and the second golden finger area; the scanning driving circuit comprises a plurality of scanning lines, and each scanning line is electrically connected with each corresponding substrate wire; and a plurality of cascaded pixel units, wherein the pixel units in the first row comprise at least one transistor, the grid electrode of the at least one transistor is connected to the second golden finger area through the at least one wiring, and the grid electrode of the at least one transistor is electrically connected with at least one test pad of the flip-chip film.
Further, the printed circuit board is provided with a time sequence controller, a level shifter and a power switch, wherein the level shifter is respectively and electrically connected with the time sequence controller and the power switch.
Further, the timing controller is configured to provide a control signal, where the control signal includes a frame start signal and a field shift pulse signal.
Further, the potential shifter is used for converting the levels of the analog ground voltage and the analog working voltage into a gate-off voltage and a gate-on voltage.
Further, the power switch is used for turning on or off the level shifter.
Further, the printed circuit board is provided with at least one test pad, and the at least one test pad of the printed circuit board is electrically connected with the first golden finger area.
Further, at least one test pad of the printed circuit board is electrically connected with the gate of the at least one transistor through the at least one wire connected to the first golden finger region.
Further, the at least one transistor includes a first transistor, a second transistor, and a third transistor.
Further, the first transistor is located at the left side of the first row of the plurality of pixel units, the second transistor is located at the middle of the first row of the plurality of pixel units, and the third transistor is located at the right side of the first row of the plurality of pixel units.
According to another aspect of the present invention, there is provided a display device including any one of the display panels described above.
According to the embodiment of the invention, the at least one test pad is arranged on the flip chip film and the printed circuit board, and the electrical connection with the grid electrode of the transistor is realized through the wiring connected to the golden finger area, so that the GOA circuit of the display panel can be simply, quickly and accurately tested to output the grid electrode waveform of the transistor in the display panel, the development efficiency is improved, and the reliability of the product is improved.
Drawings
The technical solution of the present invention and its advantageous effects will be made apparent by the following detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The terms first, second, third and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the objects so described may be interchanged where appropriate. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
In the detailed description, the drawings and examples set forth below, which illustrate the principles of the present disclosure, are only for the purpose of illustration and are not to be construed as limiting the scope of the present disclosure. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system. Exemplary embodiments will be described in detail, examples of which are illustrated in the accompanying drawings. Further, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings indicate like elements.
The terminology used in the description of the particular embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The use of expressions in the singular encompasses plural forms of expressions unless the context clearly dictates otherwise. In the present description, it should be understood that terms such as "comprising," "having," "including," and "containing" are intended to specify the presence of the stated features, integers, steps, actions, or combinations thereof disclosed in the present description, but are not intended to preclude the presence or addition of one or more other features, integers, steps, actions, or combinations thereof. Like reference numerals in the drawings refer to like parts.
Referring to fig. 1, an embodiment of the present invention provides a display panel, which includes a printed circuit board 10, a first gold finger area 110, a timing controller 110, a level shifter 120, a power switch 130, a first test pad 150, a second test pad 160, a third test pad 170, a flip-chip film 20, a second gold finger area 210, a fourth test pad 220, a fifth test pad 230, a sixth test pad 240, a substrate wire area 30, a substrate wire 310, a first trace 320, a second trace 330, a third trace 340, a scan driving circuit 40, a scan line 410, a pixel unit 50, a first transistor 510, a second transistor 520, and a third transistor 530.
The printed circuit board 10 is provided with a first golden finger area 110 and at least one test pad. The first gold finger area 110 is provided with a plurality of conductive contacts for signal transmission. In the embodiment of the present invention, the at least one test pad of the printed circuit board 10 includes a first test pad 150, a second test pad 160, and a third test pad 170. In other embodiments, however, the number of at least one test pad of the printed circuit board 10 is not limited thereto.
In addition, the printed circuit board 10 is further provided with a timing controller 110, a level shifter 120 and a power switch 130. The level shifter 120 is connected to the timing controller 110 and the power switch 130, respectively. The timing controller 110 is used for providing control signals, wherein the control signals include a frame start signal and a field shift pulse signal, but are not limited thereto. The level shifter 120 is used for converting the levels of the analog ground voltage and the analog operating voltage into a gate-off voltage and a gate-on voltage. The power switch 130 is used to turn the level shifter 120 on or off.
The flip chip film 20 is provided with a second gold finger area 210 and at least one test pad. Wherein at least one test pad of the flip chip film is electrically connected to the second gold finger region 210. In the embodiment of the invention, the at least one test pad includes a fourth test pad 220, a fifth test pad 230 and a sixth test pad 240, and the fourth test pad 220, the fifth test pad 230 and the sixth test pad 240 are electrically connected to the second gold finger area 210. However, in other embodiments, the number of the at least one test pad of the flip chip film 20 is not limited thereto.
The substrate conductive line region 30 is provided with at least one trace and a plurality of substrate conductive lines 310, wherein the at least one trace is electrically connected to the first gold finger region 110 and the second gold finger region 210. In the embodiment of the present invention, the at least one trace includes a first trace 320, a second trace 330 and a third trace 340. In other embodiments, the number of the substrate wire region 30 provided with at least one trace is not limited thereto.
The first trace 320, the second trace 330, and the third trace 340 are electrically connected to the first gold finger area 110 and the second gold finger area 210.
The scan driving circuit 40 includes a plurality of scan lines 410. Each scan line 410 is electrically connected to each corresponding substrate wire. The scan driving circuit 40 is used for driving a plurality of scan lines 410.
A plurality of pixel cells 50 are cascaded, wherein the plurality of pixel cells 50 of the first row include at least one transistor. The gate of the at least one transistor is connected to the second gold finger region 210 through at least one trace. The gate of at least one transistor is electrically connected to at least one test pad of the flip-chip film 20.
In an embodiment of the present invention, the at least one transistor includes a first transistor 510, a second transistor 520, and a third transistor 530. The first transistor 510 is positioned to the left of the first row of the plurality of pixel cells 50, the second transistor 520 is positioned to the middle of the first row of the plurality of pixel cells 50, and the third transistor 530 is positioned to the right of the first row of the plurality of pixel cells. The gates of the first transistor 510, the second transistor 520 and the third transistor 530 are respectively connected to the first gold finger area 110 through the first trace 320, the second trace 330 and the third trace 340, and the gates of the first transistor 510, the second transistor 520 and the third transistor 530 are electrically connected to the first test pad 150, the second test pad 160 and the third test pad 170. Meanwhile, the gates of the first transistor 510, the second transistor 520 and the third transistor 530 are respectively connected to the second gold finger area 210 through the first trace 320, the second trace 330 and the third trace 340, and the gates of the first transistor 510, the second transistor 520 and the third transistor 530 are electrically connected to the fourth test pad 220, the fifth test pad 230 and the sixth test pad 240. When the GOA circuit of the display panel outputs the grid waveforms of the transistors in the display panel, the test pads on the flip chip film 20 or the printed circuit board 10 can be tested by only using the probes of the common oscilloscope, so that the method is very convenient, quick and accurate. It should be noted that, in other embodiments, the number of the at least one transistor is not limited thereto. For example, the at least one transistor includes a fourth transistor located on the left of the first row of the plurality of pixel cells 50, and a fifth transistor located on the right of the first row of the plurality of pixel cells.
According to the embodiment of the invention, the at least one test pad is arranged on the flip chip film and the printed circuit board, and the electrical connection with the grid electrode of the transistor is realized through the wiring connected to the golden finger area, so that the grid electrode waveform of the transistor in the display panel output by the GOA circuit of the display panel can be simply, quickly and accurately tested, the development efficiency is improved, and the reliability of the product is improved.
Referring to fig. 2, another display panel is provided according to the embodiment of the present invention, which is different from the previous embodiment in that the display panel is not provided with test pads on the printed circuit board. The display panel includes a printed circuit board 10, a first gold finger area 110, a timing controller 110, a level shifter 120, a power switch 130, a flip chip film 20, a second gold finger area 210, a first test pad 220, a second test pad 230, a third test pad 240, a substrate wire area 30, a substrate wire 310, a first trace 320, a second trace 330, a third trace 340, a scan driving circuit 40, a scan line 410, a pixel unit 50, a first transistor 510, a second transistor 520, and a third transistor 530.
The printed circuit board 10 is provided with a first gold finger area 110. The first gold finger area 110 is provided with a plurality of conductive contacts for signal transmission.
In addition, the printed circuit board 10 is further provided with a timing controller 110, a level shifter 120 and a power switch 130, wherein the level shifter 120 is respectively connected to the timing controller 110 and the power switch 130. The timing controller 110 is used for providing control signals, wherein the control signals include a frame start signal and a field shift pulse signal, but are not limited thereto. The level shifter 120 is used for converting the levels of the analog ground voltage and the analog operating voltage into a gate-off voltage and a gate-on voltage. The power switch 130 is used to turn the level shifter 120 on or off.
The flip chip film 20 is provided with a second gold finger area 210 and at least one test pad, wherein the at least one test pad of the flip chip film is electrically connected with the second gold finger area 210. In the embodiment of the invention, the at least one test pad includes a first test pad 220, a second test pad 230 and a third test pad 240, and the first test pad 220, the second test pad 230 and the third test pad 240 are electrically connected to the second golden finger region 210.
The substrate conductive line region 30 is provided with at least one trace and a plurality of substrate conductive lines 310, wherein the at least one trace is electrically connected to the second golden finger region 210. In the embodiment of the invention, the at least one trace includes a first trace 320, a second trace 330 and a third trace 340, wherein the first trace 320, the second trace 330 and the third trace 340 are electrically connected to the second golden finger region 210.
The scan driving circuit 40 includes a plurality of scan lines 410, and each scan line 410 is electrically connected to a corresponding substrate wire. The scan driving circuit 40 is used for driving a plurality of scan lines 410.
The plurality of pixel units 50 in the cascade connection, wherein the plurality of pixel units 50 in the first row include at least one transistor, a gate of the at least one transistor is connected to the second golden finger region 210 through at least one trace, and a gate of the at least one transistor is electrically connected to at least one test pad of the flip-chip film 20.
In an embodiment of the present invention, the at least one transistor includes a first transistor 510, a second transistor 520, and a third transistor 530. The first transistor 510 is positioned to the left of the first row of the plurality of pixel cells 50, the second transistor 520 is positioned to the middle of the first row of the plurality of pixel cells 50, and the third transistor 530 is positioned to the right of the first row of the plurality of pixel cells. The gates of the first transistor 510, the second transistor 520 and the third transistor 530 are respectively connected to the second gold finger area 210 through the first trace 320, the second trace 330 and the third trace 340, and the gates of the first transistor 510, the second transistor 520 and the third transistor 530 are electrically connected to the first test pad 220, the second test pad 230 and the third test pad 240. When the GOA circuit of the display panel is tested and outputs the waveform of the grid electrode of the transistor in the display panel, the probe of the common oscilloscope is only required to test the test pad on the flip chip film 20 or the printed circuit board 10, so that the method is very convenient, quick and accurate.
According to the embodiment of the invention, the at least one test pad is arranged on the flip chip film and the printed circuit board, and the electrical connection with the grid electrode of the transistor is realized through the wiring connected to the golden finger area, so that the GOA circuit of the display panel can be simply, quickly and accurately tested to output the grid electrode waveform of the transistor in the display panel, the development efficiency is improved, and the reliability of the product is improved.
Referring to fig. 3, an embodiment of the present invention provides a display device 2 including the display panel 1 as described above. The display device 2 may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The foregoing has described in detail a display panel and a display device according to embodiments of the present invention, and specific examples have been applied to illustrate the principles and embodiments of the present invention, where the foregoing examples are provided to assist in understanding the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.
Claims (6)
1. A display panel, comprising:
a printed circuit board provided with a first golden finger area;
the flip chip film is provided with a second golden finger area and at least one test pad, wherein the at least one test pad of the flip chip film is electrically connected with the second golden finger area;
the substrate wire area is provided with at least one wire and a plurality of substrate wires, wherein the at least one wire is electrically connected with the first golden finger area and the second golden finger area;
the scanning driving circuit comprises a plurality of scanning lines, and each scanning line is electrically connected with each corresponding substrate wire; and
the plurality of GOA units in the first row comprise at least one transistor, the grid electrode of the at least one transistor is connected to the second golden finger area through the at least one wiring, and the grid electrode of the at least one transistor is electrically connected with at least one test pad of the flip-chip film;
the printed circuit board is provided with at least one test pad, and the at least one test pad of the printed circuit board is electrically connected with the first golden finger area; at least one test pad of the printed circuit board is electrically connected with the grid electrode of the at least one transistor through the at least one wire connected to the first golden finger area;
the at least one transistor comprises a first transistor, a second transistor and a third transistor, the first transistor is positioned at the left side of a first row in the plurality of GOA units, the second transistor is positioned at the middle of the first row in the plurality of GOA units, the third transistor is positioned at the right side of the first row in the plurality of GOA units, the at least one wire comprises a first wire, a second wire and a third wire, at least one test pad of the printed circuit board comprises a first test pad, a second test pad and a third test pad, and at least one test pad of the flip-chip film comprises a fourth test pad, a fifth test pad and a sixth test pad;
the gates of the first transistor, the second transistor and the third transistor are respectively connected to the first golden finger area through the first wiring, the second wiring and the third wiring, and the gates of the first transistor, the second transistor and the third transistor are electrically connected with the first test pad, the second test pad and the third test pad;
the grid electrodes of the first transistor, the second transistor and the third transistor are respectively connected to the second golden finger area through the first wiring, the second wiring and the third wiring, and the grid electrodes of the first transistor, the second transistor and the third transistor are electrically connected with the fourth test pad, the fifth test pad and the sixth test pad so as to test the grid waveforms of the transistors in the display panel through the test pads of the flip-chip film or the printed circuit board.
2. The display panel of claim 1, wherein the printed circuit board is provided with a timing controller, a level shifter and a power switch, wherein the level shifter is electrically connected with the timing controller and the power switch, respectively.
3. The display panel of claim 2, wherein the timing controller is configured to provide control signals including a start of frame signal and a field shift pulse signal.
4. The display panel of claim 2, wherein the level shifter is configured to convert levels of the analog ground voltage and the analog operating voltage to a gate-off voltage and a gate-on voltage.
5. The display panel of claim 2, wherein the power switch is configured to turn the level shifter on or off.
6. A display device comprising the display panel according to any one of claims 1 to 5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911168213.4A CN110796975B (en) | 2019-11-25 | 2019-11-25 | Display panel and display device |
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| CN201911168213.4A CN110796975B (en) | 2019-11-25 | 2019-11-25 | Display panel and display device |
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| CN110796975A CN110796975A (en) | 2020-02-14 |
| CN110796975B true CN110796975B (en) | 2023-11-28 |
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| CN111488859B (en) * | 2020-05-06 | 2023-06-06 | 武汉华星光电技术有限公司 | Fingerprint identification driving circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102131342A (en) * | 2011-03-01 | 2011-07-20 | 昆山龙腾光电有限公司 | Printed circuit board and liquid crystal display device |
| CN107340657A (en) * | 2017-08-04 | 2017-11-10 | 深圳市华星光电技术有限公司 | Array base palte |
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| CN105096789B (en) * | 2015-09-25 | 2018-01-30 | 武汉华星光电技术有限公司 | GOA tests the common circuit with removing power-off ghost shadow |
| CN108154833A (en) * | 2018-01-03 | 2018-06-12 | 京东方科技集团股份有限公司 | The output detection circuit and its method of a kind of gate driving circuit, display device |
| CN108873525B (en) * | 2018-07-17 | 2019-09-20 | 深圳市华星光电半导体显示技术有限公司 | A kind of measurement circuit of the grid line of array substrate |
| CN110428760A (en) * | 2019-06-27 | 2019-11-08 | 重庆惠科金渝光电科技有限公司 | Display panel testing method, display panel and display device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102131342A (en) * | 2011-03-01 | 2011-07-20 | 昆山龙腾光电有限公司 | Printed circuit board and liquid crystal display device |
| CN107340657A (en) * | 2017-08-04 | 2017-11-10 | 深圳市华星光电技术有限公司 | Array base palte |
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