CN110890044B - Display device test structure and display device test system - Google Patents
Display device test structure and display device test system Download PDFInfo
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- CN110890044B CN110890044B CN201911175991.6A CN201911175991A CN110890044B CN 110890044 B CN110890044 B CN 110890044B CN 201911175991 A CN201911175991 A CN 201911175991A CN 110890044 B CN110890044 B CN 110890044B
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- 238000006243 chemical reaction Methods 0.000 description 4
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The invention provides a display device test structure and a display device test system, wherein the display device test structure comprises: the debugging device comprises a display device and a debugging plate connected with the display device; the display device comprises a display panel, a driving circuit board and a flexible circuit board for connecting the display panel and the driving circuit board; wherein, be provided with first sequence control chip on the debugging board, be provided with time sequence control module on the drive circuit board, first sequence control chip is used for exporting a synchronization control signal to time sequence control module, so that time sequence control module output time sequence signal, and through the time sequence control module integration to the drive circuit board in the former time sequence control chip, the screen factory just can write into this time sequence control module with the relevant settlement of relevant screen drive before shipment, thereby solved current customer end need confirm to screen factory repeatedly in the debugging process just can export the technical problem of correct time sequence signal, and then greatly increased work efficiency.
Description
Technical Field
The application relates to the field of display, in particular to a display device testing structure and a display device testing system.
Background
At present, in the existing design of a timing control chip, a client core usually integrates a timing control module and other functional modules together, thereby achieving the purpose of reducing cost.
In recent years, a screen factory generally adopts a debugging board for debugging, a client generally integrates a time sequence control module in a client core according to self requirements and tests the client core, and a driving chip and a driving structure used by the screen factory and the client in the debugging process are different.
Therefore, when the existing test structure of the display device is debugged, the time sequence of the client core is not set by the screen factory specification, so that when a new core is introduced into the client, the screen factory is required to confirm the time sequence again, and a great additional cost is caused.
Disclosure of Invention
The application provides a display device test structure and display device test system can solve the technical problem that the correct time sequence signal can be output only if the existing client needs to repeatedly confirm to a screen factory in the debugging process.
The application provides a display device test structure, includes: the debugging device comprises a display device and a debugging plate connected with the display device; the display device comprises a display panel, a driving circuit board and a flexible circuit board for connecting the display panel and the driving circuit board;
the debugging board is provided with a first time sequence control chip, the driving circuit board is provided with a time sequence control module, and the first time sequence control chip is used for outputting a synchronous control signal to the time sequence control module so that the time sequence control module outputs a time sequence signal.
In the display device test structure that this application provided, still be provided with gamma voltage module on the driving circuit board, gamma voltage module is used for exporting gamma voltage under synchronous control signal's control, gamma voltage with the synthetic back drive of sequential signal display panel.
In the display device test structure that this application provided, work as when display panel is in the debugging state, first time sequence control chip output synchronization control signal extremely gamma voltage module with time sequence control module, so that gamma voltage module output debugging gamma voltage makes time sequence control module output debugging time sequence signal, debugging gamma voltage with the synthetic back drive of debugging time sequence signal display panel.
In the display device test structure that this application provided, when display panel is in the display mode, gamma voltage module output shows gamma voltage, time sequence control module output shows sequential signal, show gamma voltage with show that sequential signal synthesizes the back drive display panel.
In the test structure of the display device provided by the application, the driving circuit board is provided with a second time sequence control chip, and the time sequence control module is integrated on the second time sequence control chip.
In the test structure of the display device provided by the application, the second time sequence control chip is arranged on one side, close to the debugging plate, of the driving circuit board.
The present application further provides a display device test system, including: the debugging device comprises a display device and a debugging plate connected with the display device; the display device comprises a display panel, a driving circuit board and a flexible circuit board for connecting the display panel and the driving circuit board;
the debugging board is provided with a first time sequence control chip, the driving circuit board is provided with a time sequence control module, and the first time sequence control chip is used for outputting a synchronous control signal to the time sequence control module so that the time sequence control module outputs a time sequence signal.
In the display device test system that this application provided, still be provided with gamma voltage module on the drive circuit board, gamma voltage module is used for exporting gamma voltage under synchronous control signal's control, gamma voltage with the time sequence signal synthesizes the back drive display panel.
In the display device test system provided by the application, a second time sequence control chip is arranged on the driving circuit board, and the time sequence control module is integrated on the second time sequence control chip.
In the display device test system provided by the application, the second time sequence control chip is arranged on one side, close to the debugging plate, of the driving circuit board.
In the display device test structure and display device test system that this application provided, through the time sequence control module integration to the drive circuit board in the former time sequence control chip, the screen factory just can write into this time sequence control module with the relevant settlement of relevant screen drive before the shipment like this, in the test procedure, only need the debugging board to time sequence control module and gamma voltage module output a synchronization control signal, make time sequence control module output time sequence signal, gamma voltage module output gamma voltage, gamma voltage and time sequence signal synthesis after drive display panel can, thereby solved current customer end and need confirm repeatedly to the screen factory in the debugging process and just can output the technical problem of exact time sequence signal, and then greatly increased work efficiency.
Drawings
In order to more clearly illustrate the technical solutions in the present application, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings may be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a test structure of a display device according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a source circuit driving chip according to an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of another test structure of a display device according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a display device testing system according to an embodiment of the present disclosure;
fig. 5 is another schematic structural diagram of a display device testing system according to an embodiment of the present disclosure.
Detailed Description
The technical solution in the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a test structure of a display device according to an embodiment of the present disclosure. As shown in fig. 1, a test structure of a display device provided in an embodiment of the present application includes: a display device 101 and a debug board 102 connected to the display device 101; the display device 101 includes a display panel 103, a driving circuit board 104, and a flexible circuit board 105 for connecting the display panel 103 and the driving circuit board 104; the first timing control chip 1021 is disposed on the debug board 102, and the timing control module 1041 and the gamma voltage module 1042 are disposed on the driving circuit board 104.
It can be understood that the first timing control chip 1021 is configured to output a synchronization control signal to the timing control module 1041 and the gamma voltage module 1042, so that the timing control module 1041 outputs a timing signal, the gamma voltage module 1042 outputs a gamma voltage, and the gamma voltage and the timing signal are synthesized to drive the display panel 103; the first timing control chip 1021 includes a plurality of sub-modules for adjusting the quality of the display panel 103, such as sub-modules for solving the problem of uneven brightness of the display panel 103, and the sub-modules are not affected with each other, and are configured to output different control signals to the timing control module 1041 and the gamma voltage module 1042 according to the requirement for adjusting the quality of the display panel 103, so that the timing control module 1041 outputs a timing signal and the gamma voltage module 1042 outputs a gamma voltage.
As can be understood, the flexible circuit board 105 is provided with a source circuit driving chip, and the source circuit driving chip is used for synthesizing the gamma voltage and the timing signal, so as to generate the gray scale voltage to drive the display panel 103.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a source circuit driving chip according to an embodiment of the present disclosure. As shown in fig. 2, the source circuit driving chip provided in the embodiment of the present application includes: a data receiving module 1051, a data storage module 1052, a digital-to-analog conversion module 1053 and a voltage follower module 1054.
The data receiving module 1051 is configured to receive a timing signal output from the timing control module 1041, transmit the received timing signal to the data storage module 1052, and transmit the received timing signal to the digital-to-analog conversion module 1053, the digital-to-analog conversion module 1053 further receives a gamma voltage output from the gamma voltage module 1042, then the digital-to-analog conversion module 1053 synthesizes the gamma voltage and the timing signal to generate a gray scale voltage, and transmits the gray scale voltage to the voltage follower module 1054, and the voltage follower module 1054 transmits the gray scale voltage to the display panel 103 after performing amplification and correction of current driving capability to drive the display panel 103.
In one embodiment, when the display panel 103 is in the debug mode, the first timing control chip 1021 outputs a synchronization control signal to the gamma voltage module 1042 and the timing control module 1041, so that the gamma voltage module 1042 outputs a debug gamma voltage, the timing control module 1041 outputs a debug timing signal, and the debug gamma voltage and the debug timing signal are synthesized to drive the display panel 103.
In an embodiment, when the display panel 103 is in a display state, the gamma voltage module 1042 outputs a display gamma voltage, the timing control module 1041 outputs a display timing signal, and the display gamma voltage and the display timing signal are synthesized to drive the display panel 103.
The driving circuit board 104 is further provided with a level shifting module for raising the high and low levels of the timing signal output by the timing control module 1041 to the levels of the turn-on voltage and the turn-off voltage, so as to meet the requirement of driving the display panel 103.
Referring to fig. 3, fig. 3 is another schematic structural diagram of a test structure of a display device according to an embodiment of the present disclosure. As shown in fig. 3, the test structure of the display device provided in the embodiment of the present application includes: a display device 201 and a debug board 202 connected to the display device 201; the display device 201 includes a display panel 203, a driving circuit board 204, and a flexible circuit board 205 for connecting the display panel 203 and the driving circuit board 204; the debug board 202 is provided with a first timing control chip 2021, the driving circuit board 204 is provided with a second timing control chip 2041 and a gamma voltage chip 2042, and the second timing control chip 2041 is integrated with a timing control module 20411.
The first timing control chip 2021 is configured to output a synchronization control signal to the second timing control chip 2041 and the gamma voltage chip 2042, so that the timing control module 20411 outputs a timing signal, the gamma voltage chip 2042 outputs a gamma voltage, and the display panel 203 is driven after the gamma voltage and the timing signal are synthesized.
In one embodiment, the second timing control chip 2041 is disposed on the side of the driving circuit board 204 close to the debugging board 202, so that the length of the trace between the output of the second timing control chip 2041 and the output of the first timing control chip 2021 can be reduced, the time for the first timing control chip 2021 to output a control signal to the second timing control chip 2041 can be reduced, the efficiency can be improved, and the layout of the trace can be reduced, thereby saving the cost.
In one embodiment, the second timing control chip 2041 may be disposed at a position where the sum of the distances from the flexible circuit board 205 and the debug board 202 is the smallest, so that the time consumption for the second timing control chip 2041 to output the timing signal to the flexible circuit board 205 is the smallest when the first timing control chip 2021 outputs the control signal to the second timing control chip 2041, the work efficiency is maximized, and the layout of routing lines can be reduced, thereby saving the cost. Of course, the Gamma voltage chip 2042 may also be arranged according to the above requirements, but it needs to satisfy the requirement that the Gamma voltage chip 2042 and the second timing control chip 2041 do not affect each other, wherein the specific setting positions of the Gamma voltage chip 2042 and the second timing control chip 2041 can be determined by specific tests.
In the application provides a display device test structure, through the time sequence control module integration to the drive circuit board in the original time sequence control chip, the screen factory just can write in relevant settlement of screen drive into in this time sequence control module before shipment like this, in the test procedure, only need the debugging board to time sequence control module and gamma voltage module output a synchronization control signal, make time sequence control module output time sequence signal, gamma voltage module output gamma voltage, gamma voltage and time sequence signal synthesis after drive display panel can, thereby solved current client and need confirm repeatedly to the screen factory in the debugging process and just can export the technical problem of correct time sequence signal, and then greatly increased work efficiency.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a display device testing system according to an embodiment of the present disclosure. As shown in fig. 4, the display device testing system provided in the embodiment of the present application includes: a display device 301 and a debug board 302 connected to the display device 301; the display device 301 includes a display panel 303, a driving circuit board 304, and a flexible circuit board 305 for connecting the display panel 303 and the driving circuit board 304; the debug board 302 is provided with a first timing control chip 3021, and the driving circuit board 304 is provided with a timing control module 3041 and a gamma voltage module 3042.
It can be understood that the first timing control chip 3021 is configured to output a synchronization control signal to the timing control module 3041 and the gamma voltage module 3042, so that the timing control module 3041 outputs a timing signal, the gamma voltage module 3042 outputs a gamma voltage, and the gamma voltage and the timing signal are synthesized to drive the display panel 303; the first timing control chip 3021 includes a plurality of sub-modules for adjusting the quality of the display panel 303, such as sub-modules for solving the problem of uneven brightness of the display panel 303, and the sub-modules do not affect each other, and are configured to output different control signals to the timing control module 3041 and the gamma voltage module 3042 according to the requirement for adjusting the quality of the display panel 303, so that the timing control module 3041 outputs a timing signal and the gamma voltage module 3042 outputs a gamma voltage.
It can be understood that the flexible circuit board 305 is provided with a source circuit driving chip, and the source circuit driving chip is configured to synthesize the gamma voltage and the timing signal, so as to generate the gray scale voltage to drive the display panel 303.
And in the process of actually operating and debugging the display device at the client. Firstly, the client connects its debug board 302 to the display device 301 through a connection line, and the first timing control chip 3021 in the debug board 302 outputs a synchronization control signal to the timing control module 3041 and the gamma voltage module 3042 disposed in the driving circuit board 304; next, the timing control module 3041 receives the synchronization control signal and outputs the timing signal to the flexible circuit board 305, and the gamma voltage module 3042 receives the synchronization control signal and outputs the gamma voltage to the flexible circuit board 305; then the flexible circuit board 305 processes and integrates the received time sequence signal and gamma voltage through its internal module, generates a gray scale voltage and transmits it to the display panel 303; finally, the debugging of the display panel 303 is completed this time, and then the timing control chip 3021 in the debugging board 302 may continue to output another synchronous control signal to debug other functions of the display panel 303 until all the functional modules of the display panel 303 are debugged.
It can be understood that the first timing control chip 3021 in the debug board 302 outputs different synchronization control signals according to the function of the display panel 303 to be debugged.
Referring to fig. 5, fig. 5 is another schematic structural diagram of a display device testing system according to an embodiment of the present disclosure. As shown in fig. 5, the display device testing system provided in the embodiment of the present application includes: a display device 401 and a debug board 402 connected to the display device 401; the display device 401 includes a display panel 403, a driving circuit board 404, and a flexible circuit board 405 for connecting the display panel 403 and the driving circuit board 404; the debugging board 402 is provided with a first timing control chip 4021, the driving circuit board 404 is provided with a second timing control chip 4041 and a gamma voltage chip 4042, and the second timing control chip 4041 is integrated with a timing control module 40411.
The first timing control chip 4021 is configured to output a synchronization control signal to the second timing control chip 4041 and the gamma voltage chip 4042, so that the timing control module 40411 outputs the timing signal, the gamma voltage chip 4042 outputs the gamma voltage, and the display panel 403 is driven after the gamma voltage and the timing signal are synthesized.
During the process of actually operating and debugging the display device at the client. Firstly, a client connects a debugging board 402 of the client to a display device 401 through a connecting wire, and a first timing control chip 4021 in the debugging board 402 outputs a synchronous control signal to a second timing control chip 4041 and a gamma voltage chip 4042 arranged in a driving circuit board 404; then, the timing control module 40411 in the second timing control chip 4041 receives the synchronization control signal and then outputs a timing signal to the flexible circuit board 405, and the gamma voltage chip 4042 receives the synchronization control signal and then outputs a gamma voltage to the flexible circuit board 405; then the flexible circuit board 405 processes and integrates the received timing signal and gamma voltage through the internal modules thereof to generate a gray scale voltage and transmit the gray scale voltage to the display panel 403; finally, the debugging of the display panel 403 is completed this time, and then the timing control chip 4021 in the debugging board 402 may continue to output another synchronous control signal to debug other functions of the display panel until all the functional modules of the display panel 403 are debugged.
It can be understood that the first timing control chip 4021 in the debug board 402 outputs different synchronization control signals according to the function of the display panel 403 to be debugged.
In the application provides a display device test system, through integrating the time sequence control module in the original time sequence control chip to drive circuit board, the screen factory just can write in relevant settlement of screen drive into this time sequence control module before shipment like this, in the test procedure, only need the debugging board to time sequence control module and gamma voltage module output a synchronization control signal, make time sequence control module output time sequence signal, gamma voltage module output gamma voltage, gamma voltage and time sequence signal synthesis after drive display panel can, thereby solved current client and need confirm repeatedly to the screen factory in the debugging process and just can export the technical problem of correct time sequence signal, and then greatly increased work efficiency.
The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented only to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display device test structure, comprising: the debugging device comprises a display device and a debugging plate connected with the display device; the display device comprises a display panel, a driving circuit board and a flexible circuit board for connecting the display panel and the driving circuit board;
the debugging board is provided with a first time sequence control chip, the driving circuit board is provided with a time sequence control module, and the first time sequence control chip is used for outputting a synchronous control signal to the time sequence control module so that the time sequence control module outputs a time sequence signal; and the time sequence control chip outputs different synchronous control signals according to the function of the display panel to be debugged.
2. The testing structure of claim 1, wherein a gamma voltage module is further disposed on the driving circuit board, the gamma voltage module is configured to output a gamma voltage under the control of the synchronization control signal, and the gamma voltage is synthesized with the timing signal to drive the display panel.
3. The test structure of claim 2, wherein when the display panel is in a debug mode, the first timing control chip outputs synchronous control signals to the gamma voltage module and the timing control module, so that the gamma voltage module outputs a debug gamma voltage, the timing control module outputs a debug timing signal, and the debug gamma voltage and the debug timing signal are synthesized to drive the display panel.
4. The testing structure of claim 2, wherein when the display panel is in a display state, the gamma voltage module outputs a display gamma voltage, the timing control module outputs a display timing signal, and the display gamma voltage and the display timing signal are synthesized to drive the display panel.
5. The test structure of claim 1, wherein a second timing control chip is disposed on the driving circuit board, and the timing control module is integrated on the second timing control chip.
6. The display device test structure of claim 5, wherein the second timing control chip is disposed on a side of the driving circuit board close to the debugging board.
7. A display device test system, comprising: the debugging device comprises a display device and a debugging plate connected with the display device; the display device comprises a display panel, a driving circuit board and a flexible circuit board for connecting the display panel and the driving circuit board;
the debugging board is provided with a first time sequence control chip, the driving circuit board is provided with a time sequence control module, and the first time sequence control chip is used for outputting a synchronous control signal to the time sequence control module so that the time sequence control module outputs a time sequence signal; and the time sequence control chip outputs different synchronous control signals according to the function of the display panel to be debugged.
8. The system for testing a display device of claim 7, wherein a gamma voltage module is further disposed on the driving circuit board, the gamma voltage module is configured to output a gamma voltage under the control of the synchronization control signal, and the gamma voltage is synthesized with the timing signal to drive the display panel.
9. The display device testing system according to claim 7, wherein a second timing control chip is disposed on the driving circuit board, and the timing control module is integrated on the second timing control chip.
10. The display device test system according to claim 9, wherein the second timing control chip is disposed on a side of the driving circuit board close to the debug board.
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