CN107424553B - Scanning driving circuit board and display device - Google Patents
Scanning driving circuit board and display device Download PDFInfo
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- CN107424553B CN107424553B CN201710871460.5A CN201710871460A CN107424553B CN 107424553 B CN107424553 B CN 107424553B CN 201710871460 A CN201710871460 A CN 201710871460A CN 107424553 B CN107424553 B CN 107424553B
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 11
- 230000001934 delay Effects 0.000 claims 4
- 230000003111 delayed effect Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- ORFSSYGWXNGVFB-UHFFFAOYSA-N sodium 4-amino-6-[[4-[4-[(8-amino-1-hydroxy-5,7-disulfonaphthalen-2-yl)diazenyl]-3-methoxyphenyl]-2-methoxyphenyl]diazenyl]-5-hydroxynaphthalene-1,3-disulfonic acid Chemical compound COC1=C(C=CC(=C1)C2=CC(=C(C=C2)N=NC3=C(C4=C(C=C3)C(=CC(=C4N)S(=O)(=O)O)S(=O)(=O)O)O)OC)N=NC5=C(C6=C(C=C5)C(=CC(=C6N)S(=O)(=O)O)S(=O)(=O)O)O.[Na+] ORFSSYGWXNGVFB-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a scanning driving circuit board and a display device. The display device comprises a display area, a signal connecting plate, a time sequence control plate, a signal conversion plate and a scanning driving circuit board, wherein the time sequence control plate comprises a time sequence control chip and a level conversion chip, and the scanning driving circuit board comprises a debugging interface connected with an online debugging device; the memory stores the time sequence parameter of the driving time; the drive control chip reads the time sequence parameter of the drive time and online debugs the time sequence parameter of the drive time through the debugging interface, and generates a signal waveform according to the time sequence parameter so as to meet the test requirement of the display device by online debugging the drive time.
Description
Technical Field
The invention relates to the technical field of display, in particular to a scanning driving circuit board and a display device.
Background
The GOA (Gate Driver On Array, Array substrate line drive) integrates a Gate line driving circuit On an Array substrate by using an Array process, which can save a Gate driving chip On the Array substrate, thereby achieving the purposes of reducing production cost and realizing a narrow frame, the structure diagram of the existing display device is shown in fig. 1, and the existing display device supporting ud (ultra High definition) display technology is a Timing Controller (TCON) chip with a resolution of 3840 × 2160(4K × 2K) and above (8K), which cannot perform online debugging On the driving time of the display device, and therefore cannot meet the test requirements of the display device.
Disclosure of Invention
The invention mainly solves the technical problem of providing a scanning driving circuit board and a display device, so as to meet the test requirement of the display device by online debugging the driving time of the display device.
In order to solve the technical problems, the invention adopts a technical scheme that: provided is a scan driving circuit board including:
the debugging interface is used for connecting the online debugging device;
a memory for storing a timing parameter of the driving time;
and the drive control chip is connected with the memory and used for reading the time sequence parameter of the drive time from the memory to initialize, and the drive control chip is also connected with the debugging interface and used for online debugging the time sequence parameter of the drive time through an online debugging device connected with the debugging interface and generating a signal waveform according to the time sequence parameter.
In order to solve the technical problems, the invention adopts a technical scheme that: the display device is characterized by comprising a display area, a signal connecting plate connected with the display area, a time sequence control plate connected with the signal connecting plate, a signal conversion plate connected with the time sequence control plate and a scanning driving circuit board, wherein the signal conversion plate is used for connecting a video source, the scanning driving circuit board is used for connecting an online debugging device, the signal connecting plate is used for connecting an oscilloscope, the time sequence control plate comprises a time sequence control chip and a level conversion chip, and the scanning driving circuit board comprises:
the debugging interface is used for connecting the online debugging device;
a memory for storing a timing parameter of the driving time;
and the drive control chip is connected with the memory and used for reading the time sequence parameter of the drive time from the memory to initialize, and the drive control chip is also connected with the debugging interface and used for online debugging the time sequence parameter of the drive time through an online debugging device connected with the debugging interface and generating a signal waveform according to the time sequence parameter.
The invention has the beneficial effects that: different from the situation of the prior art, the display device provided by the invention has the advantages that the scanning driving circuit board is arranged, and the driving control chip, the memory and the debugging interface are arranged on the scanning driving circuit board, so that the scanning driving circuit board is connected with the time sequence control board and the online debugging device, and the online debugging device is used for online debugging of the time sequence parameters of the driving time, so that the testing requirements of the display device are met.
Drawings
FIG. 1 is a schematic diagram of a conventional display device;
FIG. 2 is a schematic structural diagram of a display device according to the present invention;
FIG. 3 is a circuit diagram of the scan driving circuit board and the timing control board in FIG. 2;
FIG. 4 is a circuit schematic diagram of the scan driving circuit board of FIG. 2;
fig. 5 is a schematic diagram of the driving time waveform of the present invention.
Detailed Description
Please refer to fig. 2 to fig. 4, which are schematic structural diagrams of the display device of the present invention. The display device 1 includes a display area 10, a signal connection board 11 connected to the display area 10, a timing control board 12 connected to the signal connection board 11, a signal conversion board 13 connected to the timing control board 12, and a scan driving circuit board 14, where the signal conversion board 13 is used to connect a video source 2, the scan driving circuit board 14 is used to connect an online debugging device, such as a computer 4, through an I2C bus jig board 3, the signal connection board 11 is used to connect an oscilloscope 5, the timing control board 12 includes a timing control chip 121 and a level conversion chip 122, and the scan driving circuit board 14 includes:
a debugging interface 143 for connecting an online debugging device, such as a computer 3;
a memory 141 for storing a timing parameter of the driving time; and
and the driving control chip 142 is connected to the memory 141 and configured to read the timing parameter of the driving time from the memory 141 for initialization, and the driving control chip 142 is further connected to the debugging interface 143 and configured to debug the timing parameter of the driving time on line through an online debugging device connected to the debugging interface 143 and generate a signal waveform according to the timing parameter.
In this embodiment, other devices and functions of the display area 10, the signal connection board 11, the signal conversion board 13, and the timing control board 12 are the same as those of the prior art, and the timing control chip 121 and the level conversion chip 122 of the timing control board 12 are also the same as those of the prior art, and are not described herein again. The online debugging device is a computer 4 electrically connected to the scan driving circuit board 14 through an I2C bus jig board 3, wherein the I2C bus jig board 3 is a conventional device and is not described herein again. The signal conversion board 13 is used to convert an image signal into a control signal, such as an LVDS signal, into a Vx1 signal.
Specifically, the driving control chip 142 includes a parameter configuration unit 1421 and a driving time unit 1422, the parameter configuration unit 1421 is configured to read the timing parameter of the driving time from the memory 141 for initialization and online debug the timing parameter of the driving time through an online debugging device connected to the debugging interface 143, and the driving time unit 1422 is configured to generate a signal waveform according to the timing parameter.
Specifically, the parameter configuration unit 1421 includes a master unit 14211 and a slave unit 14212, the master unit 14211 is configured to read the timing parameter of the driving time from the memory 141 for initialization, and the slave unit 14212 is configured to debug the timing parameter of the driving time on line through an online debugging device connected to the debugging interface 143.
Specifically, the driving time unit 1422 includes:
a trigger signal delay unit 14221, configured to delay the video data valid indicator DE according to the delay parameter in the parameter configuration unit 1421, so as to generate a trigger delay signal STV _ DE;
a clock signal delay unit 14222, configured to delay the video data valid indication signal DE according to the delay parameter in the parameter configuration unit 1421, so as to generate a clock delay signal CK _ DE; the clock signal delay unit 14222 and the trigger signal delay unit 14221 have the same function, but the two units are independent, so that they do not interfere with each other when performing online debugging.
A trigger signal generating unit 14223, configured to generate a trigger signal STV waveform according to the trigger signal parameter in the parameter configuration unit 1421 and the trigger delay signal STV _ DE;
a clock signal generating unit 14224 for generating a clock signal CK waveform, such as clock signal CK1, CK2, CK3, CK4 to CKN, according to the clock signal CK parameter, the video data valid indication signal DE parameter and the clock delay signal CK _ DE in the parameter configuration unit 1421; and
the circuit switching control signal generating unit 14225 generates a waveform of the circuit switching control signal LC during an inactive period of a frame by generating a frame number by counting the trigger delay signal STV _ DE according to the inversion period of the circuit switching control signal LC in the parameter configuration unit 1421.
In this embodiment, the memory 141 is an electrically erasable programmable read only memory, and the stored timing parameters of the driving time include a high level width of the trigger signal STV, a number of delay clocks of the trigger signal STV, a high level width of the clock signal CK, a number of delay clocks of the clock signal CK, a flip period of the circuit switching control signal LC, a number of valid display clocks of the video data valid indication signal DE, and a number of clocks of a blank area of the video data valid indication signal DE; the debug interface 143 is an I2C bus debug interface, the master device 14211 is an I2C bus master device, the slave device 14212 is an I2C bus slave device, the scan driving circuit board 14 is connected to the video data valid indication signal DE and the clock signal CLK of the timing control chip 121 on the timing control board 12, and the scan driving circuit board 14 is connected to the trigger signal STV, the first circuit switching control signal LC1, the second circuit switching control signal LC2 and the plurality of clock signals CK of the level shift chip 122 on the timing control board 12.
The scan driving circuit board 14 is connected to the video data valid indication signal DE and the clock signal CLK of the timing control chip 121 on the timing control board 12 through a flexible circuit board (not shown), and is simultaneously connected to the trigger signal STV of the level shift chip 122 on the timing control board 12, the first circuit switching control signal LC1, the second circuit switching control signal LC2, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, and so on until the nth clock signal CKN, wherein the value of N depends on the number of scanning lines of the display device.
The working principle of the display device for online adjusting the driving time is described as follows:
the oscilloscope 5 is electrically connected with the signal connection board 11, the scan driving circuit board 14 is connected with the computer 4 through the I2C jig board 3, the display device 1 is started after the signal conversion board 13 is connected with the video source 2, the driving control chip 142 on the scan driving circuit board 14 is powered on and initialized, the time sequence parameters of the driving time stored in the memory 141 are read through the I2C bus, and when the time sequence parameters are successfully configured, the corresponding indicator light is lightened to indicate that the time sequence parameter configuration is completed. Then, the driving control chip 142 on the scan driving circuit board 14 sets corresponding registers according to the timing parameters, and continuously detects the video data valid indication signal DE under the control of the clock signal CLK of the timing control chip 121 on the timing control board 12, the driving control chip 142 on the scan driving circuit board 14 correspondingly generates a trigger signal STV, a first circuit switching control signal LC1, a second circuit switching control signal LC2, a first clock signal CK1, a second clock signal CK2 …, an nth clock signal CKN, and displays them by an oscilloscope 5 (as shown in fig. 5) for a tester to watch, for example, signal waveforms such as duty ratio of the trigger signal STV, since the scan driving circuit board 14 is connected to the computer 4 through the I2C jig board 3, at this time, software in the computer 4 communicates with the scan driving circuit board 14 through the I2C jig board 3, at this time, the driving control chip 142 on the scanning driving circuit board 14 becomes a slave of the I2C bus, and the computer 4 becomes a host of the I2C bus, and plays a designated test image (such as a test image of pure red, pure green, pure blue, etc.) through the video source 2, and a tester sends a time sequence parameter of driving time through the computer 4 according to a signal waveform displayed by the oscilloscope 5 to update a register of the driving control chip 142 in real time, so as to implement online debugging of the driving time, thereby meeting the test requirement of the display device 1. After the driving time is debugged on line, that is, the optimal timing sequence parameter of the driving time is obtained, the computer 4 burns the optimal timing sequence parameter of the driving time into the memory 141 of the scan driving circuit board 14 through the I2C bus jig board 3, so that when the display device 1 is restarted, the scan driving circuit board 14 uses the optimal timing sequence parameter of the driving time, and then other parameters (such as an algorithm of the timing control chip) of the display device 1 can be tested, so as to meet the test requirement of the display device 1.
The display device is provided with the scanning driving circuit board, and the scanning driving circuit board is provided with the driving control chip, the memory and the debugging interface, so that the scanning driving circuit board is connected with the time sequence control board and the online debugging device, and the online debugging device is used for online debugging of the time sequence parameters of the driving time, thereby meeting the testing requirements of the display device.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A scan driving circuit board, comprising:
the debugging interface is used for connecting the online debugging device; the debugging interface is an I2C bus debugging interface;
a memory for storing a timing parameter of the driving time;
the drive control chip is connected with the memory and used for reading the time sequence parameter of the drive time from the memory to initialize, and the drive control chip is also connected with the debugging interface and used for debugging the time sequence parameter of the drive time on line through an online debugging device connected with the debugging interface and generating a signal waveform according to the time sequence parameter;
the drive control chip sets a corresponding register according to the time sequence parameter, the register stores the time sequence parameter of the drive time debugged by the online debugging device in real time, and the online debugging device burns the best time sequence parameter obtained by testing into the memory through the debugging interface.
2. The scan driving circuit board of claim 1, wherein the driving control chip comprises a parameter configuration unit and a driving time unit, the parameter configuration unit is configured to read timing parameters of the driving time from the memory for initialization and online debug the timing parameters of the driving time through an online debugging device connected to the debugging interface, and the driving time unit is configured to generate a signal waveform according to the timing parameters.
3. The scan driving circuit board of claim 2, wherein the parameter configuration unit comprises a master unit and a slave unit, the master unit is configured to read the timing parameter of the driving time from the memory for initialization, and the slave unit is configured to debug the timing parameter of the driving time online through an online debugging device connected to the debugging interface.
4. The scan driving circuit board of claim 3, wherein the driving time unit comprises:
the trigger signal delay unit delays the video data effective indication signal according to the delay parameters in the parameter configuration unit to generate a trigger delay signal;
the clock signal delay unit delays the video data effective indication signal according to the delay parameter in the parameter configuration unit to generate a clock delay signal;
the trigger signal generating unit generates a trigger signal waveform according to the trigger signal parameters in the parameter configuration unit and the trigger delay signal;
the clock signal generating unit generates a clock signal waveform according to the clock signal parameter, the video data effective indication signal parameter and the clock delay signal in the parameter configuration unit; and
and the circuit switching control signal generating unit is used for generating the waveform of the circuit switching control signal in the invalid period of the frame according to the overturning period of the circuit switching control signal in the parameter configuration unit and the frame number generated by counting the trigger delay signal.
5. The scan driving circuit board of claim 3, wherein the memory is an Electrically Erasable Programmable Read Only Memory (EEPROM), and the stored timing parameters of the driving time include a high level width of the trigger signal, a number of delayed clocks of the trigger signal, a high level width of the clock signal, a number of delayed clocks of the clock signal, a flip period of the circuit switching control signal, a number of valid display clocks of the video data valid indication signal, and a number of clocks of the blank area of the video data valid indication signal; the master device is an I2C bus master device, and the slave device is an I2C bus slave device.
6. The display device is characterized by comprising a display area, a signal connecting plate connected with the display area, a time sequence control plate connected with the signal connecting plate, a signal conversion plate connected with the time sequence control plate and a scanning driving circuit board, wherein the signal conversion plate is used for connecting a video source, the scanning driving circuit board is used for connecting an online debugging device, the signal connecting plate is used for connecting an oscilloscope, the time sequence control plate comprises a time sequence control chip and a level conversion chip, and the scanning driving circuit board comprises:
the debugging interface is used for connecting the online debugging device; the debugging interface is an I2C bus debugging interface;
a memory for storing a timing parameter of the driving time;
the drive control chip is connected with the memory and used for reading the time sequence parameter of the drive time from the memory to initialize, and the drive control chip is also connected with the debugging interface and used for debugging the time sequence parameter of the drive time on line through an online debugging device connected with the debugging interface and generating a signal waveform according to the time sequence parameter;
the drive control chip sets a corresponding register according to the time sequence parameter, the register stores the time sequence parameter of the drive time debugged by the online debugging device in real time, and the online debugging device burns the best time sequence parameter obtained by testing into the memory through the debugging interface.
7. The display device according to claim 6, wherein the driving control chip comprises a parameter configuration unit and a driving time unit, the parameter configuration unit is configured to read timing parameters of the driving time from the memory for initialization and online debug the timing parameters of the driving time through an online debugging device connected to the debugging interface, and the driving time unit is configured to generate a signal waveform according to the timing parameters.
8. The display device according to claim 7, wherein the parameter configuration unit comprises a master unit and a slave unit, the master unit is configured to read the timing parameter of the driving time from the memory for initialization, and the slave unit is configured to debug the timing parameter of the driving time online through an online debugging device connected to the debugging interface.
9. The display device according to claim 8, wherein the driving time unit comprises:
the trigger signal delay unit delays the video data effective indication signal according to the delay parameter in the parameter configuration unit to generate a trigger delay signal;
the clock signal delay unit delays the video data effective indication signal according to the delay parameter in the parameter configuration unit to generate a clock delay signal;
the trigger signal generating unit generates a trigger signal waveform according to the trigger signal parameters in the parameter configuration unit and the trigger delay signal;
the clock signal generating unit generates a clock signal waveform according to the clock signal parameter, the video data effective indication signal parameter and the clock delay signal in the parameter configuration unit; and
and the circuit switching control signal generating unit is used for generating the waveform of the circuit switching control signal in the invalid period of the frame according to the overturning period of the circuit switching control signal in the parameter configuration unit and the frame number generated by counting the trigger delay signal.
10. The display device according to claim 8, wherein the memory is an eeprom, and the stored timing parameters of the driving time include a high level width of the trigger signal, a number of delayed clocks of the trigger signal, a high level width of the clock signal, a number of delayed clocks of the clock signal, a flip period of the circuit switching control signal, a number of valid display clocks of the video data valid indication signal, and a number of clocks of a blank area of the video data valid indication signal; the scanning driving circuit board is connected with a trigger signal of a level conversion chip on the time sequence control board, a first circuit switching control signal, a second circuit switching control signal and a plurality of clock signals.
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| CN108346404B (en) * | 2018-03-05 | 2020-11-24 | 昆山龙腾光电股份有限公司 | Parameter debugging method of a timing controller and screen drive circuit |
| CN108520714B (en) * | 2018-03-27 | 2021-03-23 | 苏州佳智彩光电科技有限公司 | Test method and system supporting multiple working modes of OLED screen |
| CN110888766B (en) * | 2019-11-18 | 2023-08-01 | 珠海泰芯半导体有限公司 | Chip starting method |
| CN114255712B (en) * | 2020-09-22 | 2023-02-03 | 咸阳彩虹光电科技有限公司 | Display method and display device |
| CN112133236A (en) * | 2020-09-28 | 2020-12-25 | 深圳创维－Rgb电子有限公司 | Display screen testing method, oscilloscope and storage medium |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101089678A (en) * | 2006-06-16 | 2007-12-19 | 群康科技(深圳)有限公司 | Detection device for flat display picture and detection method thereof |
| CN101009074B (en) * | 2006-12-13 | 2011-05-11 | 康佳集团股份有限公司 | A LED scanning board with the self-testing function and its testing method |
| CN201392473Y (en) * | 2009-04-16 | 2010-01-27 | 合肥创源智能网络有限责任公司 | On-vehicle network system with online debugging and program downloading functions |
| CN101587679B (en) * | 2009-07-03 | 2011-05-11 | 四川长虹电器股份有限公司 | Test method for energy recovery function of plasma television drive chip |
| TW201220269A (en) * | 2010-11-11 | 2012-05-16 | Novatek Microelectronics Corp | Display controller driver and testing method therewith |
| CN102750914B (en) * | 2011-04-18 | 2014-12-24 | 青岛海信电器股份有限公司 | Display module driving circuit, driving method and liquid crystal television |
| CN202976775U (en) * | 2012-10-17 | 2013-06-05 | 无锡爱迪信光电科技有限公司 | Driving control circuit of LED array |
| CN102968944B (en) * | 2012-11-09 | 2016-04-06 | 深圳Tcl新技术有限公司 | The method of turntable driving output display and device |
| CN103065587B (en) * | 2012-12-28 | 2016-01-20 | 富顺光电科技股份有限公司 | A kind of LED synchronous display controlling system without sending card |
| CN103606357B (en) * | 2013-11-15 | 2016-01-20 | 四川长虹电器股份有限公司 | LCD TV backlight sequence control method and system |
| CN105448216B (en) * | 2014-09-15 | 2019-02-19 | 惠州市德赛西威汽车电子股份有限公司 | A kind of test method of vehicle LCD |
| CN105448220B (en) * | 2015-12-17 | 2018-11-23 | 昆山龙腾光电有限公司 | Driving signal configuration method and device |
| CN206224977U (en) * | 2016-10-12 | 2017-06-06 | 昆山龙腾光电有限公司 | Common electric voltage generating means and display device |
| CN106710496A (en) * | 2017-01-18 | 2017-05-24 | 深圳市视显光电技术有限公司 | Device and method for online debugging of parameters of LCD logic board |
| CN106920500B (en) * | 2017-05-02 | 2020-09-11 | 惠科股份有限公司 | Display driving method and display driving device |
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Address after: No.9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: No.9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |