[go: up one dir, main page]

CN110491859A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

Info

Publication number
CN110491859A
CN110491859A CN201910407970.6A CN201910407970A CN110491859A CN 110491859 A CN110491859 A CN 110491859A CN 201910407970 A CN201910407970 A CN 201910407970A CN 110491859 A CN110491859 A CN 110491859A
Authority
CN
China
Prior art keywords
layer
chip
molding compound
wafer
redistribution layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910407970.6A
Other languages
English (en)
Other versions
CN110491859B (zh
Inventor
郑家明
李柏汉
杨惟中
吴冠荣
张恕铭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
Original Assignee
XinTec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN110491859A publication Critical patent/CN110491859A/zh
Application granted granted Critical
Publication of CN110491859B publication Critical patent/CN110491859B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92124—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种晶片封装体及其制造方法。在所述晶片封装体中，第一接合结构位于第一重布线层上。第一晶片包括邻近一主动面的一感测区及一导电垫。第一晶片通过第一接合结构接合于第一重布线层上，且第一接合结构位于导电垫与第一重布线层之间。模塑料层覆盖第一重布线层且环绕第一晶片。第二重布线层位于模塑料层及第一晶片上，且第二重布线层电性连接至第一重布线层。第二晶片堆叠于第一晶片的非主动面上，且第二晶片通过第二重布线层、第一重布线层及第一接合结构电性连接至第一晶片。本发明能够简化制程步骤、减少制造时间且大幅降低制造成本。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种半导体封装技术，特别有关于一种晶片封装体及其制造方法。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使其免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路，例如晶片封装体内具有导线以形成导电路径。随着电子产品逐渐朝向小型化发展，晶片封装体的尺寸也逐渐缩小。
一般而言，晶片封装体与其他电子元件(例如，各种集成电路晶片或各种被动元件)各自独立地设置于电路板上，且间接地彼此电性连接。虽然目前已发展出系统级封装(System in Package，SiP)的技术来缩小电子产品的尺寸，然而具有感测功能的晶片的感测面不能受到遮蔽，因此制作具有感测功能的系统级封装的晶片封装体是一大挑战，进而导致电路板及所形成的电子产品的尺寸难以进一步缩小。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明实施例提供一种晶片封装体，包括一第一重布线层、一第一接合结构、一第一晶片、一模塑料层、一第二重布线层及一第二晶片。第一接合结构位于第一重布线层上。第一晶片包括邻近主动面的一感测区及一导电垫。第一晶片通过第一接合结构接合于第一重布线层上，且第一接合结构位于导电垫与第一重布线层之间。模塑料层覆盖第一重布线层且环绕第一晶片。第二重布线层位于模塑料层及第一晶片上，且第二重布线层电性连接至第一重布线层。第二晶片堆叠于第一晶片的非主动面上，且第二晶片通过第二重布线层、第一重布线层及第一接合结构电性连接至第一晶片。
本发明实施例提供一种晶片封装体的制造方法，包括形成一第一重布线层。在第一重布线层上形成一第一接合结构。通过第一接合结构将一第一晶片接合于第一重布线层上。第一晶片包括邻近主动面的一感测区及一导电垫，且第一接合结构位于导电垫与第一重布线层之间。形成一模塑料层，以覆盖第一重布线层且环绕第一晶片。在模塑料层及第一晶片上形成一第二重布线层。第二重布线层电性连接至第一重布线层。堆叠一第二晶片。第二晶片位于第一晶片的非主动面上，且第二晶片通过第二重布线层、第一重布线层及第一接合结构电性连接至第一晶片。
附图说明
图1A至1J是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图。
图2是绘示出根据本发明一些实施例的晶片封装体的上视图。
图3A至3J是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图。
图4A至4I是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图。
图5A至5H是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图。
其中，附图中符号的简单说明如下：
100：盖板；110：间隔层；115：开口；330：芯片组；120：重布线层；125：开口；126：孔洞；130：导电结构；140、140a：第一接合结构；150：第一晶片；155：空腔；160：基底；165：感测区；170：绝缘层；180：导电垫；190：光学部件；200：模塑料层；210：绝缘层；215：开口；220：重布线层；230：保护层；235：开口；236：开口；240：导电结构；250、250a：第二晶片；255：第三晶片；260：基底；270：绝缘层；280：导电垫；285：开口；290：第二接合结构；300A、300B、300C、300D：晶片封装体；310：晶圆；320：粘着层。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含主动元件或被动元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronicdevices)、微机电系统(Micro Electro Mechanical System，MEMS)、生物辨识元件(biometric device)、微流体系统(micro fluidic systems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package，WSP)制程对影像感测元件、发光二极管(light-emitting diodes，LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprint recognition device)、微制动器(microactuators)、表面声波元件(surface acoustic wave devices)、压力感测器(processsensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
以下所述实施例可能讨论特定的内容，例如所述晶片封装体及其制造方法应用于影像感测技术，然而所属技术领域中具有通常知识者阅读所揭露内容可理解在其他实施例中可考虑其他各种应用，例如生物特征感测技术。应注意的是，此处所讨论的实施例可能未必叙述出可能存在于结构内的每一个部件，举例来说，当部件的讨论说明足以传达实施例的各个样态时可能将其从图式中省略。再者，此处所讨论的实施例可能未必叙述出每一个制造步骤，且可能以特定的进行顺序讨论晶片封装体的制造方法，然而在其他实施例中，可以以任何合理的顺序进行晶片封装体的制造。
以下配合图1A至1J说明本发明一些实施例的晶片封装体及其制造方法，其中图1A至1J是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图。
请参照图1A，提供一盖板100。在一些实施例中，盖板100包括透光材料，例如盖板100可包括玻璃、氮化铝(AlN)或其他适合的透光材料。在一些其他实施例中，盖板100可作为暂时性载板(carrier)，且将会在后续的制程中被移除，此时盖板100可以包括透光或不透光的载板材料。在一些实施例中，盖板100的形状可为圆形或矩形，且盖板100的尺寸并不受限，例如盖板100可具有8寸或12寸的晶圆尺寸。
之后，在一些实施例中，在盖板100上形成一间隔层(或称作围堰(dam))110，间隔层110具有多个开口115，如图1A所示。在一些实施例中，间隔层110大致上不吸收水气。间隔层110可直接接触盖板100，且间隔层110可不具有黏性。在一些实施例中，可通过集成制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)形成间隔层110。在一些实施例中，间隔层110可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene，BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他适合的绝缘材料。或者，间隔层110可包括光致抗蚀剂材料，且可通过曝光及显影制程而图案化，以形成开口115。
本发明的实施例具有许多变化。在一些其他实施例中，可以以一粘着层取代间隔层110。此粘着层不具有开口，且包括透光材料。
请参照图1B，在间隔层110上形成图案化的一重布线层120(也称为第一重布线层)。在一些实施例中，重布线层120可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。在一些实施例中，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、光刻制程及蚀刻制程，形成图案化的重布线层120。
接着，在重布线层120上形成多个导电结构130，如图1B所示。在一些实施例中，导电结构130及间隔层110直接接触重布线层120，且一部分的重布线层120夹置于导电结构130与间隔层110之间。
导电结构130可以包括导电柱、导电凸块或其他适合的导电结构。在一些实施例中，导电结构130可包括铜、铜合金、钛、钛合金、前述的组合或其他适合的导电材料。在一些实施例中，可通过沉积制程(例如，电镀制程、无电镀制程或其他适合的制程)，在重布线层120上形成导电结构130。举例来说，可在间隔层110及重布线层120上形成具有开口的一遮罩层(未绘示)，此遮罩层可包括光致抗蚀剂材料。遮罩层的开口定义出导电结构130预定形成的位置。接着，进行沉积制程，以在遮罩层的开口内形成导电结构130。之后，将遮罩层去除。
请参照图1C，通过多个第一接合结构140，将一第一晶片150接合于重布线层120上。第一接合结构140可以包括导电层、导电膏、导电胶、导电凸块或其他适合的接合结构。在一些实施例中，第一接合结构140可包括锡、焊料、银、前述的组合或其他适合的导电材料。在一些实施例中，第一接合结构140及导电结构130包括不同的材料，举例来说，第一接合结构140包括锡，而导电结构130包括铜，然而本发明实施例并不限定于此。
在一些实施例中，在重布线层120上形成第一接合结构140，且将第一晶片150以主动面朝向盖板100的方式放置于第一接合结构140上，并进行回焊(reflow)制程，使得第一晶片150经由第一接合结构140连接到重布线层120。在一些其他实施例中，在重布线层120上涂布第一接合结构140，且经由第一接合结构140将第一晶片150直接粘着于重布线层120上。
在一些实施例中，第一接合结构140及间隔层110直接接触重布线层120，且一部分的重布线层120夹置于第一接合结构140与间隔层110之间。在一些实施例中，如图1C所示，导电结构130的厚度(或高度)小于第一晶片150的厚度(或高度)，且导电结构130的厚度大于第一接合结构140的厚度。
在一些实施例中，第一晶片150具有感测影像或生物特征的功能，例如第一晶片150为互补式金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)影像感测(CMOS image sensor，CIS)晶片、光学式指纹感测(fingerprint sensor，FPS)晶片、电容式指纹感测晶片或其他适用的感测晶片。
在一些实施例中，第一晶片150包括一基底160、一感测区165、一绝缘层170、多个导电垫180及一光学部件190，如图1C所示。感测区165、绝缘层170、导电垫180及光学部件190邻近于第一晶片150的主动面，而第一晶片150的非主动面大致上等同于基底160的背表面。在一些其他实施例中，第一晶片150可不包括光学部件190。
在一些实施例中，基底160可为一硅基底或其他半导体基底。绝缘层170位于基底160的前表面上。一般而言，绝缘层170可由层间介电(interlayer dielectric，ILD)层、金属间介电(inter-metal dielectric，IMD)层及覆盖的钝化(passivation)层组成。为简化图式，此处仅绘示出单层绝缘层170。在一些实施例中，绝缘层170可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
导电垫180位于绝缘层170内，且绝缘层170内的钝化层具有露出导电垫180的开口。在一些实施例中，导电垫180可为单层导电层或具有多层的导电层结构。在一些实施例中，导电垫180通过位于绝缘层170内的内连线结构(未绘示)电性连接至感测区165。内连线结构可包括导线、导电介层窗(via)及导电插塞(contact)。
感测区165内包括一感测元件或其他适合的电子元件。在一些实施例中，感测区165内包括感光元件或其他适合的光电元件。在一些其他实施例中，感测区165内可包括感测生物特征的元件(例如，一指纹辨识元件)、感测环境特征的元件(例如，一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件)或其他适合的感测元件。
光学部件190设置于绝缘层170上，且对应于感测区165。在一些实施例中，光学部件190可为微透镜阵列、滤光层、前述的组合或其他适合的光学部件。在一些实施例中，间隔层110具有开口115(标示于图1A中)，在第一晶片150接合于重布线层120上之后，间隔层110在第一晶片150的主动面与盖板100之间围绕出对应于感测区165的一空腔155(如图1C所示)，使得光学部件190可容纳于空腔155内，并通过盖板100保护光学部件190。
请参照图1D，在间隔层110及重布线层120上形成一模塑料层200，模塑料层200环绕导电结构130及第一晶片150。模塑料层200也可称为封胶层(encapsulating layer)。在一些实施例中，模塑料层200直接接触间隔层110、重布线层120、导电结构130及第一晶片150。在一些实施例中，模塑料层200包括模塑成型化合物，例如模塑料层200包括环氧化物(epoxy)、树脂(resin)、可塑形聚合物(moldable polymer)或其他适合的材料。
在一些实施例中，模塑料层200为具延展性的固体，例如由模塑成型化合物所构成的胶片(tape)，可将此胶片贴合在间隔层110上，且包覆住重布线层120、导电结构130及第一晶片150。在一些实施例中，可利用模具注入及固化模塑料层200。在一些实施例中，可涂布大致上为液体的模塑料层200，并经由化学反应固化模塑料层200。在一些实施例，模塑料层200可为紫外光(ultraviolet，UV)固化或热固化聚合物的胶体，并利用紫外光或热将模塑料层200固化。
在一些实施例中，模塑料层200覆盖导电结构130及第一晶片150的非主动面(亦即，基底160的背表面)。之后，对模塑料层200进行薄化制程，直到露出导电结构130，如图1E所示。薄化制程可包括研磨(polishing)制程、磨削(grinding)制程、铣削(milling)制程或其他适用的制程。在一些实施例中，导电结构130的厚度小于第一晶片150的厚度，因此在薄化模塑料层200的期间，第一晶片150也被薄化，以露出导电结构130。例如，从基底160的背表面薄化，减少基底160的厚度。
在一些其他实施例中，可能在接合第一晶片150之前先对基底160进行薄化制程，使得第一晶片150的厚度小于或大致上相同于导电结构130的厚度，结果在薄化模塑料层200的期间，第一晶片150并未被薄化。根据本发明一些实施例，在薄化模塑料层200的期间，同时对基底160进行薄化的步骤，能够简化制程及降低制造成本。
请参照图1F，在模塑料层200及第一晶片150的非主动面上形成一绝缘层210。在一些实施例中，绝缘层210可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。在一些实施例中，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，形成绝缘层210。接着，可通过光刻制程及蚀刻制程，在绝缘层210内形成多个开口215，开口215露出被模塑料层200环绕的导电结构130。
在一些实施例中，在进行上述薄化制程之后，第一晶片150、导电结构130及模塑料层200大致上共平面，且绝缘层210直接接触第一晶片150的非主动面、导电结构130及模塑料层200。在一些其他实施例中，可能有一部分模塑料层200夹置于第一晶片150的非主动面与绝缘层210之间，将第一晶片150与绝缘层210分隔。
请参照图1G，在绝缘层210上形成图案化的一重布线层220(也称为第二重布线层)。重布线层220填充绝缘层210的开口215，且经由开口215电性及物理性连接被模塑料层200环绕的导电结构130。在一些实施例中，一部分的重布线层220重叠第一晶片150的感测区165。在一些实施例中，一部分的绝缘层210夹置于第一晶片150的非主动面与重布线层220之间。
在一些实施例中，重布线层220可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。在一些实施例中，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、光刻制程及蚀刻制程，形成图案化的重布线层220。
请参照图1H，可通过沉积制程，在绝缘层210上形成一保护层230，以覆盖重布线层220。在一些实施例中，保护层230与绝缘层210直接接触。在一些实施例中，保护层230可包括环氧树脂、绿漆、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，可通过光刻制程及蚀刻制程，在保护层230内形成多个开口235及多个开口236，以露出一部分的重布线层220。在一些实施例中，如图1H所示，开口235重叠于模塑料层200，而开口236重叠于第一晶片150。在一些实施例中，开口235的尺寸(例如，宽度)大于开口236的尺寸。
请参照图1I，在从开口235露出的重布线层220上形成多个导电结构240，且导电结构240填满开口235。导电结构240的底部被保护层230环绕，而导电结构240的顶部位于保护层230上方。导电结构240经由重布线层220、导电结构130、重布线层120及第一接合结构140电性连接到第一晶片150。
在一些实施例中，导电结构240为焊球、导电凸块、导电柱或其他适合的导电结构。在一些实施例中，导电结构240可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。在一些实施例中，导电结构240及第一接合结构140可包括相同的材料，例如锡或其他适合的导电材料。在一些实施例中，可通过植球制程、网版印刷制程、电镀制程或其他适合的制程，在重布线层220上形成导电结构240，并进行回焊制程。
在形成导电结构240之后，将一第二晶片250接合于从开口236露出的重布线层220上，使得第二晶片250堆叠在第一晶片150的非主动面上，如图1I所示。在一些实施例中，第二晶片250重叠于第一晶片150的感测区165。在一些实施例中，第二晶片250的厚度(或高度)小于导电结构240的厚度(或高度)，以利于导电结构240后续接合于其他元件(例如，电路板)上。
在一些实施例中，第一晶片150及第二晶片250皆为已知良好的晶片(known gooddie)。在一些实施例中，第一晶片150及第二晶片250具有不同的功能。在一些实施例中，第二晶片250不具有感测的功能，例如第二晶片250可包括特定应用集成电路(application-specific integrated circuit，ASIC)、信号处理器(signal processor)或其他电子部件。
在一些实施例中，第二晶片250包括一基底260、一绝缘层270及多个导电垫280，如图1I所示。绝缘层270及导电垫280邻近于第二晶片250的主动面，而第二晶片250的非主动面大致上等同于基底260的背表面。在一些实施例中，第二晶片250不包括感测区及光学部件。
在一些实施例中，基底260可为一硅基底或其他半导体基底。绝缘层270位于基底260的前表面上。一般而言，绝缘层270可由层间介电层、金属间介电层及覆盖的钝化层组成。为简化图式，此处仅绘示出单层绝缘层270。在一些实施例中，绝缘层270可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
导电垫280位于绝缘层270内，且绝缘层270内的钝化层具有露出导电垫280的开口。在一些实施例中，导电垫280可为单层导电层或具有多层的导电层结构。在一些实施例中，导电垫280电性连接至位于绝缘层170内的内连线结构(未绘示)。
如图1I所示，可通过多个第二接合结构290将第二晶片250接合于重布线层220上，第二接合结构290填满保护层230的开口236。在一些实施例中，第二接合结构290及导电结构240都位于重布线层220上，因此第二接合结构290及导电结构240位于相同层位。第二接合结构290可以包括导电凸块或其他适合的接合结构。在一些实施例中，第二接合结构290可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。在一些实施例中，可通过网版印刷制程、电镀制程或其他适合的制程，形成第二接合结构290，并进行回焊制程。
请参照图1J，在一些实施例中，沿着切割道切割保护层230、绝缘层210、模塑料层200、间隔层110及盖板100，以形成多个独立的晶片封装体300A。举例来说，可使用切割刀具或激光进行切割制程，其中使用激光切割制程可以避免上下膜层发生位移。在一些其他实施例中，第一晶片150是电容式指纹感测晶片，且盖板100仅为暂时性载板，因此形成的晶片封装体300A不包括盖板100及间隔层110。
在一些实施例中，每一个晶片封装体300A包括不同功能的一个第一晶片150及一个第二晶片250，如图1J所示。然而，本发明实施例可以具有许多变化。在一些其他实施例中，多个第二晶片250堆叠于一个第一晶片150上。在一些其他实施例中，还有一个或一个以上的第三晶片255堆叠于一个第一晶片150上，其中第三晶片255的结构及设置方式可大致上相同或类似于第二晶片250的结构及设置方式。或者，第一晶片150、第二晶片250及第三晶片255可能各自具有不同的功能。
举例来说，图2是绘示出根据本发明一些实施例的晶片封装体的上视图。为了清楚说明及简化图式，图2仅绘示出盖板100、第一晶片150、感测区165、第二晶片250及第三晶片255。在一些实施例中，晶片封装体包括一个第一晶片150，多个第二晶片250及多个第三晶片255堆叠于一个第一晶片150上，且第二晶片250及第三晶片255与第一晶片150的感测区165局部重叠。
在某些情况下，由于具有感测功能的晶片的感测面不能受到遮蔽，因此可能采用硅通孔电极(through-silicon via，TSV)的技术形成堆叠晶片之间的电性导通路径。然而，硅通孔电极的技术涉及将硅基底接合在暂时性载板上，且对硅基底进行蚀刻制程，以在硅基底内形成露出导电结构的通孔。而且，硅通孔电极的技术也涉及在通孔内形成绝缘层，以将硅基底与后续形成的导电层电性隔离，且对绝缘层进行蚀刻制程，去除覆盖住导电结构的绝缘层，使得后续形成的导电层能够与露出的导电结构电性连接。之后，还需要移除暂时性载板。
根据本发明的上述实施例，可利用第一接合结构140、重布线层120、模塑料层200中的导电结构130、重布线层220及第二接合结构290，将第一晶片150及第二晶片250互相电性连接，而无需采用硅通孔电极的技术，特别是不需要对硅基底及通孔内的绝缘层进行蚀刻制程，也可以不需要接合暂时性载板及去除暂时性载板，因此能够简化制程步骤、减少制造时间且大幅降低制造成本。
第一晶片150与第二晶片250之间的电性导通路径是经由第一晶片150外侧的导电结构130，且导电结构130与第一晶片150之间具有厚度充足的模塑料层200，因此能够减少或避免导电结构130与第一晶片150之间发生漏电流的问题。而且，模塑料层200包覆第一晶片150，能够进一步增加晶片封装体300A的结构强度。如此一来，在对晶片封装体300A进行可靠度测试时，模塑料层200可保护第一晶片150。因此，晶片封装体300A具有提升的装置性能及可靠度。
再者，由于模塑料层200包覆第一晶片150，增加了结构强度，而不会产生破裂或其他结构上的问题，因此受到模塑料层200保护的第一晶片150的尺寸(例如，厚度)可以更进一步缩减。如此一来，晶片封装体300A能够具有更小的尺寸，后续接合的电路板及所形成的电子产品的尺寸也能够进一步缩小。换句话说，可通过模塑料层200控制第一晶片150的尺寸，使得晶片封装体300A的尺寸具有更高的设计弹性。
以下配合图3A至3J说明本发明一些实施例的晶片封装体及其制造方法。图3A至3J是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图，其中相同于图1A至1J中的部件使用相同的标号并省略其说明。
请参照图3A，提供如图1A所示的结构，也就是说，在盖板100上形成具有多个开口115的间隔层110。接着，通过与图1B相同或相似的步骤，在间隔层110上形成图案化的重布线层120，如图3B所示。然而，并未在图3B中的重布线层120上形成图1B中的导电结构130。
请参照图3C，提供一晶圆310。晶圆310包括基底160、感测区165、绝缘层170、导电垫180及光学部件190，且基底160为半导体晶圆，以利进行晶圆级制程。接着，将多个第二晶片250接合至晶圆310上，如图3C所示。在一些实施例中，第二晶片250为已知良好的晶片。具体而言，第二晶片250的非主动面朝向晶圆310的非主动面，且可通过一粘着层320将第二晶片250的非主动面贴附至晶圆310的非主动面上，因此图3C中的第二晶片250与晶圆310并无电性连接。在一些实施例中，在接合第二晶片250之前，可对晶圆310进行薄化制程，例如从晶圆310的非主动面薄化基底160，以减少基底160的厚度。
在接合第二晶片250之后，可沿着切割道切割晶圆310的基底160及绝缘层170，以形成多个独立的第一晶片150。每一个第一晶片150的非主动面上可堆叠一个或一个以上的第二晶片250，而第一晶片150与第二晶片250尚未电性连接。
请参照图3D，进行相同或相似于图1C的步骤，通过多个第一接合结构140，将堆叠的第二晶片250及第一晶片150接合于重布线层120上。在一些实施例中，第一接合结构140夹置于重布线层120与第一晶片150的导电垫180之间。在一些实施例中，第二晶片250的尺寸(例如，宽度)小于第一晶片150的尺寸，因此局部露出第一晶片150的非主动面，如图3D所示。
请参照图3E，进行相同或相似于图1D的步骤，在间隔层110及重布线层120上形成模塑料层200。在一些实施例中，模塑料层200环绕第一晶片150、粘着层320及第二晶片250。在一些实施例中，模塑料层200覆盖第二晶片250的主动面及邻近主动面的导电垫280。在一些实施例中，模塑料层200直接接触粘着层320及第一晶片150的非主动面。
请参照图3F，在模塑料层200内形成多个开口125(也称为第一开口)，开口125局部露出重布线层120。再者，在模塑料层200内形成局部露出第二晶片250的主动面的多个开口285(也称为第二开口)，使得导电垫280从开口285露出。在一些实施例中，开口125的尺寸(例如，深度)大于开口285的尺寸。在一些实施例中，对模塑料层200进行激光钻孔制程，以形成开口125及开口285。开口125及开口285可在不同的激光钻孔制程中形成，且形成开口125及开口285的先后顺序并无限定。
请参照图3G，在模塑料层200上形成图案化的重布线层220。重布线层220从模塑料层200上延伸到模塑料层200的开口125内，且经由开口125电性及物理性连接重布线层120。再者，重布线层220延伸到模塑料层200的开口285内，且经由开口285电性及物理性连接第二晶片250的导电垫280。在一些实施例中，重布线层220直接接触模塑料层200。
请参照图3H，进行相同或相似于图1H的步骤，在模塑料层200上形成保护层230，以覆盖重布线层220。在一些实施例中，没有绝缘层位于保护层230与模塑料层200之间，且保护层230与模塑料层200直接接触。
在一些实施例中，重布线层220及保护层230共同填满开口285。在一些实施例中，保护层230仅局部填入开口125，使得重布线层220及保护层230在开口125内围绕出一孔洞126。如此一来，后续制程中遭遇热循环(Thermal Cycle)时，孔洞126能够作为保护层230与重布线层220之间的缓冲，以降低由于热膨胀系数不匹配所引发不必要的应力，且防止外界温度或压力剧烈变化时保护层230会过度拉扯重布线层220，进而可避免重布线层220剥离甚至断路的问题。
接着，进行相同或相似于图1H的步骤，在保护层230内形成多个开口235，以露出一部分的重布线层220，如图3H所示。之后，进行相同或相似于图1I的步骤，在开口235内及露出的重布线层220上形成多个导电结构240，如图3I所示。导电结构240经由重布线层220、重布线层120及第一接合结构140电性连接到第一晶片150。
请参照图3J，进行相同或相似于图1J的步骤，沿着切割道切割保护层230、模塑料层200、间隔层110及盖板100，以形成多个独立的晶片封装体300B。在一些其他实施例中，第一晶片150是指纹感测晶片，且盖板100仅为暂时性载板，因此形成的晶片封装体300B可不包括盖板100及间隔层110。
晶片封装体300B类似于晶片封装体300A，每一个晶片封装体300B包括不同功能的一个第一晶片150及一个第二晶片250，如图3J所示。然而，本发明实施例可以具有许多变化，晶片封装体300B可包括不同功能的一个第一晶片150及多个第二晶片250。
图4A至4I绘示出根据本发明一些实施例的晶片封装体及其制造方法，其中图4A至4I是绘示出根据本发明的一些实施例的晶片封装体的制造方法的剖面示意图。其中，与图1A至1J或图3A至3J中相同的部件使用相同的标号并省略其说明。
请参照图4A，提供一盖板100。之后，在一些实施例中，在盖板100上形成图案化重布线层(RDL)120(其也称作第一重布线层)。之后，在一些实施例中，在重布线层120上形成第一接合结构140a。在一些实施例中，第一接合结构140a与重布线层120直接接触，并且重布线层120的一部分夹设于第一接合结构140a与盖板100之间。在一些实施例中，第一接合结构140a可相同或相似于图1B所示的导电结构130。举例来说，第一接合结构140a包括柱体、凸块或其他合适的导电结构。在一些实施例中，第一接合结构140a包括铜、铜合金、钛、钛合金，其组合或其他合适的材料。可使用相同或相似于形成图1B所示的导电结构130的方法在重布线层120上形成第一接合结构140a。
之后，在一些实施例中，使用相同或相似于图1A的步骤在盖板100上形成具有开口115的间隔层(或围堰)110，如图4B所示，使第一接合结构140a围绕间隔层110。如图4B所示的间隔层110未如图1B所示形成在重布线层120上。在一些实施例中，间隔层110与重布线层120位于相同的层位。
请参照图4C，通过第一接合结构140a将第一晶片150接合至重布线层120上，并通过间隔层110接合至盖板100上。在一些实施例中，第一晶片150使用相同或相似于图1C的步骤将第一晶片150接合至重布线层120及盖板100上。在将第一晶片150接合至重布线层120之后，在每个第一晶片150的主动表面与盖板100之间形成一空腔155，且空腔155被对应的第一晶片150下方的间隔层110所围绕。空腔155也对应于每个第一晶片150的感测区165，使得光学部件190位于对应的空腔155内且由盖板100保护。
请参照图4D，使用相同或相似于图1D的步骤在盖板100上形成模塑料层200。在一些实施例中，模塑料层200围绕重布线层120及第一晶片150。在一些实施例中，模塑料层200与间隔层110、重布线层120、第一接合结构140a及第一晶片150直接接触。在一些实施例中，模塑料层200覆盖每个第一晶片150的非主动表面(即，基底160的背表面)。
请参照图4E，通过相同或相似于图3F的步骤在模塑料层200内形成开口125，其中开口125局部露出重布线层120。之后，在一些实施例中，图案化的重布线层220(也称作第二重布线层)通过相同或相似于图3G所示的方式形成在模塑料层200上，如图4F所示。模塑料层200上的重布线层220延伸至模塑料层200的开口125内，并通过开口125电性连接及物理连接至重布线层120。在一些实施例中，重布线层220与模塑料层200直接接触。
请参照图4G，在模塑料层200上形成一保护层230，以覆盖重布线层220。接着，在保护层230内形成开口235及开口236，以露出部分的重布线层220。在一些实施例中，使用相同或相似于图1H的步骤形成保护层230与开口235及开口236。如图4G所示，从上视角度来看，开口235可与模塑料层200重叠，且开口236可与第一晶片150重叠。在一些实施例中，开口235的尺寸(例如，宽度)大于开口236的尺寸(例如，宽度)。在一些实施例中，在保护层230及模塑料层200之间没有绝缘层，且保护层230与模塑料层200直接接触。
在一些实施例中，保护层230局部地填入开口125，而形成孔洞126，每个开口125内的重布线层220及保护层230围绕孔洞126，如图4G所示。
请参照图4H，进行相同或相似于图1I的步骤，使得第二晶片250通过第二接合结构290(其完全填满开口236)接合至重布线层220，且导电结构240形成在开口235内露出的重布线层220上。
请参照图4I，使用相同或相似于图1J的步骤沿着切割道切割模塑料层200及盖板100，以形成多个独立的晶片封装体300C。在一些其他实施例中，第一晶片150为指纹感测晶片，且盖板100仅为暂时性载板。因此，形成的晶片封装体300C不包括盖板100及间隔层110。
晶片封装体300C相似于晶片封装体300A及300B，每一个晶片封装体300C包括不同功能的一个第一晶片150及一个第二晶片250，如图4I所示。然而，本发明实施例可以具有许多变化，晶片封装体300C可包括不同功能的一个第一晶片150及多个第二晶片250。
图5A至5H绘示出根据本发明一些实施例的晶片封装体及其制造方法，其中图5A至5H是绘示出根据本发明的一些实施例的晶片封装体的制造方法的剖面示意图。其中，与图1A至1J、图3A至3J、或图4A至4I中相同的部件使用相同的标号并省略其说明。
请参照图5A，提供如图4C所示的结构。亦即，在盖板100上形成具有第一接合结构140a位于上方的图案化重布线层(RDL)120(其也称作第一重布线层)、具有多个开口115的间隔层110。接着，第一晶片150通过第一接合结构140接合至重布线层120上，且通过间隔层110接合至盖板100上。
请参照图5B，使用相同或相似于图3D的步骤，通过一粘着层320将第二晶片250a对应地接合到第一晶片150上。如此一来，每个第二晶片250a的非主动表面面向对应的第一晶片150的非主动表面，因此第二晶片250a并未电性连接晶圆310。第二晶片250a相似于图3C所示的第二晶片250。具体地，第二晶片250a包括一基底260、一绝缘层270及多个导电垫280。不同于图3C所示的第二晶片250，第二晶片250a还包括形成在对应的导电垫280上的至少一个第二接合结构290。在一些实施例中，第二接合结构290相同或相似于第一接合结构140a。或者，第二接合结构290相同或相似于图1C所示的第一接合结构140。
一或多个第二晶片250a可堆叠在每个第一晶片150的非主动表面上，其中第一晶片150尚未电性连接至第二晶片250a。在一些实施例中，第二晶片250a的尺寸(例如，宽度)小于第一晶片150的尺寸(例如，宽度)，因此露出局部的第一晶片150的非主动表面。
请参照图5C，使用相同或相似于图3E的步骤在盖板100上形成一模塑料层200。在一些实施例中，模塑料层200围绕第一晶片150、粘着层320及第二晶片250a。在一些实施例中，模塑料层200覆盖第二晶片250a的主动表面及与主动表面相邻的多个导电垫280。在一些实施例中，模塑料层200与粘着层320及每个第一晶片150的非主动表面(即，基板160的背表面)直接接触。在一些实施例中，模塑料层200与间隔层110、重布线层120及第一接合结构140a直接接触。
请参照图5D，在模塑料层200上进行一薄化制程，直至露出第二接合结构290。薄化制程可包括研磨制程、磨削制程、铣削制程或其他适用的制程。之后，使用相同或相似于图3F的步骤在模塑料层200内形成多个开口125，其中开口125局部露出重布线层120。
之后，在一些实施例中，使用相同或相似于图3G的步骤在模塑料层200上形成一图案化的重布线层220，如图5E所示。模塑料层200上的重布线层220延伸至模塑料层200内的开口125中，并通过开口125电性连接及物理连接至重布线层120。在一些实施例中，重布线层220直接接触模塑料层200层及露出的第二接合结构290，使得重布线层220电性连接至第二晶片250。
请参照图5F，在模塑料层200上形成一保护层230，以覆盖重布线层220。接着，在保护层230内形成多个开口235，以露出多个部分的重布线层220。在一些实施例中，通过相同或相似于图1H的步骤形成保护层230及开口235。在一些实施例中，在保护层230与模塑料层200之间没有绝缘层，且保护层230直接接触模塑料层200。
在一些实施例中，保护层230局部填入开口125而形成孔洞126，孔洞126被每个开口125内的重布线层220及保护层230围绕，如图5F所示。之后，在一些实施例中，进行相同或相似于图1I的步骤，使得导电结构240形成在开口235内的露出的重布线层220上，如图5G所示。导电结构240通过重布线层220、重布线层120及第一接合结构140a电性连接至第一晶片150。
请参照图5H，通过相同或相似于图1J的步骤沿着切割道切割保护层230、模塑料层200及盖板100，以形成多个独立的晶片封装体300D。在一些其他实施例中，第一晶片150为指纹感测晶片，且盖板100仅为暂时性载板。因此，形成的晶片封装体300D不包括盖板100及间隔层110。
晶片封装体300D相似于晶片封装体300A、300B及300C，每一个晶片封装体300D包括不同功能的一个第一晶片150及一个第二晶片250，如图5H所示。然而，本发明实施例可以具有许多变化，晶片封装体300D可包括不同功能的一个第一晶片150及多个第二晶片250。
晶片封装体300B、300C及300D具有相同或类似于晶片封装体300A的优点。详细而言，可利用第一接合结构140、重布线层120、形成于模塑料层200中及模塑料层200上的重布线层220，将第一晶片150及第二晶片250互相电性连接，而无需采用硅通孔电极的技术，因此能够简化制程步骤、减少制造时间且大幅降低制造成本。
第一晶片150与第二晶片250之间的电性导通路径是经由第一晶片150外侧的重布线层220，且重布线层220与第一晶片150之间具有厚度充足的模塑料层200，因此能够减少或避免漏电流。
而且，模塑料层200包覆第一晶片150及第二晶片250，能够进一步增加晶片封装体300B或300D的结构强度。如此一来，在对晶片封装体300B进行可靠度测试时，模塑料层200可保护第一晶片150及第二晶片250。因此，晶片封装体300B具有提升的装置性能及可靠度。再者，由于通过模塑料层200包覆晶片封装体300B或300D内的第一晶片150及第二晶片250，增加了结构强度，因此不会发生破裂或其他结构性问题。因此，受到模塑料层200保护的第一晶片150及第二晶片250的尺寸(例如，厚度)可以更进一步缩减。如此一来，晶片封装体300B或300D能够具有更小的尺寸，后续接合的电路板及所形成的电子产品的尺寸也能够进一步缩小。换句话说，可通过模塑料层200控制第一晶片150及第二晶片250的尺寸，使得晶片封装体300B或300D的尺寸具有更高的设计弹性。
另外，本发明实施例的晶片封装体300A、晶片封装体300B、晶片封装体300C及晶片封装体300D皆能够根据实际需求封装不同功能的晶片，且晶片的数量并无限制，可以配合所需的晶片数量及晶片尺寸适当选择盖板100的尺寸，以利于进行晶圆级的封装制程，进而提升制造效率。
综上所述，本发明的各种实施例采用晶片堆叠的技术制作具有多功能且小尺寸的感测晶片封装体，并解决了采用硅通孔电极技术产生的问题，特别是能够简化制程及降低制造成本，更提升系统级封装的晶片封装体的装置性能及可靠度。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (39)

1.一种晶片封装体，包括：
第一重布线层；
第一接合结构，其中该第一接合结构位于该第一重布线层上；
第一晶片，其中该第一晶片包括邻近主动面的感测区及导电垫，且其中该第一晶片通过该第一接合结构接合于该第一重布线层上，且该第一接合结构位于该导电垫与该第一重布线层之间；
模塑料层，其中该模塑料层覆盖该第一重布线层且环绕该第一晶片；
第二重布线层，其中该第二重布线层位于该模塑料层及该第一晶片上，且该第二重布线层电性连接至该第一重布线层；以及
第二晶片，其中该第二晶片堆叠于该第一晶片的非主动面上，且该第二晶片通过该第二重布线层、该第一重布线层及该第一接合结构电性连接至该第一晶片。
2.根据权利要求1所述的晶片封装体，其中该第一晶片具有感测影像或生物特征的功能，且该第二晶片不具有感测的功能。
3.根据权利要求1所述的晶片封装体，还包括：
盖板，其中该盖板包括透光材料，且其中该第一晶片的该主动面朝向该盖板，且该第一重布线层及该第一接合结构位于该盖板与该第一晶片的该主动面之间。
4.根据权利要求3所述的晶片封装体，还包括：
间隔层，其中该间隔层位于该盖板与该第一重布线层之间，且该间隔层在该第一晶片的该主动面与该盖板之间围绕出对应于该感测区的空腔，且其中该第一晶片还包括位于该主动面的光学部件，且该光学部件对应于该空腔。
5.根据权利要求3所述的晶片封装体，还包括：
间隔层，其中该第一重布线层位于该间隔层与该第一接合结构之间，且该间隔层接触该盖板、该模塑料层及该第一重布线层。
6.根据权利要求3所述的晶片封装体，还包括：
间隔层，其中该间隔层位于该盖板上及该第一晶片下方，且被该第一接合结构围绕，该间隔层在该第一晶片的该主动面与该盖板之间围绕出对应于该感测区的空腔，且其中该第一晶片还包括位于该主动面的光学部件，且该光学部件对应于该空腔。
7.根据权利要求1所述的晶片封装体，还包括：
保护层，其中该保护层位于该模塑料层及该第一晶片的该非主动面上，且该保护层覆盖该第二重布线层；以及
多个导电结构，其中该导电结构位于该第二重布线层上，且该保护层局部环绕该导电结构。
8.根据权利要求7所述的晶片封装体，还包括：
第二接合结构，其中该第二晶片通过该第二接合结构接合于该第二重布线层上，且其中该保护层环绕该第二接合结构及该导电结构。
9.根据权利要求8所述的晶片封装体，其中该第二接合结构与该导电结构位于相同层位，且其中该第二晶片的厚度小于该导电结构的厚度。
10.根据权利要求7所述的晶片封装体，其中该第二晶片包括第二接合结构，其中该第二晶片通过该第二接合结构电性连接于该第二重布线层上，且其中该模塑料层围绕该第二接合结构，而该保护层围绕该导电结构。
11.根据权利要求7所述的晶片封装体，其中该模塑料层环绕该第一晶片及该第二晶片，且其中该保护层及该导电结构位于该模塑料层、该第一晶片及该第二晶片上。
12.根据权利要求7所述的晶片封装体，其中该保护层及该第二重布线层从该模塑料层上延伸至该模塑料层中，且其中该保护层及该第二重布线层在该模塑料层内围绕出孔洞。
13.根据权利要求1所述的晶片封装体，其中该第二晶片的宽度小于该第一晶片的宽度。
14.根据权利要求1所述的晶片封装体，还包括：
导电结构，其中该导电结构位于该第一重布线层上且被该模塑料层环绕，且其中位于该模塑料层上的该第二重布线层通过该导电结构电性连接至被该模塑料层覆盖的该第一重布线层，且该导电结构与该第一接合结构包括不同的材料。
15.根据权利要求14所述的晶片封装体，还包括：
绝缘层，其中该绝缘层位于该模塑料层上及该第一晶片与该第二晶片之间，且其中该绝缘层夹置于该第一晶片的该非主动面与该第二重布线层之间。
16.根据权利要求1所述的晶片封装体，还包括：
粘着层，其中该粘着层将该第二晶片贴附于该第一晶片的该非主动面，且其中该模塑料层还环绕该第二晶片及该粘着层。
17.根据权利要求1所述的晶片封装体，还包括：
第三晶片，其中该第二晶片及该第三晶片堆叠于该第一晶片的该非主动面上且重叠该第一晶片的该感测区。
18.一种晶片封装体的制造方法，包括：
形成第一重布线层；
在该第一重布线层上形成第一接合结构；
通过该第一接合结构将第一晶片接合于该第一重布线层上，其中该第一晶片包括邻近主动面的感测区及导电垫，且该第一接合结构位于该导电垫与该第一重布线层之间；
形成模塑料层，以覆盖该第一重布线层且环绕该第一晶片；
在该模塑料层及该第一晶片上形成第二重布线层，其中该第二重布线层电性连接至该第一重布线层；以及
堆叠第二晶片，其中该第二晶片位于该第一晶片的非主动面上，且该第二晶片通过该第二重布线层、该第一重布线层及该第一接合结构电性连接至该第一晶片。
19.根据权利要求18所述的晶片封装体的制造方法，还包括：
提供盖板；以及
在该盖板上形成间隔层，其中在接合该第一晶片之前，在该间隔层上形成该第一重布线层。
20.根据权利要求19所述的晶片封装体的制造方法，其中在接合该第一晶片之前，在该间隔层上形成该第一重布线层。
21.根据权利要求19所述的晶片封装体的制造方法，其中该第一接合结构围绕该间隔层。
22.根据权利要求19所述的晶片封装体的制造方法，还包括：
在该模塑料层及该第一晶片的该非主动面上形成保护层，以覆盖该第二重布线层，其中该保护层具有露出该第二重布线层的多个开口；
在该保护层的该开口内形成多个导电结构，其中该导电结构电性连接至该第二重布线层；以及
切割该保护层、该模塑料层、该间隔层及该盖板，以形成该晶片封装体。
23.根据权利要求22所述的晶片封装体的制造方法，其中在形成该导电结构之后，进行回焊制程，以通过第二接合结构将该第二晶片接合于该第二重布线层上。
24.根据权利要求22所述的晶片封装体的制造方法，其中该第二晶片包括第二接合结构，其中通过该第二接合结构将该第二晶片电性连接于该第二重布线层。
25.根据权利要求24所述的晶片封装体的制造方法，还包括：
在该模塑料层内形成露出该第一重布线层的第一开口。
26.根据权利要求25所述的晶片封装体的制造方法，其中对该模塑料层进行激光钻孔制程，以形成该第一开口。
27.根据权利要求25所述的晶片封装体的制造方法，其中该第二重布线层接触该模塑料层及该第一重布线层。
28.根据权利要求25所述的晶片封装体的制造方法，还包括：
在该模塑料层、该第二晶片及该第一晶片上形成保护层，以覆盖该第二重布线层，其中该保护层从该模塑料层上延伸至该第一开口，且该保护层与该第二重布线层在该第一开口内围绕出孔洞。
29.根据权利要求18所述的晶片封装体的制造方法，其中在形成该模塑料层之前，对该第一接合结构进行回焊制程，将该第一晶片接合于该第一重布线层上。
30.根据权利要求18所述的晶片封装体的制造方法，还包括：
在接合该第一晶片及形成该模塑料层之前，在该第一重布线层上形成导电结构，使得在接合该第一晶片及形成该模塑料层之后，该模塑料层环绕该导电结构及该第一晶片；以及
薄化该模塑料层，直到露出该导电结构。
31.根据权利要求30所述的晶片封装体的制造方法，其中该导电结构的厚度小于该第一晶片的厚度且大于该第一接合结构的厚度，且其中在薄化该模塑料层的期间，从该非主动面薄化该第一晶片。
32.根据权利要求30所述的晶片封装体，还包括：
在堆叠该第二晶片之前，在该模塑料层及该第一晶片的该非主动面上形成绝缘层，其中该绝缘层具有露出该导电结构的开口，且其中该第二重布线层形成于该绝缘层上且延伸至该开口内，以通过该导电结构电性连接至该第一重布线层。
33.根据权利要求18所述的晶片封装体的制造方法，还包括：
提供晶圆，其中该第二晶片堆叠于该晶圆上；以及
将该晶圆切割成该第一晶片，其中在形成该模塑料层之前，该第二晶片堆叠于该第一晶片的该非主动面上。
34.根据权利要求33所述的晶片封装体的制造方法，其中该第二晶片通过粘着层贴附于该晶圆上，且其中该模塑料层环绕该粘着层、该第一晶片及该第二晶片。
35.根据权利要求34所述的晶片封装体的制造方法，还包括：
在该模塑料层内形成露出该第一重布线层的第一开口；以及
在该模塑料层内形成露出该第二晶片的第二开口，其中该第二重布线层从该模塑料层上延伸至该第一开口及该第二开口内，以电性连接该第一重布线层及该第二晶片。
36.根据权利要求35所述的晶片封装体的制造方法，其中对该模塑料层进行激光钻孔制程，以形成该第一开口及该第二开口。
37.根据权利要求35所述的晶片封装体的制造方法，其中该第二重布线层接触该模塑料层及该第一重布线层。
38.根据权利要求35所述的晶片封装体的制造方法，还包括：
在该模塑料层、该第二晶片及该第一晶片上形成保护层，以覆盖该第二重布线层，其中该保护层从该模塑料层上延伸至该第一开口及该第二开口内，且该保护层与该第二重布线层在该第一开口内围绕出孔洞，且其中该保护层与该第二重布线层共同填满该第二开口。
39.根据权利要求33所述的晶片封装体的制造方法，其中该第二晶片的非主动面朝向该第一晶片的该非主动面，且其中该模塑料层覆盖该第二晶片的主动面。
CN201910407970.6A 2017-05-18 2019-05-15 晶片封装体及其制造方法 Active CN110491859B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762508028P 2017-05-18 2017-05-18
US15/980,577 2018-05-15
US15/980,577 US10446504B2 (en) 2017-05-18 2018-05-15 Chip package and method for forming the same

Publications (2)

Publication Number Publication Date
CN110491859A true CN110491859A (zh) 2019-11-22
CN110491859B CN110491859B (zh) 2021-05-25

Family

ID=64272114

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910407970.6A Active CN110491859B (zh) 2017-05-18 2019-05-15 晶片封装体及其制造方法

Country Status (3)

Country Link
US (1) US10446504B2 (zh)
CN (1) CN110491859B (zh)
TW (1) TWI700753B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113629020A (zh) * 2021-06-25 2021-11-09 北京大学 一种毫米波封装结构及其制备方法

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10644046B2 (en) * 2017-04-07 2020-05-05 Samsung Electronics Co., Ltd. Fan-out sensor package and optical fingerprint sensor module including the same
US11309296B2 (en) * 2017-09-26 2022-04-19 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
CN109698208B (zh) * 2017-10-20 2023-06-30 新加坡有限公司 图像传感器的封装方法、图像传感器封装结构和镜头模组
JP2020047775A (ja) * 2018-09-19 2020-03-26 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法および半導体装置
CN109345963B (zh) * 2018-10-12 2020-12-18 芯光科技新加坡有限公司 一种显示装置及其封装方法
US11610935B2 (en) 2019-03-29 2023-03-21 Lumileds Llc Fan-out light-emitting diode (LED) device substrate with embedded backplane, lighting system and method of manufacture
EP3719841B1 (en) * 2019-04-01 2022-02-16 Detection Technology Oy Radiation sensor element and method
KR102767585B1 (ko) * 2019-07-24 2025-02-17 삼성전자주식회사 이미지 센서 칩을 포함하는 반도체 패키지 및 이의 제조 방법
CN110729255A (zh) * 2019-08-08 2020-01-24 厦门云天半导体科技有限公司 一种键合墙体扇出器件的三维封装结构和方法
KR102733567B1 (ko) * 2019-08-28 2024-11-26 삼성전자주식회사 반도체 패키지
US20220293837A1 (en) * 2019-08-29 2022-09-15 Osram Opto Semiconductors Gmbh Optoelectronic device with light emitter and detector and method for manufacturing an optoelectronic device
CN112574668A (zh) * 2019-09-27 2021-03-30 台湾积体电路制造股份有限公司 用于牺牲膜的组合物
US11798857B2 (en) * 2019-09-27 2023-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Composition for sacrificial film, package, manufacturing method of package
US11373967B2 (en) * 2019-11-14 2022-06-28 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for packaging the same
JP7615142B2 (ja) * 2019-11-19 2025-01-16 ルミレッズ リミテッド ライアビリティ カンパニー 発光ダイオードデバイスおよび照明システムのためのファンアウト構造
US11156346B2 (en) 2019-11-19 2021-10-26 Lumileds Llc Fan out structure for light-emitting diode (LED) device and lighting system
WO2021102097A1 (en) * 2019-11-19 2021-05-27 Lumileds Llc Fan out structure for light-emitting diode (led) device and lighting system
US11777066B2 (en) 2019-12-27 2023-10-03 Lumileds Llc Flipchip interconnected light-emitting diode package assembly
US11664347B2 (en) 2020-01-07 2023-05-30 Lumileds Llc Ceramic carrier and build up carrier for light-emitting diode (LED) array
US11476217B2 (en) 2020-03-10 2022-10-18 Lumileds Llc Method of manufacturing an augmented LED array assembly
US12113022B2 (en) * 2020-05-26 2024-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method of semiconductor package
CN111883438B (zh) * 2020-07-03 2022-09-30 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
TWI788903B (zh) * 2020-08-06 2023-01-01 力成科技股份有限公司 封裝結構及其製造方法
US11990494B2 (en) * 2020-08-06 2024-05-21 Powertech Technology Inc. Package structure and manufacturing method thereof
KR20220021238A (ko) * 2020-08-13 2022-02-22 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR20220070766A (ko) 2020-11-23 2022-05-31 삼성전자주식회사 글래스 기판을 포함하는 이미지 센서 패키지
TWI782817B (zh) * 2021-03-16 2022-11-01 日商鎧俠股份有限公司 半導體封裝及半導體裝置
CN113675101B (zh) * 2021-10-20 2021-12-21 深圳新声半导体有限公司 用于芯片封装的方法和芯片颗粒
TWI782857B (zh) * 2022-01-18 2022-11-01 勝麗國際股份有限公司 感測器封裝結構
KR20250023741A (ko) * 2023-08-10 2025-02-18 주식회사 글로벌테크놀로지 디스플레이 일체형 구동 패키지 및 이의 제조 방법
KR102736165B1 (ko) * 2023-12-04 2024-11-28 진성호 필라범프를 포함하는 이미지센서 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050001331A1 (en) * 2003-07-03 2005-01-06 Toshiyuki Kojima Module with a built-in semiconductor and method for producing the same
US20130221452A1 (en) * 2011-09-15 2013-08-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus
CN107146795A (zh) * 2016-03-01 2017-09-08 精材科技股份有限公司 晶片封装体及其制造方法
US20170271248A1 (en) * 2016-03-21 2017-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package and manufacturing process thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140264808A1 (en) * 2013-03-15 2014-09-18 Andreas Wolter Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
US9691708B1 (en) * 2016-07-20 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050001331A1 (en) * 2003-07-03 2005-01-06 Toshiyuki Kojima Module with a built-in semiconductor and method for producing the same
US20130221452A1 (en) * 2011-09-15 2013-08-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus
CN107146795A (zh) * 2016-03-01 2017-09-08 精材科技股份有限公司 晶片封装体及其制造方法
US20170271248A1 (en) * 2016-03-21 2017-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package and manufacturing process thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113629020A (zh) * 2021-06-25 2021-11-09 北京大学 一种毫米波封装结构及其制备方法
CN113629020B (zh) * 2021-06-25 2023-09-19 北京大学 一种毫米波封装结构及其制备方法

Also Published As

Publication number Publication date
TWI700753B (zh) 2020-08-01
CN110491859B (zh) 2021-05-25
US10446504B2 (en) 2019-10-15
US20180337142A1 (en) 2018-11-22
TW201947679A (zh) 2019-12-16

Similar Documents

Publication Publication Date Title
TWI700753B (zh) 晶片封裝體及其製造方法
US10056419B2 (en) Chip package having chip connected to sensing device with redistribution layer in insulator layer
US10157875B2 (en) Chip package and method for forming the same
CN104681516B (zh) 晶片封装体及其制造方法
CN107644847B (zh) 半导体封装与其制造方法
CN104733422B (zh) 晶片封装体及其制造方法
TWI529892B (zh) 晶片封裝體及其製造方法
US20170278769A1 (en) Chip package and method for forming the same
US9997473B2 (en) Chip package and method for forming the same
US11309296B2 (en) Semiconductor package and manufacturing method thereof
CN110943052B (zh) 晶片封装体及其制造方法
CN105720040B (zh) 晶片封装体及其制造方法
US20170117242A1 (en) Chip package and method for forming the same
TWI632665B (zh) 晶片封裝體之製造方法
CN105097790B (zh) 晶片封装体及其制造方法
TWI845129B (zh) 晶片封裝體及其製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant