CN113675101B - 用于芯片封装的方法和芯片颗粒 - Google Patents
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000002245 particle Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 166
- 239000004033 plastic Substances 0.000 claims abstract description 106
- 238000005520 cutting process Methods 0.000 claims abstract description 17
- 238000003466 welding Methods 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 238000000465 moulding Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 35
- 239000010408 film Substances 0.000 description 25
- 238000005538 encapsulation Methods 0.000 description 13
- 239000008187 granular material Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002985 plastic film Substances 0.000 description 2
- 229920006255 plastic film Polymers 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/561—Batch processing
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/10—Mounting in enclosures
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
-
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L23/66—High-frequency adaptations
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- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1078—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a foil covering the non-active sides of the SAW device
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- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
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Abstract
本申请涉及芯片封装技术领域,公开一种用于芯片封装的方法,包括:提供滤波器晶圆和若干个待封装基板;各待封装基板上设置有多个第一焊盘;将各待封装基板倒装焊接在滤波器晶圆上;对各待封装基板进行塑封,在各待封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆形成塑封结构;各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔;使塑封层暴露出各第一焊盘;将塑封结构切割成若干个芯片颗粒。这样,在对滤波器晶圆完成封装的同时,也完成了滤波器封装,不需要单独对滤波器晶圆进行封装,再进行滤波器封装,能够使得芯片颗粒的尺寸小型化。本申请还公开一种芯片颗粒。
Description
技术领域
本申请涉及芯片封装技术领域,例如涉及一种用于芯片封装的方法和芯片颗粒。
背景技术
目前,传统的滤波器封装通常是利用双层有机薄膜等盖体工艺形成滤波器所必须的空腔结构,并设置倒装焊接凸点以完成晶圆级封装。切割完成封装的滤波器晶圆,获得单颗芯片,再将单颗芯片倒装焊接到封装基板上,然后进行塑封、切割以获得芯片颗粒。该方法将封装完成的滤波器晶圆倒装焊接在基本上,不利于芯片颗粒的尺寸小型化。
发明内容
为了对披露的实施例的一些方面有基本的理解,下面给出了简单的概括。所述概括不是泛泛评述,也不是要确定关键/重要组成元素或描绘这些实施例的保护范围,而是作为后面的详细说明的序言。
本发明实施例提供一种用于芯片封装的方法和芯片颗粒,以便于芯片颗粒的尺寸小型化。
在一些实施例中,一种用于芯片封装的方法,包括:提供滤波器晶圆和若干个待封装基板;各所述待封装基板上设置有多个第一焊盘;将各所述待封装基板倒装焊接在所述滤波器晶圆上;对各所述待封装基板进行塑封,在各所述待封装基板上形成塑封层,各所述待封装基板、各所述待封装基板对应的塑封层和所述滤波器晶圆形成塑封结构;各所述待封装基板、各所述待封装基板对应的塑封层和所述滤波器晶圆分别围合形成有空腔;使所述塑封层暴露出各所述第一焊盘;将所述塑封结构切割成若干个芯片颗粒。
在一些实施例中,一种芯片颗粒,所述芯片颗粒通过上述的用于芯片封装的方法制得。
本发明实施例提供一种用于芯片封装的方法和芯片颗粒,可以实现以下技术效果:通过将各待封装基板倒装焊接在滤波器晶圆上;对各待封装基板进行塑封,在各待封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆形成塑封结构;各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔;使塑封层暴露出各第一焊盘;将塑封结构切割成若干个芯片颗粒。这样,通过将待封装基板倒装焊接在未进行封装的滤波器晶圆上,在各封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔,从而在对滤波器晶圆完成封装的同时,也完成了滤波器封装,不需要单独对滤波器晶圆进行封装,再进行滤波器封装,能够使得芯片颗粒的尺寸小型化,同时降低制造芯片颗粒的成本。
以上的总体描述和下文中的描述仅是示例性和解释性的,不用于限制本申请。
附图说明
一个或多个实施例通过与之对应的附图进行示例性说明,这些示例性说明和附图并不构成对实施例的限定,附图中具有相同参考数字标号的元件示为类似的元件,附图不构成比例限制,并且其中:
图1是本发明实施例提供的一个用于芯片封装的方法的示意图;
图2是本发明实施例提供的一个待切割基板的结构示意图;
图3是本发明实施例提供的一个在待切割基板上设置支撑层后的结构示意图;
图4是本发明实施例提供的一个在待切割基板上设置焊接凸点后的结构示意图;
图5是本发明实施例提供的一个待封装基板的结构示意图;
图6是本发明实施例提供的一个滤波器晶圆的结构示意图;
图7是本发明实施例提供的一个将各待封装基板倒装焊接在滤波器晶圆后的结构示意图;
图8是本发明实施例提供的一个在各待封装基板上形成第一有机薄膜的结构示意图;
图9是本发明实施例提供的一个在各待封装基板上形成第二有机薄膜结构示意图;
图10是本发明实施例提供的一个对塑封层和支撑层减薄后的结构示意图;
图11是本发明实施例提供的一个对滤波器晶圆减薄后的结构示意图;
图12是本发明实施例提供的一个芯片颗粒的结构示意图;
图13是本发明实施例提供的一个在第一焊盘设置第二焊锡凸点后的结构示意图;
图14是本发明实施例提供的另一个对滤波器晶圆减薄后的结构示意图;
图15是本发明实施例提供的另一个芯片颗粒的结构示意图;
图16是本发明实施例提供的另一个在各待封装基板上形成第一有机薄膜的结构示意图;
图17是本发明实施例提供的另一个对塑封层减薄后的结构示意图;
图18是本发明实施例提供的另一个对滤波器晶圆减薄后的结构示意图;
图19是本发明实施例提供的另一个芯片颗粒的结构示意图;
图20是本发明实施例提供的另一个在第一焊盘设置第二焊锡凸点后的结构示意图;
图21是本发明实施例提供的另一个对滤波器晶圆减薄后的结构示意图;
图22是本发明实施例提供的另一个芯片颗粒的结构示意图;
图23是本发明实施例提供的另一个用于芯片封装的方法的示意图;
图24是本发明实施例提供的另一个用于芯片封装的方法的示意图。
附图标记:
100:待切割基板;110:第一焊盘;120:第二焊盘;130:支撑层;140:第一焊接凸点;150:待封装晶圆衬底;160:第三焊盘;170:第一有机薄膜;180:第二有机薄膜;190:第二焊接凸点。
具体实施方式
为了能够更加详尽地了解本发明实施例的特点与技术内容,下面结合附图对本发明实施例的实现进行详细阐述,所附附图仅供参考说明之用,并非用来限定本发明实施例。在以下的技术描述中,为方便解释起见,通过多个细节以提供对所披露实施例的充分理解。然而,在没有这些细节的情况下,一个或多个实施例仍然可以实施。在其它情况下,为简化附图,熟知的结构和装置可以简化展示。
本发明实施例的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换,以便这里描述的本发明实施例的实施例。此外,术语“包括”和“具有”以及他们的任何变形,意图在于覆盖不排他的包含。
本发明实施例中,术语“上”、“下”、“内”、“中”、“外”、“前”、“后”等指示的方位或位置关系为基于附图所示的方位或位置关系。这些术语主要是为了更好地描述本发明实施例及其实施例,并非用于限定所指示的装置、元件或组成部分必须具有特定方位,或以特定方位进行构造和操作。并且,上述部分术语除了可以用于表示方位或位置关系以外,还可能用于表示其他含义,例如术语“上”在某些情况下也可能用于表示某种依附关系或连接关系。对于本领域普通技术人员而言,可以根据具体情况理解这些术语在本发明实施例中的具体含义。
另外,术语“设置”、“连接”、“固定”应做广义理解。例如,“连接”可以是固定连接,可拆卸连接,或整体式构造;可以是机械连接,或电连接;可以是直接相连,或者是通过中间媒介间接相连,又或者是两个装置、元件或组成部分之间内部的连通。对于本领域普通技术人员而言,可以根据具体情况理解上述术语在本发明实施例中的具体含义。
除非另有说明,术语“多个”表示两个或两个以上。
本发明实施例中,字符“/”表示前后对象是一种“或”的关系。例如,A/B表示:A或B。
术语“和/或”是一种描述对象的关联关系,表示可以存在三种关系。例如,A和/或B,表示:A或B,或,A和B这三种关系。
需要说明的是,在不冲突的情况下,本发明实施例中的实施例及实施例中的特征可以相互组合。
结合图1所示,本发明实施例提供一种用于芯片封装的方法,包括:
步骤S101,提供滤波器晶圆和若干个待封装基板;各待封装基板上设置有多个第一焊盘;
步骤S102,将各待封装基板倒装焊接在滤波器晶圆上;
步骤S103,对各待封装基板进行塑封,在各待封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆形成塑封结构;各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔;
步骤S104,使塑封层暴露出各第一焊盘;
步骤S105,将塑封结构切割成若干个芯片颗粒。
采用本发明实施例提供的用于芯片封装的方法,通过将各待封装基板倒装焊接在滤波器晶圆上;对各待封装基板进行塑封,在各待封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆形成塑封结构;各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔;使塑封层暴露出各第一焊盘;将塑封结构切割成若干个芯片颗粒。这样,通过将待封装基板倒装焊接在未进行封装的滤波器晶圆上,在各封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔,从而在对滤波器晶圆完成封装的同时,也完成了滤波器封装,不需要单独对滤波器晶圆进行封装,再进行滤波器封装,能够使得芯片颗粒的尺寸小型化,同时降低制造芯片颗粒的成本。
可选地,芯片颗粒具有滤波器功能。
结合图2至图4所示,可选地,若干个待封装基板通过以下方式获取:提供待切割基板100,待切割基板100上设置有多个第一焊盘110,待切割基板远离第一焊盘110的一侧设置有多个第二焊盘120;在各第二焊盘120上分别设置第一焊接凸点140;对待切割基板进行切割获得若干个待封装基板,各待封装基板分别设置有多个第一焊盘和多个带有第一焊接凸点的第二焊盘。
在一些实施例中,待切割基板中设置有多个待切割芯片,第一焊盘是待切割基板上的客户端焊盘,第二焊盘是FC(Flip Chip,倒装芯片)封装焊盘。
可选地,第一焊接凸点由能够用于倒装焊接的材料制成,例如:焊锡球、铜柱、金凸块和导电胶中的一种或多种。
在一些实施例中,待切割基板为PCB(Printed Circuit Board,印制线路板)基板或陶瓷基板。
可选地,在提供待切割基板后,还包括:在待切割基板设置第一焊盘110的一侧施加支撑层130,支撑层130覆盖各第一焊盘110。
这样,在待切割基板的强度不足以进行后续封装工艺的情况下,施加支撑层能够支撑待切割基板进行后续工艺。
可选地,支撑层由PP介质或陶瓷材料制成。
在一些实施例中,在待切割基板设置第一焊盘的一侧施加有支撑层的情况下,对待切割基板进行切割获得若干个待封装基板,如图5所示,图5为待封装基板的结构示意图。
在一些实施例中,如图6为滤波器晶圆的结构示意图,滤波器晶圆包括多个待封装芯片、包裹多个待封装芯片的待封装晶圆衬底150、用于与待封装基板的第二焊盘进行连接的第三焊盘160。
可选地,第一焊盘、第二焊盘和第三焊盘均由能够导电的材质制成,例如,金属。
可选地,倒装焊接的方法为焊锡回流焊、金属超声焊接或导电胶粘接。
在一些实施例中,结合图7所示,将各待封装基板倒装焊接在滤波器晶圆上后,各待封装基板的各第二焊盘120与滤波器晶圆的各第三焊盘160分别通过各第一焊接凸点140进行连接。
可选地,对各待封装基板进行塑封,在各待封装基板上形成塑封层,包括:对各待封装基板施加第一有机薄膜,由第一有机薄膜作为塑封层。
结合图8和图9所示,可选地,对各待封装基板进行塑封,在各待封装基板上形成塑封层,包括:对各待封装基板施加第一有机薄膜170,在所述第一有机薄膜远离所述待封装基板的一侧施加第二有机薄膜180,由第一有机薄膜170和第二有机薄膜180构成塑封层。
这样,通常在真空环境下贴膜到晶圆表面,使得有机薄膜能很好地沿着焊接在滤波器晶圆上的待封装基板的侧壁将待封装基板包裹,因而能够很好的由待封装基板、待封装基板对应的塑封层和滤波器晶圆形成空腔。
可选地,第一有机薄膜由Dry Film干膜或塑封薄膜制成。
可选地,第二有机薄膜由Dry Film干膜或塑封薄膜制成。
可选地,第一有机薄膜与第二有机薄膜的材质可以相同,也可以不相同。
可选地,使塑封层暴露出各第一焊盘,包括:减薄塑封层,使塑封层暴露出第一焊盘。
可选地,使塑封层暴露出各第一焊盘,包括:减薄塑封层和支撑层,使塑封层暴露出第一焊盘110。如图10所示,图10为减薄塑封层和支撑层后的结构示意图。
可选地,其特征在于,使塑封层暴露出各第一焊盘后,还包括:将滤波器晶圆减薄至预设厚度。即,将滤波器晶圆的待封装晶圆衬底150减薄至预设厚度,如图11所示,图11为将滤波器晶圆减薄至预设厚度后的结构示意图。
在一些实施例中,通过Grinding研磨工艺减薄塑封层和支撑层,通过Grinding研磨工艺和/或化学腐蚀工艺将滤波器晶圆减薄至预设厚度。
在一些实施例中,将塑封结构切割成若干个芯片颗粒,如图12所示,图12为芯片颗粒的结构示意图。
可选地,使塑封层暴露出各第一焊盘后,还包括:在各第一焊盘上分别设置第二焊接凸点。
在一些实施例中,使塑封层暴露出各第一焊盘后,在各第一焊盘110上分别设置第二焊接凸点190,获得如图13所示结构示意图;再将滤波器晶圆减薄至预设厚度,获得如图14所示结构示意图;然后将塑封结构切割成若干个芯片颗粒,获得如图15所示结构示意图。
可选地,第二焊接凸点由能够用于倒装焊接的材料制成,例如:焊锡球、铜柱、金凸块和导电胶中的一种或多种。
在一些实施例中,在第一焊盘上设置RDL层,在RDL层上制作第二焊接凸点。
在一些实施例中,在由第一有机薄膜170作为塑封层的情况下,在各待封装基板上形成第一有机薄膜,获得如图16所示结构示意图;减薄第一有机薄膜170,使第一有机薄膜170暴露出各第一焊盘,获得如图17所示结构示意图;将滤波器晶圆减薄至预设厚度,获得如图18所示结构示意图;然后将塑封结构切割成若干个芯片颗粒,获得如图19所示结构示意图。
在一些实施例中,在由第一有机薄膜170作为塑封层的情况下;减薄第一有机薄膜170,使第一有机薄膜170暴露出各第一焊盘;在各第一焊盘分别设置第二焊接凸点190,获得如图20所示结构示意图,将滤波器晶圆减薄至预设厚度,获得如图21所示结构示意图;然后将塑封结构切割成若干个芯片颗粒,获得如图22所示结构示意图。
结合图23所示,本发明实施例提供的另一种用于芯片封装的方法,包括:
步骤S201,提供滤波器晶圆和若干个待封装基板;各待封装基板上设置有多个第一焊盘;
步骤S202,将各待封装基板倒装焊接在滤波器晶圆上;
步骤S203,对各待封装基板进行塑封,在各待封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆形成塑封结构;各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔;
步骤S204,使塑封层暴露出各第一焊盘;
步骤S205,将滤波器晶圆减薄至预设厚度;
步骤S206,将塑封结构切割成若干个芯片颗粒。
采用本发明实施例提供的用于芯片封装的方法,通过将各待封装基板倒装焊接在滤波器晶圆上;对各待封装基板进行塑封,在各待封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆形成塑封结构;各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔;使塑封层暴露出各第一焊盘;将塑封结构切割成若干个芯片颗粒。这样,通过将待封装基板倒装焊接在未进行封装的滤波器晶圆上,在各封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔,从而在对滤波器晶圆完成封装的同时,也完成了滤波器封装,不需要单独对滤波器晶圆进行封装,再进行滤波器封装,能够使得芯片颗粒的尺寸小型化,同时降低制造芯片颗粒的成本。
结合图24所示,本发明实施例提供的另一种用于芯片封装的方法,包括:
步骤S301,提供滤波器晶圆和若干个待封装基板;各待封装基板上设置有多个第一焊盘;
步骤S302,将各待封装基板倒装焊接在滤波器晶圆上;
步骤S303,对各待封装基板进行塑封,在各待封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆形成塑封结构;各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔;
步骤S304,使塑封层暴露出各第一焊盘;
步骤S305,在各第一焊盘上分别设置第二焊接凸点;
步骤S306,将滤波器晶圆减薄至预设厚度;
步骤S307,将塑封结构切割成若干个芯片颗粒。
采用本发明实施例提供的用于芯片封装的方法,通过将各待封装基板倒装焊接在滤波器晶圆上;对各待封装基板进行塑封,在各待封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆形成塑封结构;各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔;使塑封层暴露出各第一焊盘;将塑封结构切割成若干个芯片颗粒。这样,通过将待封装基板倒装焊接在未进行封装的滤波器晶圆上,在各封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔,从而在对滤波器晶圆完成封装的同时,也完成了滤波器封装,不需要单独对滤波器晶圆进行封装,再进行滤波器封装,能够使得芯片颗粒的尺寸小型化,同时降低制造芯片颗粒的成本。
本发明实施例提供一种芯片颗粒,芯片颗粒通过本发明实施例提供的用于芯片封装的方法制得。
采用本发明实施例提供的芯片颗粒,通过将待封装基板倒装焊接在未进行封装的滤波器晶圆上,在各封装基板上形成塑封层,各待封装基板、各待封装基板对应的塑封层和滤波器晶圆分别围合形成有空腔,从而在对滤波器晶圆完成封装的同时完成了滤波器封装,不需要单独对滤波器晶圆进行封装,再进行滤波器封装,能够使得芯片颗粒的尺寸小型化,同时降低制造芯片颗粒的成本。
可选地,滤波器晶圆,用于支撑待封装基板;待封装基板,设置有多个第一焊盘,待封装基板倒装焊接在滤波器晶圆上;塑封层,与滤波器晶圆和待封装基板围合形成有空腔;塑封层暴露出各第一焊盘。可选地,在各第一焊盘上分别设置有第二焊接凸点。
以上描述和附图充分地示出了本发明的实施例,以使本领域的技术人员能够实践它们。其他实施例可以包括结构的、逻辑的、电气的、过程的以及其他的改变。实施例仅代表可能的变化。除非明确要求,否则单独的部件和功能是可选的,并且操作的顺序可以变化。一些实施例的部分和特征可以被包括在或替换其他实施例的部分和特征。而且,本申请中使用的用词仅用于描述实施例并且不用于限制权利要求。如在实施例以及权利要求的描述中使用的,除非上下文清楚地表明,否则单数形式的“一个”(a)、“一个”(an)和“所述”(the)旨在同样包括复数形式。类似地,如在本申请中所使用的术语“和/或”是指包含一个或一个以上相关联的列出的任何以及所有可能的组合。另外,当用于本申请中时,术语“包括”(comprise)及其变型“包括”(comprises)和/或包括(comprising)等指陈述的特征、整体、步骤、操作、元素,和/或组件的存在,但不排除一个或一个以上其它特征、整体、步骤、操作、元素、组件和/或这些的分组的存在或添加。在没有更多限制的情况下,由语句“包括一个…”限定的要素,并不排除在包括所述要素的过程、方法或者设备中还存在另外的相同要素。本文中,每个实施例重点说明的可以是与其他实施例的不同之处,各个实施例之间相同相似部分可以互相参见。对于实施例公开的方法、产品等而言,如果其与实施例公开的方法部分相对应,那么相关之处可以参见方法部分的描述。
Claims (10)
1.一种用于芯片封装的方法,其特征在于,包括:
提供滤波器晶圆和若干个待封装基板;各所述待封装基板上设置有多个第一焊盘;
将各所述待封装基板倒装焊接在所述滤波器晶圆上;
对各所述待封装基板进行塑封,在各所述待封装基板上形成塑封层,各所述待封装基板、各所述待封装基板对应的塑封层和所述滤波器晶圆形成塑封结构;各所述待封装基板、各所述待封装基板对应的塑封层和所述滤波器晶圆分别围合形成有空腔;
使所述塑封层暴露出各所述第一焊盘;
将所述塑封结构切割成若干个芯片颗粒。
2.根据权利要求1所述的方法,其特征在于,若干个待封装基板通过以下方式获取:
提供待切割基板,所述待切割基板上设置有多个第一焊盘,所述待切割基板远离所述第一焊盘的一侧设置有多个第二焊盘;
在各所述第二焊盘上分别设置第一焊接凸点;
对所述待切割基板进行切割获得若干个待封装基板,各所述待封装基板分别设置有多个第一焊盘和多个带有焊接凸点的第二焊盘。
3.根据权利要求2所述的方法,其特征在于,在提供待切割基板后,还包括:
在所述待切割基板设置第一焊盘的一侧施加支撑层,所述支撑层覆盖各所述第一焊盘。
4.根据权利要求1所述的方法,其特征在于,使所述塑封层暴露出各所述第一焊盘,包括:
减薄所述塑封层,使所述塑封层暴露出所述第一焊盘。
5.根据权利要求3所述的方法,其特征在于,使所述塑封层暴露出各所述第一焊盘,包括:
减薄所述塑封层和所述支撑层,使所述塑封层暴露出所述第一焊盘。
6.根据权利要求1至5任一项所述的方法,其特征在于,使所述塑封层暴露出各所述第一焊盘后,还包括:
将所述滤波器晶圆减薄至预设厚度。
7.根据权利要求1至5任一项所述的方法,其特征在于,使所述塑封层暴露出各所述第一焊盘后,还包括:
在各所述第一焊盘上分别设置第二焊接凸点。
8.一种芯片颗粒,其特征在于,所述芯片颗粒通过执行权利要求1至7任一项所述的用于芯片封装的方法制得。
9.根据权利要求8所述的芯片颗粒,其特征在于,包括:
滤波器晶圆,用于支撑待封装基板;
所述待封装基板,设置有多个第一焊盘,所述待封装基板倒装焊接在所述滤波器晶圆上;
塑封层,与所述滤波器晶圆和所述待封装基板围合形成有空腔;所述塑封层暴露出各所述第一焊盘。
10.根据权利要求9所述的芯片颗粒,其特征在于,所述第一焊盘上设置有第二焊接凸点。
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