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CN107146795A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN107146795A
CN107146795A CN201710103788.2A CN201710103788A CN107146795A CN 107146795 A CN107146795 A CN 107146795A CN 201710103788 A CN201710103788 A CN 201710103788A CN 107146795 A CN107146795 A CN 107146795A
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CN
China
Prior art keywords
layer
insulating layer
redistribution layer
chip package
redistribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201710103788.2A
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English (en)
Inventor
林佳升
赖炯霖
陈瑰玮
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XinTec Inc
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XinTec Inc
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Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN107146795A publication Critical patent/CN107146795A/zh
Withdrawn legal-status Critical Current

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract

本发明提供一种晶片封装体及其制造方法，该晶片封装体包括：一基底，基底内的一感测区或元件区电性连接至一导电垫；一第一绝缘层，位于基底上；一重布线层，位于第一绝缘层上，重布线层的一第一部分及一第二部分电性连接至导电垫；一第二绝缘层，顺应性地延伸于第一绝缘层上且包覆第一部分及第二部分的侧表面；一保护层，位于第二绝缘层上，第二绝缘层的一部分位于保护层与第一绝缘层之间。本发明可大幅提升晶片封装体的品质及可靠度。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种半导体封装技术，特别为有关于一种晶片封装体及其制造方法。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使其免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路，例如晶片封装体内具有导线以形成导电路径。随着电子产品逐渐朝向小型化发展，晶片封装体的尺寸也逐渐缩小。
然而，当晶片封装体的尺寸缩小时，导线的厚度及宽度变小，且导线与导线之间的间距也变窄，使得密集的线路区域内容易产生电路故障的问题。举例来说，由金属所构成的导线与导线之间可能出现电迁移(electromigration)的现象及/或产生贾凡尼效应(Galvanic)，因而造成电性短路及/或断路的问题，导致晶片封装体的品质及可靠度降低。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片封装体，包括：一基底，基底内的一感测区或元件区电性连接至一导电垫；一第一绝缘层，位于基底上；一重布线层，位于第一绝缘层上，重布线层的一第一部分及一第二部分电性连接至导电垫；一第二绝缘层，顺应性地延伸于第一绝缘层上且包覆第一部分及第二部分的侧表面；一保护层，位于第二绝缘层上，第二绝缘层的一部分位于保护层与第一绝缘层之间。
本发明还提供一种晶片封装体，包括：一基底，基底内的一感测区或元件区电性连接至一导电垫；一第一绝缘层，位于基底上；一第一重布线层，位于第一绝缘层上，第一重布线层的一第一部分电性连接至导电垫；一第二重布线层，其一第一部分位于第一重布线层的第一部分上，且第二重布线层的一第二部分直接接触第一绝缘层。
本发明还提供一种晶片封装体的制造方法，包括：提供一基底，基底内的一感测区或元件区电性连接至一导电垫；在基底上形成一第一绝缘层；在第一绝缘层上形成一第二重布线层，第二重布线层的一第一部分及一第二部分电性连接至导电垫；形成一第二绝缘层，第二绝缘层顺应性地延伸于第一绝缘层上且包覆第二重布线层的第一部分及第二部分的侧表面；以及在第二绝缘层上形成一保护层，第二绝缘层的一部分位于保护层与第一绝缘层之间。
本发明可解决密集的线路区域内产生电路故障的问题，特别是能够减缓或消除电迁移现象及/或贾凡尼效应，因此可大幅提升晶片封装体的品质及可靠度。
附图说明
图1A至1F是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图。
图2A至2C是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图。
图3是绘示出根据本发明一些实施例的晶片封装体的剖面示意图。
其中，附图中符号的简单说明如下：
100：基底；100a：前表面；100b：背表面；100c：侧表面；110：感测区或元件区；120：晶片区；130：第一绝缘层；140：导电垫150：光学部件；160：间隔层；170：盖板；180：空腔；190：第一开口；200：第二开口；210：绝缘层；220A：第一部分；220B：第二部分；230A：第一部分；230B：第二部分；240：第二绝缘层；250：保护层；260：开口；270：导电结构；SC：切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而，应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然而其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System，MEMS)、生物辨识元件(biometric device)、微流体系统(micro fluidic systems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package，WSP)制程对影像感测元件、发光二极管(light-emittingdiodes，LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprint recognition device)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆迭(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
以下配合图1A至1F说明本发明一些实施例的晶片封装体的制造方法，其中图1A至1F是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图。
请参照图1A，提供一基底100，其具有一前表面100a及一背表面100b，且包括多个晶片区120。为简化图式，此处仅绘示出一完整的晶片区120及与其相邻的晶片区120的一部分。在一些实施例中，基底100可为一硅基底或其他半导体基底。在一些实施例中，基底100为一硅晶圆，以利于进行晶圆级封装制程。
基底100的前表面100a上具有一绝缘层130。一般而言，绝缘层130可由层间介电层(interlayer dielectric，ILD)、金属间介电层(inter-metal dielectric，IMD)及覆盖的钝化层(passivation)组成。为简化图式，此处仅绘示出单层绝缘层130。在一些实施例中，绝缘层130可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
在一些实施例中，每一晶片区120的绝缘层130内具有一个或一个以上的导电垫140。在一些实施例中，导电垫140可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明。在一些实施例中，每一晶片区120的绝缘层130内包括一个或一个以上的开口，露出对应的导电垫140。
在一些实施例中，每一晶片区120内具有一感测区或元件区110。感测区或元件区110可邻近于绝缘层130及基底100的前表面100a，且可通过绝缘层130内的内连线结构(未绘示)与导电垫140电性连接。内连线结构包括各种导电特征部件，例如导电线路、导电介层窗及导电插塞。
感测区或元件区110内包括一感测元件或其他适合的电子元件。在一些实施例中，感测区或元件区110内包括感光元件或其他适合的光电元件。在一些其他实施例中，感测区或元件区110内可包括感测生物特征的元件(例如，一指纹辨识元件)、感测环境特征的元件(例如，一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件)或其他适合的感测元件。
在一些实施例中，可依序进行半导体装置的前段(front end)制程(例如，在基底100内制作感测区或元件区110)及后段(back end)制程(例如，在基底100上制作绝缘层130、内连线结构及导电垫140)来提供前述结构。换句话说，以下晶片封装体的制造方法用于对完成后段制程的基底进行后续的封装制程。
在一些实施例中，每一晶片区120内具有一光学部件150设置于基底100的前表面100a上，且对应于感测区或元件区110。在一些实施例中，光学部件150可为微透镜阵列、滤光层、其组合或其他适合的光学部件。在一些其他实施例中，基底100的前表面100a上未设置光学部件150。
接着，在一盖板170上形成一间隔层(或称作围堰(dam))160，通过间隔层160将盖板170接合至基底100的前表面100a上，且间隔层160在每一晶片区120内的基底100与盖板170之间形成一空腔180，使得光学部件150位于空腔180内，并通过盖板170保护空腔180内的光学部件150。在一些其他实施例中，可先在基底100的前表面100a上形成间隔层160，之后将盖板170接合至基底100上。
在一些实施例中，盖板170可包括玻璃、氮化铝(AlN)、或其他适合的透明材料。在一些其他实施例中，基底100的前表面100a上未设置光学部件，且盖板170可包括半导体材料或其他适合的非透明材料。在一些实施例中，盖板170为暂时性基底，且在后续制程中被去除。
在一些实施例中，间隔层160大致上不吸收水气。在一些实施例中，间隔层160不具有粘性，可通过额外的粘着胶将盖板170贴附于基底100上。在一些其他实施例中，间隔层160具有粘性，因此可通过间隔层160将盖板170贴附于基底100上，如此一来间隔层160可不与任何的粘着胶接触，以确保间隔层160的位置不因粘着胶而移动。同时，由于不需使用粘着胶，可避免粘着胶溢流而污染光学部件150。在一些其他实施例中，以粘着层取代间隔层160，且基底100与盖板170之间没有形成空腔180。
在一些实施例中，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)形成间隔层160。在一些实施例中，间隔层160可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene，BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他适合的绝缘材料。或者，间隔层160可包括光阻材料，且可通过曝光及显影制程而图案化，以露出光学部件150。
请参照图1B，以盖板170作为承载基底，对基底100的背表面100b进行薄化制程(例如，蚀刻制程、铣削(milling)制程、磨削(grinding)制程或研磨(polishing)制程)，以减少基底100的厚度。
接着，通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在每一晶片区120的基底100内同时形成多个第一开口190及第二开口200，第一开口190及第二开口200自基底100的背表面100b露出绝缘层130。在一些其他实施例中，可分别通过刻痕(notching)制程以及微影及蚀刻制程形成第二开口200以及第一开口190。
在一些实施例中，第一开口190对应于导电垫140而贯穿基底100，且第一开口190邻近于前表面100a的口径小于其邻近于背表面100b的口径，因此第一开口190具有倾斜的侧表面，进而降低后续形成于第一开口190内的膜层的制程难度，并提高可靠度。举例来说，由于第一开口190邻近于前表面100a的口径小于其邻近于背表面100b的口径，因此后续形成于第一开口190内的膜层(例如，后续形成的绝缘层及重布线层)能够较轻易地沉积于第一开口190与绝缘层130之间的转角，以避免影响电性连接路径或产生漏电流的问题。
在一些实施例中，第二开口200为一沟槽，第二开口200沿着相邻晶片区120之间的切割道SC延伸且贯穿基底100，使得每一晶片区120内的基底100彼此分离。第二开口200邻近于前表面100a的口径小于其邻近于背表面100b的口径，因此第二开口200具有倾斜的侧表面，亦即每一晶片区120内的基底100具有倾斜的侧表面100c。
在一些实施例中，相邻两晶片区120内的多个第一开口190沿着第二开口200间隔排列，且第一开口190与第二开口200通过基底100的侧壁部分互相间隔且完全隔离。
在一些实施例中，第二开口200可沿着晶片区120延伸而环绕第一开口190。在一些其他实施例中，第一开口190与第二开口200连通。例如，第一开口190邻近于背表面100b的部分与第二开口200邻近于背表面100b的部分彼此连通，使得基底100具有一侧壁部分低于背表面100b。换句话说，上述侧壁部分的厚度小于基底100的厚度。由于第一开口190与第二开口200彼此连通，而并非通过基底100的一部分完全隔离，因此能够防止应力累积于第一开口190与第二开口200之间的基底100，且可通过第二开口200缓和及释放应力，进而避免基底100的侧壁部分出现破裂。
请参照图1C，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在基底100的背表面100b上形成一第一绝缘层210，第一绝缘层210顺应性地沉积于第一开口190及第二开口200的侧壁及底部上。在一些实施例中，第一绝缘层210可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，可通过微影制程及蚀刻制程，去除第一开口190底部的第一绝缘层210及其下方的绝缘层130，使得第一开口190延伸至绝缘层130内而露出对应的导电垫140。
之后，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在第一绝缘层210上形成一层或多层图案化的重布线层。在一些实施例中，第一重布线层包括互相电性连接的第一部分220A及第二部分220B，第二重布线层包括互相电性连接的第一部分230A及第二部分230B。
在一些实施例中，第一重布线层与第二重布线层具有大致上相同的线路图案，例如第一部分220A与第一部分230A完全重叠且第二部分220B与第二部分230B完全重叠。换句话说，第一部分220A的侧表面与第一部分230A的侧表面共平面，且第二部分220B的侧表面与第二部分230B的侧表面共平面。
在一些其他实施例中，第一重布线层与第二重布线层具有类似的线路图案。第一部分230A可包覆第一部分220A的侧表面及顶表面，且第二部分230B可包覆第二部分220B的侧表面及顶表面，因此第一部分230A及第二部分230B延伸至直接接触第一绝缘层210。
第一重布线层与第二重布线层的厚度可相同或不同。例如，第一重布线层的厚度可小于第二重布线层的厚度。在一些其他实施例中，图案化的重布线层仅由一层重布线层所构成。或者，图案化的重布线层可包括三层或三层以上的重布线层。
在一些实施例中，第一部分220A以及第一部分230A位于第一开口190的侧壁及底部上，例如第一部分220A以及第一部分230A顺应性地延伸于第一开口190的侧壁及底部上，以电性连接导电垫140。第一部分220A以及第一部分230A还自第一开口190内延伸至基底100的背表面100b上方，但第一部分220A以及第一部分230A仅局部覆盖第一开口190周围的背表面100b，如图1C所示。在一些实施例中，第一部分220A以及第一部分230A与导电垫140纵向地重叠，而未与感测区或元件区110纵向地重叠。
在一些实施例中，第二部分220B以及第二部分230B位于基底100的背表面100b上方，例如第二部分220B及/或第二部分230B纵向地重叠于感测区或元件区110，而未与导电垫140纵向地重叠。在一些其他实施例中，第二部分220B及/或第二部分230B可未与感测区或元件区110纵向地重叠。
在一些实施例中，第一部分220A、第二部分220B、第一部分230A及第二部分230B通过第一绝缘层210与基底100电性隔离。第一部分220A以及第一部分230A经由第一开口190直接电性接触或间接电性连接露出的导电垫140。因此，第一开口190内的第一部分220A以及第一部分230A也可称为硅通孔电极(through silicon via，TSV)。
在一些实施例中，第一部分220A、第二部分220B、第一部分230A及第二部分230B可包括铝、镍、金、铜、铂、锡、钛钨、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。举例来说，第一部分220A及第二部分220B由铝所构成，而第一部分230A及第二部分230B由镍所构成。或者，第一部分220A及第二部分220B由钛钨所构成，而第一部分230A及第二部分230B由铝及/或镍所构成。
请参照图1D，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在基底100的背表面100b上形成一第二绝缘层240。第二绝缘层240覆盖图案化的第一重布线层及第二重布线层，且与第一绝缘层210直接接触。
第二绝缘层240自背表面100b沿着第一开口190及第二开口200的侧壁及底部顺应性地延伸于第一绝缘层210上，且第二绝缘层240覆盖基底100的侧表面100c。也就是说，位于第一开口190的侧壁及底部上的第二绝缘层240的厚度大致上相同于位于第二开口200的侧壁及底部上的第二绝缘层240的厚度，也大致上相同于位于背表面100b上的第二绝缘层240的厚度。
在一些实施例中，第二绝缘层240完全覆盖第一部分220A及第二部分220B的侧表面，且第二绝缘层240完全覆盖第一部分230A及第二部分230B的侧表面及顶表面。在一些实施例中，第一绝缘层210及第二绝缘层240共同包围第二部分220B及第二部分230B。
在一些实施例中，一部分的第二绝缘层240侧向地夹设于第一部分220A与第二部分220B之间。在一些实施例中，一部分的第二绝缘层240侧向地夹设于两个第二部分220B之间。
在一些实施例中，第二绝缘层240可包括无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)或其他适合的绝缘材料。第二绝缘层240与第一绝缘层210可由相同的材料或不同的材料所构成。在一些实施例中，第二绝缘层240由具有高绝缘性且大致上不吸收水气的材料所构成。
在一些实施例中，第二绝缘层240的厚度小于第一绝缘层210的厚度。例如，第一绝缘层210的厚度可为大约0.5μm至大约4μm的范围，而第二绝缘层240的厚度可为大约0.2μm至大约0.5μm的范围。在一些实施例中，第二绝缘层240的厚度小于第一重布线层及/或第二重布线层的厚度。例如，第二绝缘层240的厚度小于第二部分220B的厚度及/或第二部分230B的厚度，或是第二绝缘层240的厚度小于第二部分220B加上第二部分230B的厚度。
请参照图1E，可通过沉积制程，在基底100的背表面100b上形成一保护层250。保护层250自背表面100b延伸至第二开口200内，且覆盖基底100的侧表面100c。保护层250与第二绝缘层240直接接触。
在一些实施例中，保护层250填满第二开口200。在一些其他实施例中，保护层250仅部分填充第二开口200而未完全填满第二开口200。
在一些实施例中，保护层250封住第一开口190，但未填入第一开口190，使得第一开口190内的第二绝缘层240与保护层250之间形成一孔洞。在一些其他实施例中，保护层250可局部填充第一开口190或完全填满第一开口190。
在一些实施例中，保护层250与第一部分220A、第二部分220B、第一部分230A及第二部分230B完全隔离而未直接接触。在一些实施例中，一部分的第二绝缘层240纵向及/或侧向地夹设于第一部分230A与保护层250之间。一部分的第二绝缘层240纵向及/或侧向地夹设于第二部分230B与保护层250之间。在一些实施例中，一部分的第二绝缘层240侧向地夹设于第一部分220A与保护层250之间。一部分的第二绝缘层240侧向地夹设于第二部分220B与保护层250之间。
在一些实施例中，保护层250与第一绝缘层210完全分离而未直接接触。在一些实施例中，一部分的第二绝缘层240纵向地夹设于保护层250与第一绝缘层210之间，也侧向地夹设于第一部分220A与第二部分220B之间。
在一些实施例中，保护层250可包括环氧树脂、绿漆、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
在一些实施例中，第二绝缘层240与保护层250由不同的材料所构成。举例来说，第二绝缘层240的材料相较于保护层250的材料具有较高的绝缘性。再者，保护层250的材料可能会吸收水气，而第二绝缘层240的材料不具吸水性。
接着，可通过微影制程及蚀刻制程，在基底100的背表面100b上的保护层250及第二绝缘层240内形成一个或多个开口260，以露出第二部分230B的一部分。
在一些实施例中，第二绝缘层240内的开口260的宽度相同于保护层250内的开口260的宽度。在一些其他实施例中，第二绝缘层240内的开口260的宽度大于保护层250内的开口260的宽度。例如，采用湿式蚀刻制程形成开口260时，可能会对第二绝缘层240过度蚀刻而产生底切(under cut)现象。
请参照图1F，可通过电镀制程、网版印刷制程或其他适合的制程，在开口260内填入导电结构270(例如，焊球、凸块或导电柱)，以与露出的第二部分230B电性连接。在一些实施例中，导电结构270可包括锡、铅、铜、金、镍、或前述的组合。
在一些实施例中，导电结构270与第二绝缘层240直接接触。在一些实施例中，导电结构270的下部被第二绝缘层240及保护层250连续地环绕。在一些实施例中，导电结构270与露出的第二部分230B之间可选择性形成其他接合层，举例来说，接合层可包括镍层、金层、其他适合的材料层或其组合。在一些实施例中，接合层与第二绝缘层240直接接触，而导电结构270与第二绝缘层240彼此分隔。
接着，沿着切割道SC(等同于沿着第二开口200)切割保护层250、第二绝缘层240、第一绝缘层210、间隔层160及盖板170，以形成多个独立的晶片封装体。举例来说，可使用切割刀具或雷射进行切割制程，其中使用雷射切割制程可以避免上下膜层发生位移。切割后的基底100及绝缘层130可视为一晶片/晶粒。
根据本发明的上述实施例，特别形成第二绝缘层来完全覆盖图案化的重布线层的侧表面及/或顶表面。第二绝缘层具有高绝缘性，且可有效隔绝外界的污染物，例如第二绝缘层可防止水气侵入图案化的重布线层内。如此一来，能够通过第二绝缘层减缓或消除图案化的重布线层之间的电迁移现象，避免第一重布线层与第二重布线层之间因离子迁移(例如，镍或其他金属离子)形成不必要的连接而造成短路，也避免第一重布线层及/或第二重布线层内因离子迁移出现空洞而造成断路，因此可改善晶片封装体的品质及可靠度。
以下配合图2A至2C说明本发明一些实施例的晶片封装体的制造方法。图2A至2C是绘示出根据本发明一些实施例的晶片封装体的制造方法的剖面示意图，其中相同于图1A至1F中的部件使用相同的标号并省略其说明。
请参照图2A，提供如图1B所示的结构，并通过与图1C相同或相似的步骤，形成第一绝缘层210。接着，可通过微影制程及蚀刻制程，去除第一开口190底部的第一绝缘层210及其下方的绝缘层130，使得第一开口190延伸至绝缘层130内而露出对应的导电垫140。
之后，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在第一绝缘层210上形成图案化的第一重布线层。在一些实施例中，第一重布线层包括第一部分220A。第一重布线层可包括单层材料层或多层材料层。
在一些实施例中，第一部分220A位于第一开口190的侧壁及底部上，例如第一部分220A顺应性地延伸于第一开口190的侧壁及底部上。第一部分220A还自第一开口190内延伸至基底100的背表面100b上方，但第一部分220A仅局部覆盖第一开口190周围的背表面100b。在一些实施例中，第一部分220A与导电垫140纵向地重叠，而未与感测区或元件区110纵向地重叠。
在一些实施例中，第一部分220A可包括铝、镍、金、铜、铂、锡、钛钨、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。
在一些实施例中，第一部分220A作为导电垫140与后续形成于第一部分220A上方的材料层之间的隔离层。举例来说，第一部分220A的材料(例如，钛钨或其他材料)可避免导电垫140的材料(例如，铜或其他材料)与后续形成的材料层(例如，铝或其他材料)彼此反应而产生迁移或扩散现象。因此，第一部分220A能够防止导电垫140与后续形成的材料层出现层离(delamination)的问题，也避免晶片封装体的性能降低。
请参照图2B，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在第一绝缘层210及第一部分220A上形成图案化的第二重布线层。在一些实施例中，第二重布线层包括互相电性连接的第一部分230A及第二部分230B。第二重布线层可包括单层材料层或多层材料层。
在一些实施例中，第一部分230A与第一部分220A具有大致上相同的线路图案，例如第一部分230A与第一部分220A完全重叠。在一些其他实施例中，第一部分230A与第一部分220A具有类似的线路图案，例如第一部分230A可包覆第一部分220A的侧表面及顶表面，因此第一部分230A延伸至直接接触第一绝缘层210。
在一些实施例中，第一部分230A位于第一开口190内的第一部分220A上，例如第一部分230A沿着第一开口190的侧壁及底部顺应性地延伸。第一部分230A还自第一开口190内延伸至基底100的背表面100b上方，但第一部分230A仅局部覆盖第一开口190周围的背表面100b。
在一些实施例中，第一部分230A与导电垫140纵向地重叠，而未与感测区或元件区110纵向地重叠。在一些实施例中，第二部分230B位于基底100的背表面100b上方，例如第二部分230B纵向地重叠于感测区或元件区110，但第二部分230B未与导电垫140纵向地重叠。
在一些实施例中，第二部分230B的底表面低于第一部分230A的底表面，因此第二部分230B的底表面与第一部分230A的底表面不共平面。在一些实施例中，第二部分230B的底表面与一部分的第一部分220A的底表面大致上共平面。
在一些实施例中，第二部分230B与第一绝缘层210直接接触，而一部分的第一部分220A将第一部分230A与第一绝缘层210互相分隔。在一些实施例中，一部分的第一部分220A夹设于第一部分230A与第一绝缘层210之间，另一部分的第一部分220A夹设于第一部分230A与导电垫140之间。
在一些实施例中，第一部分230A及第二部分230B可包括铝、镍、金、铜、铂、锡、钛钨、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。在一些实施例中，第一部分220A由钛钨所构成，而第一部分230A及第二部分230B由铝及/或镍所构成。
在某些情况下，一层以上的重布线层由不同的材料所构成，使得一层以上的重布线层之间可能因不同的电位差而产生贾凡尼效应，导致不同的材料层之间产生置换反应。举例来说，钛钨层和镍层或其他材料层之间可能产生贾凡尼效应，导致镍离子迁移或扩散至钛钨层内。
根据本发明的上述实施例，第一重布线层仅包括作为隔离层的第一部分220A，而没有形成于感测区或元件区110上的部份(例如，图1C所示的第二部分220B)，因此可避免感测区或元件区110上的第一重布线层与第二重布线层之间产生贾凡尼效应，进而确保晶片封装体的电性表现。
在某些情况下，在沉积一层以上的重布线层之后对一层以上的重布线层进行蚀刻制程。然而，由于上层重布线层覆盖住下层重布线层，蚀刻剂仅能自下层重布线层的侧表面进行去除，因此难以顺利地将下层重布线层图案化，进而出现下层重布线层的残留物。
根据本发明的上述实施例，在沉积第二重布线层之前，先对已沉积的第一重布线层进行蚀刻制程，蚀刻剂可自第一重布线层的整个顶表面进行去除，因此有利于第一重布线层的图案化，而不会产生残留物。
举例来说，先使用第一罩幕层将沉积的第一重布线层图案化为第一部分220A，之后沉积第二重布线层，并使用第二罩幕层将第二重布线层图案化为第一部分230A及第二部分230B，其中第一罩幕层与第二罩幕层具有不同的开口图案。如此一来，能够大致上完全去除位于感测区或元件区110上的第一重布线层(例如，图1C所示的第二部分220B)，使得感测区或元件区110上不会出现第一重布线层的残留物，可避免残留物对晶片封装体的可靠度造成负面影响。
请参照图2C，可通过与第1E至1F图相同或相似的步骤，依序形成保护层250、保护层250的开口260及导电结构270。接着，进行切割制程，以形成多个独立的晶片封装体。
在一些实施例中，保护层250未填入第一开口190，使得第一开口190内的第一部分230A与保护层250之间形成一孔洞。如此一来，后续制程中遭遇热循环(Thermal Cycle)时，孔洞能够作为保护层250与第一部分220A以及第一部分230A之间的缓冲，以降低由于热膨胀系数不匹配所引发不必要的应力，且防止外界温度或压力剧烈变化时保护层250会过度拉扯第一部分220A以及第一部分230A，进而可避免靠近导电垫结构的第一部分220A以及第一部分230A剥离甚至断路的问题。在一些其他实施例中，保护层250可局部填充第一开口190或完全填满第一开口190。
在一些实施例中，保护层250与第一部分220A、第一部分230A及第二部分230B直接接触。保护层250也与第一绝缘层210直接接触。在一些实施例中，一部分的保护层250侧向地夹设于第一部分220A与第二部分230B之间。一部分的保护层250侧向地夹设于多个第二部分230B之间。在一些实施例中，第二部分230B局部纵向地夹设于保护层250与第一绝缘层210之间。
在一些实施例中，导电结构270与露出的第二部分230B之间可选择性形成其他接合层，举例来说，接合层可包括镍层、金层、其他适合的材料层或其组合。
本发明的上述各种实施例可解决密集的线路区域内产生电路故障的问题，特别是能够减缓或消除电迁移现象及/或贾凡尼效应，因此可大幅提升晶片封装体的品质及可靠度。
本发明的上述实施例也可具有许多变化及/或更动，例如图1A至1F的实施例也可与图2A至2C的实施例互相结合。举例来说，请参照图3，提供如图2B所示的结构，并通过与图1D至1F相同或相似的步骤形成图3中的晶片封装体。在图3中，第二部分230B与第二绝缘层240及第一绝缘层210直接接触，且第二部分230B局部纵向地夹设于第二绝缘层240与第一绝缘层210之间。
可以理解的是，图3中的晶片封装体可具有图1F及/或图2C中的晶片封装体所具有的前述优点及技术效果。
为了说明本发明实施例，此处使用具有前照式(frontside illumination，FSI)感测装置的晶片封装体作为范例。然而，本发明实施例也可适用于具有背照式(backsideillumination，BSI)感测装置的晶片封装体。再者，上述晶片封装体的制造方法并不限定于具有光学感测装置的晶片封装体，其亦可应用于其他类型的晶片封装体，例如可应用于具有生物特征感测元件或环境特征感测元件的晶片封装体、或其他适合的晶片封装体。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (22)

1.一种晶片封装体，其特征在于，包括：
基底，其中该基底内的感测区或元件区电性连接至导电垫；
第一绝缘层，位于该基底上；
第一重布线层，位于该第一绝缘层上，其中该第一重布线层的第一部分及第二部分电性连接至该导电垫；
第二绝缘层，其中该第二绝缘层顺应性地延伸于该第一绝缘层上且包覆该第一部分及该第二部分的侧表面；以及
保护层，位于该第二绝缘层上，其中该第二绝缘层的一部分位于该保护层与该第一绝缘层之间。
2.根据权利要求1所述的晶片封装体，其特征在于，该第二绝缘层的该部分与该第一绝缘层及该保护层直接接触。
3.根据权利要求1所述的晶片封装体，其特征在于，该第二绝缘层的该部分夹设于该第一重布线层的该第一部分与该第二部分之间。
4.根据权利要求1所述的晶片封装体，其特征在于，还包括导电结构，其中该导电结构位于该第一重布线层的该第二部分上，且该导电结构的下部被该保护层及该第二绝缘层所环绕。
5.根据权利要求1所述的晶片封装体，其特征在于，该第二绝缘层的另一部分侧向地夹设于该第一重布线层的该第一部分与该保护层之间。
6.根据权利要求1所述的晶片封装体，其特征在于，该第二绝缘层的材料不同于该保护层的材料。
7.一种晶片封装体，其特征在于，包括：
基底，其中该基底内的感测区或元件区电性连接至导电垫；
第一绝缘层，位于该基底上；
第一重布线层，位于该第一绝缘层上，其中该第一重布线层的第一部分电性连接至该导电垫；以及
第二重布线层，其中该第二重布线层的第一部分位于该第一重布线层的该第一部分上，且该第二重布线层的第二部分直接接触该第一绝缘层。
8.根据权利要求7所述的晶片封装体，其特征在于，该第二重布线层的该第二部分纵向地重叠于该感测区或元件区。
9.根据权利要求7所述的晶片封装体，其特征在于，该第一重布线层的该第一部分局部夹设于该第一绝缘层与该第二重布线层的该第一部分之间。
10.根据权利要求7所述的晶片封装体，其特征在于，该第一重布线层的该第一部分局部夹设于该导电垫与该第二重布线层的该第一部分之间。
11.根据权利要求7所述的晶片封装体，其特征在于，该第二重布线层的该第二部分的底表面低于该第二重布线层的该第一部分的底表面，且与该第一重布线层的该第一部分的底表面共平面。
12.根据权利要求7所述的晶片封装体，其特征在于，该第一重布线层的材料不同于该第二重布线层的材料。
13.根据权利要求7所述的晶片封装体，其特征在于，还包括第二绝缘层，其中该第二绝缘层顺应性地延伸于该第一绝缘层上且包覆该第一重布线层的该第一部分的侧表面、该第二重布线层的该第一部分及该第二部分的侧表面。
14.根据权利要求13所述的晶片封装体，其特征在于，该第二绝缘层的一部分夹设于该第一重布线层的该第一部分与该第二重布线层的该第二部分之间。
15.根据权利要求7所述的晶片封装体，其特征在于，还包括保护层，该保护层位于该第二重布线层上，且直接接触该第一绝缘层、该第一重布线层及该第二重布线层。
16.根据权利要求15所述的晶片封装体，其特征在于，该保护层的一部分夹设于该第一重布线层的该第一部分与该第二重布线层的该第二部分之间。
17.一种晶片封装体的制造方法，其特征在于，包括：
提供基底，其中该基底内的感测区或元件区电性连接至导电垫；
在该基底上形成第一绝缘层；
在该第一绝缘层上形成第二重布线层，其中该第二重布线层的第一部分及第二部分电性连接至该导电垫；
形成第二绝缘层，其中该第二绝缘层顺应性地延伸于该第一绝缘层上且包覆该第二重布线层的该第一部分及该第二部分的侧表面；以及
在该第二绝缘层上形成保护层，其中该第二绝缘层的一部分位于该保护层与该第一绝缘层之间。
18.根据权利要求17所述的晶片封装体的制造方法，其特征在于，还包括在形成该第二重布线层之前，形成图案化的第一重布线层，其中该第一重布线层的第一部分位于该第二重布线层的该第一部分与该第一绝缘层之间。
19.根据权利要求18所述的晶片封装体的制造方法，其特征在于，该第二重布线层的该第二部分直接接触该第一绝缘层。
20.根据权利要求18所述的晶片封装体的制造方法，其特征在于，该第一重布线层的该第一部分延伸至直接接触该导电垫。
21.根据权利要求18所述的晶片封装体的制造方法，其特征在于，该第二重布线层的该第二部分的底表面低于该第二重布线层的该第一部分的底表面，且与该第一重布线层的该第一部分的底表面共平面。
22.根据权利要求17所述的晶片封装体的制造方法，其特征在于，还包括：
在该保护层及该第二绝缘层内形成开口，以露出该第二重布线层的该第二部分；以及
在该开口内形成导电结构，其中该导电结构的下部被该保护层及该第二绝缘层所环绕。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110085564A (zh) * 2018-01-25 2019-08-02 代罗半导体有限公司 晶圆级晶粒尺寸封装结构及其制造方法
CN110491859A (zh) * 2017-05-18 2019-11-22 精材科技股份有限公司 晶片封装体及其制造方法
CN110676228A (zh) * 2018-07-03 2020-01-10 精材科技股份有限公司 晶片封装体
CN113307222A (zh) * 2020-02-27 2021-08-27 台湾积体电路制造股份有限公司 微机电系统及其制造方法

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI649856B (zh) * 2016-05-13 2019-02-01 精材科技股份有限公司 晶片封裝體與其製造方法
US10211161B2 (en) * 2016-08-31 2019-02-19 Advanced Semiconductor Engineering, Inc. Semiconductor package structure having a protection layer
CN110291637B (zh) * 2017-02-22 2023-11-14 索尼半导体解决方案公司 摄像器件、电子装置和制造摄像器件的方法
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
WO2019195428A1 (en) 2018-04-04 2019-10-10 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
WO2020009759A1 (en) 2018-07-02 2020-01-09 Qorvo Us, Inc. Rf semiconductor device and manufacturing method thereof
JP6897640B2 (ja) * 2018-08-02 2021-07-07 日亜化学工業株式会社 発光装置の製造方法
US11171090B2 (en) * 2018-08-30 2021-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
KR102771428B1 (ko) 2019-01-23 2025-02-26 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
KR102713392B1 (ko) * 2019-10-30 2024-10-04 삼성전자주식회사 반도체 칩, 및 이를 가지는 반도체 패키지
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
US11851321B2 (en) 2021-03-01 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Micro-electro mechanical system and manufacturing method thereof
KR20220021238A (ko) * 2020-08-13 2022-02-22 삼성전자주식회사 반도체 패키지 및 그 제조방법
US11600592B2 (en) * 2021-01-21 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package
WO2022186857A1 (en) 2021-03-05 2022-09-09 Qorvo Us, Inc. Selective etching process for si-ge and doped epitaxial silicon
CN116344478B (zh) * 2021-12-24 2025-02-25 长鑫存储技术有限公司 一种半导体结构及半导体结构的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108573A1 (en) * 2005-11-17 2007-05-17 Samsung Electronics Co., Ltd. Wafer level package having redistribution interconnection layer and method of forming the same
CN102201383A (zh) * 2010-03-26 2011-09-28 精材科技股份有限公司 电子元件封装体及其制造方法
CN104733422A (zh) * 2013-11-18 2015-06-24 精材科技股份有限公司 晶片封装体及其制造方法
CN105047629A (zh) * 2010-03-19 2015-11-11 精材科技股份有限公司 影像感测元件封装构件及其制作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI550737B (zh) * 2014-08-11 2016-09-21 精材科技股份有限公司 晶片封裝體及其製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108573A1 (en) * 2005-11-17 2007-05-17 Samsung Electronics Co., Ltd. Wafer level package having redistribution interconnection layer and method of forming the same
CN105047629A (zh) * 2010-03-19 2015-11-11 精材科技股份有限公司 影像感测元件封装构件及其制作方法
CN102201383A (zh) * 2010-03-26 2011-09-28 精材科技股份有限公司 电子元件封装体及其制造方法
CN104733422A (zh) * 2013-11-18 2015-06-24 精材科技股份有限公司 晶片封装体及其制造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491859A (zh) * 2017-05-18 2019-11-22 精材科技股份有限公司 晶片封装体及其制造方法
CN110085564A (zh) * 2018-01-25 2019-08-02 代罗半导体有限公司 晶圆级晶粒尺寸封装结构及其制造方法
CN110085564B (zh) * 2018-01-25 2024-05-24 代罗半导体有限公司 晶圆级晶粒尺寸封装结构及其制造方法
CN110676228A (zh) * 2018-07-03 2020-01-10 精材科技股份有限公司 晶片封装体
CN110676228B (zh) * 2018-07-03 2021-10-22 精材科技股份有限公司 晶片封装体
CN113307222A (zh) * 2020-02-27 2021-08-27 台湾积体电路制造股份有限公司 微机电系统及其制造方法
CN113307222B (zh) * 2020-02-27 2024-05-28 台湾积体电路制造股份有限公司 微机电系统及其制造方法

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