CN110445099B - Semiconductor structure of integrated battery protection circuit and manufacturing process thereof - Google Patents

Abstract

The invention provides a semiconductor structure of an integrated battery protection circuit and a manufacturing process thereof, wherein the battery protection circuit comprises a basic protection circuit, a grid substrate control circuit and a charge-discharge control MOS (metal oxide semiconductor) tube which are integrated on the same semiconductor substrate; the basic protection circuit is used for detecting the charging and discharging conditions of the battery and sending a control signal to the grid substrate control circuit, and the grid substrate control circuit controls the charging and discharging of the battery by controlling the on and off of the charging and discharging control MOS tube according to the received control signal; the grid substrate control circuit comprises a first substrate switching MOS tube and a second substrate switching MOS tube which are used for controlling the substrate voltage of the charge and discharge control MOS tube.

Description

A semiconductor structure with integrated battery protection circuit and its manufacturing process

technical field

The invention relates to the technical field of battery charging, in particular to a semiconductor structure integrating a battery protection circuit and a manufacturing process thereof.

Background technique

In recent years, with the continuous increase of the functions of the mobile terminal, the performance of the mobile terminal is also rapidly improving, which also puts forward higher requirements for the terminal battery. The battery charging and discharging circuits of the prior art are all provided with battery protection circuits. When the battery voltage is overcharged, charging overcurrent and charging overtemperature, battery voltage overdischarge, discharge overcurrent and discharge overtemperature, discharge short circuit and other abnormal conditions, The battery protection circuit will cut off the charging and discharging circuit to protect the battery.

FIG. 1 is a block diagram of a battery protection circuit in the prior art, including a battery, a control circuit A, two power MOS tubes, a charger, a load, a capacitor and a resistor, and the like. Among them, the control circuit A realizes the charge and discharge control of the battery by controlling the gate voltage of the power MOS transistor Mc and the power MOS transistor Md. Due to the large area of the power MOS transistor Mc and the power MOS transistor Md, the battery protection circuit chip will be damaged. The larger the area, the higher the cost. At the same time, the battery protection circuit contains many semiconductor devices, and the peak voltage and DC high voltage generated during the charging and discharging of the battery and the production process are very likely to cause damage to the semiconductor devices. The solution in the prior art is usually to increase the withstand voltage value of the semiconductor device so that it can withstand the peak voltage, but this will greatly increase the area occupied by the semiconductor device on the battery protection circuit chip, and the cost of the battery protection circuit chip will be greatly increased. rise.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present invention is to provide a semiconductor structure with integrated battery protection circuit and a manufacturing process thereof, so as to reduce the area occupied by the semiconductor device on the battery protection circuit chip and reduce the manufacturing cost of the battery protection circuit chip.

The technical scheme provided by the present invention is as follows:

The invention provides a semiconductor structure integrating a battery protection circuit, the battery protection circuit includes a basic protection circuit, a gate substrate control circuit and a charge-discharge control MOS tube integrated on the same semiconductor substrate; the basic protection circuit It is used to detect the charge and discharge of the battery and send a control signal to the gate substrate control circuit, and the gate substrate control circuit controls the charge and discharge control MOS tube to turn on and off according to the received control signal. The gate substrate control circuit includes a first substrate switching MOS transistor and a second substrate switching MOS transistor for controlling the substrate voltage of the charging and discharging control MOS transistor.

Preferably, both the first substrate switching MOS transistor and the second substrate switching MOS transistor are embedded in the charge-discharge control MOS transistor. This can effectively reduce the area occupied by the charge-discharge control MOS transistor, the first substrate switching MOS transistor and the second substrate switching MOS transistor on the battery protection circuit chip, thereby reducing the size of the battery protection circuit chip and reducing battery protection Manufacturing cost of circuit chips. Furthermore, the first substrate switching MOS transistor and the second substrate switching MOS transistor can more truly and accurately reflect the substrate conditions of the charge-discharge control MOS transistor, thereby implementing accurate substrate switching. At the same time, the anti-interference performance of the substrate switching circuit can be improved.

Preferably, the first substrate-switching MOS transistor, the second substrate-switching MOS transistor, and the charge-discharge control MOS transistor include: a first P-type doped region located in the semiconductor substrate, so that the The first P-type doped region is a plurality of MOSFET units formed by a substrate, each of the MOSFET units includes an n-type source region, an n-type drain region and a gate structure, and the first P-type doped region The regions are led out through the first P-type substrate contact regions.

Preferably, the plurality of MOSFET units are divided into three parts and form the first substrate switching MOS transistor, the second substrate switching MOS transistor and the charge and discharge control MOS transistor, respectively. The n-type source region of the switching MOS transistor and the n-type source region of the second substrate switching MOS transistor are both connected to the first P-type substrate contact region, and the first substrate switching MOS transistor has an n-type source region. The drain region is connected to the n-type source region of the charge-discharge control MOS transistor, and the n-type drain region of the second substrate switching MOS transistor is connected to the n-type drain region of the charge-discharge control MOS transistor.

Preferably, the area ratio between the first substrate switching MOS transistor, the charge-discharging control MOS transistor, and the second substrate switching MOS transistor is in the range of 1:4:1 to 1:32:1.

Preferably, the battery protection circuit further includes an over-temperature protection circuit integrated on the semiconductor substrate. By integrating the over-temperature protection circuit and other circuits on the same semiconductor substrate, the temperature of the battery protection circuit chip can be monitored in time, and the battery protection circuit chip can be effectively prevented from being damaged by high temperature.

Preferably, the battery protection circuit further includes a clamping circuit integrated on the semiconductor substrate, and the clamping circuit is used for clamping the power supply voltage of the gate substrate control circuit.

Preferably, the clamping circuit includes N unidirectional series-connected diodes or voltage dividing resistors and N unidirectional series-connected diodes, where N≥1;

When the voltage dividing resistor exists, one end of the resistor is connected to the supply voltage VDD, the other end is connected to the positive end of the N unidirectional series-connected diodes, and the negative end of the N unidirectional series-connected diodes is connected to the VSS end ;

When there are only N unidirectional series-connected diodes, the positive terminals of the N unidirectional series-connected diodes are connected to the supply voltage VDD, and the negative terminals of the N unidirectional series-connected diodes are connected to the VSS terminal.

preferably,

The clamping circuit includes N zener tubes connected in unidirectional series or voltage divider resistors and N zener tubes connected in unidirectional series, wherein N≥1;

When the voltage dividing resistor exists, one end of the voltage dividing resistor is connected to the supply voltage VDD, the other end of the voltage dividing resistor is connected to the negative electrode of the unidirectional series connected Zener, and the positive electrode of the Zener is connected to the VSS terminal ;

When there are only N unidirectional series-connected zeners, the anodes of the N unidirectional series-connected zeners are connected to the supply voltage VDD, and the negative ends of the N unidirectional series-connected zeners are connected to the VSS terminal .

The present invention also provides a manufacturing process of a semiconductor structure integrating a battery protection circuit, comprising:

A semiconductor substrate is provided, a shallow trench isolation structure is formed on the semiconductor substrate, and a control circuit part, a main switch transistor MO and a substrate switching MOS transistor M1/M2 part located in the semiconductor substrate are defined and Zener section;

A first N-type deep well is formed in the main switch transistor M0 and the substrate switching MOS transistors M1/M2, and a second N-type deep well is formed in the control circuit part;

forming a second N-type doped region in the second N-type deep well, and forming a third N-type doped region in the Zener portion;

forming a first P-type doping region in the first N-type deep well, and forming a second P-type doping region in the second N-type deep well;

forming a third N-type heavily doped region in the third N-type doped region;

forming a gate structure of a MOS transistor, and forming a polysilicon resistor on the semiconductor substrate;

A first N-type source region and a first N-type drain region are formed in the first P-type doping region, and a second N-type source region and a second N-type drain region are formed in the second P-type doping region a third N-type heavily doped region and a fourth N-type heavily doped region are formed in the third N-type doped region;

A second P-type source region and a second P-type drain region are formed in the second N-type doped region, a first P-type heavily doped contact region is formed in the first P-type doped region, and a first P-type heavily doped contact region is formed in the first P-type doped region. A third P-type heavily doped contact region is formed in the third N-type doped region;

ion doping is performed to adjust the resistivity of the polysilicon resistor;

Formation of metal silicide for reducing contact resistance;

forming a first insulating dielectric layer, forming a contact hole in the first insulating dielectric layer, then forming a first layer of interconnection metal, and forming a first metal layer of the MIM capacitor at the same time;

forming a dielectric layer and a second metal layer of the MIM capacitor;

A second insulating medium layer is formed, a contact hole is formed in the second insulating medium layer, and then a second layer of interconnection metal is formed.

The semiconductor structure and manufacturing process of the battery protection circuit provided by the invention can effectively reduce the area of the battery protection circuit chip occupied by the semiconductor devices in the battery protection circuit, thereby reducing the size of the battery protection circuit chip and reducing the battery protection circuit. The manufacturing cost of the chip.

Description of drawings

The preferred embodiments will be described below in a clear and easy-to-understand manner with reference to the accompanying drawings, and further description will be given of the above-mentioned characteristics, technical features, advantages and implementations of a semiconductor structure and manufacturing process of a battery protection circuit.

1 is a block diagram of a battery protection circuit in the prior art;

2 is a block diagram of an embodiment of an integrated battery protection circuit of the present invention;

3 is a schematic circuit diagram of an embodiment of the basic protection circuit in FIG. 2;

FIG. 4 is a schematic circuit diagram of an embodiment of the over-temperature protection circuit in FIG. 2;

FIG. 5 is a schematic circuit diagram of an embodiment of the gate substrate control circuit in FIG. 2;

FIG. 6 is a schematic circuit diagram of an embodiment of the clamping circuit in FIG. 2;

FIG. 7 is a schematic circuit diagram of another embodiment of the clamping circuit in FIG. 2;

8 is a schematic top-view structural diagram of an embodiment of the present invention in which both the first substrate switching MOS transistor and the second substrate switching MOS transistor are embedded in the charge-discharge control MOS transistor;

9 is a schematic circuit diagram of an embodiment of the present invention in which both the first substrate switching MOS transistor and the second substrate switching MOS transistor are embedded in the charge-discharge control MOS transistor;

10 to 20 are schematic process flow diagrams of an embodiment of a manufacturing process of a semiconductor structure with integrated battery protection circuit of the present invention.

Detailed ways

In order to more clearly describe the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative efforts, and obtain other implementations.

In order to keep the drawings concise, the drawings only schematically show the parts related to the present invention, and they do not represent its actual structure as a product. In addition, in order to make the drawings concise and easy to understand, in some drawings, only one of the components having the same structure or function is schematically shown, or only one of them is marked. As used herein, "one" not only means "only one", but also "more than one".

FIG. 2 is a block diagram of an embodiment of an integrated battery protection circuit of the present invention. As shown in FIG. 2, an integrated battery protection circuit of the present invention includes: a basic protection circuit, an over-temperature protection circuit, a clamping voltage circuit, Gate substrate control circuit, first logic control unit I12, second logic control unit I13, charge and discharge control MOS tube. One end of the source and drain of the charge and discharge control MOS tube is connected to the negative terminal of the battery, and the other end of the source and drain of the charge and discharge control MOS tube is connected to the negative electrode of the charger; the charge and discharge control MOS tube The gate and substrate are respectively connected to the gate substrate control circuit; the basic protection circuit is used to detect the charge and discharge of the battery and send a control signal to the gate substrate control circuit, the gate substrate The bottom control circuit controls the on and off of the charge and discharge control MOS tube according to the received control signal, so as to control the charge and discharge of the battery.

FIG. 3 is a schematic circuit diagram of an embodiment of the basic protection circuit in FIG. 2. As shown in FIG. 3, the basic protection circuit includes: a reference circuit, a discharge overcurrent comparator, a discharge short circuit comparator, a charge overcurrent comparator, an overcurrent Discharge voltage comparator, overcharge voltage comparator, charge and discharge detection circuit, delay circuit, resistor R1, resistor R2, resistor R3, resistor R4, logic control unit I0, logic control unit I1, logic control unit I2, logic control unit I3 and logic control unit I4.

The reference circuit is used to generate the positive input signal VOC1 of the discharge overcurrent comparator, the positive input signal VSHORT of the discharge short-circuit comparator, the negative input signal VCHOC of the charge overcurrent comparator, the reference output voltages VPN, VOTP, The positive input signal VOCV of the overcharge voltage comparator and the negative input signal VODV of the overdischarge voltage comparator are generated.

The discharge overcurrent comparator is based on the comparison result of the positive input signal VOC1 and the negative input signal virtual ground voltage VM1. When VOC1 is greater than VM1, it outputs a high level VDD, and when VOC1 is lower than VM1, it outputs a low level VGND.

The discharge short-circuit comparator is based on the comparison result of the positive input signal VSHORT and the negative input signal virtual ground voltage VM1. When VSHORT is greater than VM1, it outputs a high level VDD, and when VSHORT is lower than VM1, it outputs a low level VGND.

The charging overcurrent comparator is based on the comparison result of the positive input signal virtual ground voltage VM1 and the negative input signal VCHOC. When VM1 is greater than VCHOC, it outputs a high level VDD, and when VM1 is lower than VCHOC, it outputs a low level VGND.

The overcharge voltage comparator outputs a high level VDD or a low level VGND based on a comparison result of the magnitude of the positive input signal VOCV and the negative input signal VROCV after the VDD voltage is divided by the resistor.

The over-discharge voltage comparator outputs a high-level VDD or a low-level VGND based on the comparison result of the magnitude of the positive input signal VRODV and the negative input signal VODV after the VDD voltage is divided by the resistor.

The charge-discharge detection circuit outputs a high-level VDD or a low-level VGND based on the comparison result between the positive input VGND and the negative input signal VM1. When VGND is greater than VM1, it outputs a high level VDD, and when VGND is lower than VM1, it outputs a low level VGND.

The delay circuit is used for the output signal OC1 of the discharge overcurrent comparator, the output signal SHORT of the discharge short circuit comparator, the output signal CHOC of the charge overcurrent comparator, the output signal ODV of the overdischarge voltage comparator, and the output signal of the overcharge voltage comparator. The signal of the output signal OCV is delayed, and the corresponding output DOC1, DSHORT, DCHOC, DODV, DOCV after the delay. DOC1 is the delayed signal of OC1, DSHORT is the delayed signal of SHORT, DCHOC is the delayed signal of CHOC, DODV is the delayed signal of ODV, and DOCV is the delayed signal of OCV.

When DOC1, DSHORT, DODV are all high, DO3 output is high level VDD, when at least one of DOC1, DSHORT, DODV is low, DO3 output is low level VGND.

When both DCHOC and DOCV are high, CO3 output is high level VDD, when at least one of DCHOC and DOCV is low, CO3 output is low level VGND.

When at least one of DO3 and CH is high, DO2 outputs a high level VDD; when both DO3 and CH are low, DO2 outputs a low level VGND.

When at least one of CO3 and CHN is high, CO2 output is high level VDD, when both CO3 and CHN are low, CO2 output is low level VGND.

FIG. 4 is a schematic circuit diagram of an embodiment of the over-temperature protection circuit in FIG. 2. As shown in FIG. 4, the over-temperature protection circuit includes: an over-temperature comparator, a first logic control unit I14, a second logic control unit I15, The third logic control unit I16. The over-temperature comparator is based on the comparison result of the magnitude of the positive input signal VPN and the negative input signal VOTP. When VPN is greater than VOTP, it outputs a high level, and when VPN is less than VOTP, it outputs a low level. When at least one of OTP and CHN is high, the CHOTP output is high level VDD, and when both OTP and CHN are low, the CHOTP output is low. When at least one of OTP and CH is high, DISOTP output is high level VDD, when both OTP and CH are low, DISOTP output is low.

FIG. 5 is a schematic circuit diagram of an embodiment of the gate substrate control circuit in FIG. 2 . As shown in FIG. 5 , the positive power supply voltage of the gate substrate control circuit is the output potential GVDD of the clamping circuit, and the input voltage DO is It may be high-level VDD or low-level VGND, GVDD~VDD, and the voltage of GVDD~VGND may exceed the gate breakdown voltage of MOS transistors M7 and M8 to damage MOS transistors M7 and M8. Add R11, M21, R12, M22 The maximum voltage from GATE to GVDD of M7 and M8 is the parasitic diode voltage of M21 and M22, and the parasitic diode voltage will not damage the MOS tube. Similarly: R13, R14, M23, M24 protect M11, M12 from damage; R15, R16, M25, M26 protect M15, M16 from damage. The gate substrate control circuit also includes a first substrate switching MOS transistor M1 and a second substrate switching MOS transistor M2 for controlling charge and discharge to control the voltage of the MOS transistor substrate, and the first substrate switching MOS transistor M1 and the second substrate switching MOS transistor M2 The substrate switching MOS transistor M2 outputs the substrate voltage VSUB of the charge and discharge control MOS transistor. The gate substrate control circuit also outputs the gate voltage VGATE of the charge-discharge control MOS transistor.

FIG. 6 is a schematic circuit diagram of an embodiment of the clamping circuit in FIG. 2. As shown in FIG. 6, the clamping circuit may include a voltage dividing resistor R5 and a Zener tube Z0, or only the Zener tube Z0, or Connect several Zener tubes in series. The connection terminal of the voltage dividing resistor R5 and the Zener transistor Z0 is the output terminal GVDD, the other end of the voltage dividing resistor R5 is connected to the power supply voltage VDD, and the other end of the Zener transistor is connected to the VSS terminal. The principle that the clamping circuit clamps the voltage between GVDD and VSS within a preset range is: the resistance of the PN junction of the Zener is extremely low in the reverse breakdown state, so when the Zener is turned on, the GVDD The ~VSS voltage is equal to the breakdown voltage of the Zener; when the Zener is not conducting, GVDD is almost equal to VDD.

When the voltage of VDD-VSS is lower than the turn-on voltage of the Zener, GVDD is equal to VDD; when the voltage of VDD-VSS is higher than the turn-on voltage of the Zener, the highest output voltage of GVDD-VSS is the Zener voltage. Generally, the turn-on voltage of the Zener tube inside the chip is 4 to 9V, and the turn-on voltage of the currently used Zener tube is 6.3V. Then the output voltage of GVDD~VSS is up to 6.3V. If the voltage of VDD~VSS continues to increase, the Zener voltage is stable at 6.3V, and the rest of the voltage is dropped on the resistor R5, and there is no problem with the voltage drop of several tens of volts on the resistor R5; therefore, the withstand voltage of VDD~VSS is as high as Dozens of volts won't damage the clamp circuit. The power supply voltage of the gate substrate control circuit is the voltage of GVDD˜VSS, and the maximum value is the turn-on voltage of the Zener (ie, 6.3V). The gate substrate control circuit will not be damaged when the VDS breakdown voltage of the PMOS tube is lower than 7V to 14V.

FIG. 7 is a schematic circuit diagram of another embodiment of the clamping circuit in FIG. 2 . As shown in FIG. 7 , the clamping circuit may include a voltage dividing resistor R5 and N unidirectional series-connected diodes, or only N single diodes. To the diode in series, that is, the resistor R5 is 0. Wherein: N≥1; one end of the voltage dividing resistor R5 is connected to the supply voltage VDD, and the other end of the voltage dividing resistor R5 is connected to the negative end of the N unidirectional series-connected diodes. The positive terminal of the series connected diode is connected to the VSS terminal. The principle that multiple diodes in series can clamp the voltage between GVDD and VSS within a preset range is: using the constant characteristics of the forward conduction voltage of the diodes, when the diodes are turned on, the GVDD~VSS voltage is equal to the conduction of multiple diodes. Sum of voltages; GVDD is almost equal to VDD when the diode is not conducting.

8 is a schematic top-view structural diagram of an embodiment of the present invention in which both the first substrate switching MOS transistor M1 and the second substrate switching MOS transistor M2 in the gate substrate control circuit are embedded in the charge-discharge control MOS transistor MO, 9 is a schematic circuit diagram of an embodiment of the present invention in which both the first substrate switching MOS transistor M1 and the second substrate switching MOS transistor M2 in the gate substrate control circuit are embedded in the charge-discharge control MOS transistor MO. Both the first substrate switching MOS transistor M1 and the second substrate switching MOS transistor M2 are embedded in the charge-discharge control MOS transistor MO, so that the first substrate switching MOS transistor and the second substrate switching MOS transistor can more truly and accurately reflect the charge and discharge. Control the substrate condition of the MOS tube to implement accurate substrate switching. At the same time, the anti-interference performance of the substrate switching circuit can be improved.

As shown in FIG. 8 and FIG. 9 , the first substrate switching MOS transistor M1, the second substrate switching MOS transistor M2 and the charge and discharge control MOS transistor M0 include: a first P-type doped region located in the semiconductor substrate to The first P-type doped region is a plurality of MOSFET units formed by a substrate, each MOSFET unit includes an n-type source region, an n-type drain region and a gate structure, and the first P-type doped region Lead out through the first P-type substrate contact area. The plurality of MOSFET units are divided into three parts and respectively form a first substrate switching MOS transistor M1, a second substrate switching MOS transistor M2 and a charge and discharge control MOS transistor M0, and the n-type source of the first substrate switching MOS transistor M1 region, the n-type source region of the second substrate switching MOS transistor M2 and the first p-type substrate contact region are connected to the SUB terminal, the n-type drain region of the first substrate switching MOS transistor M1 is connected to the charge and discharge control MOS transistor The n-type source region of M0 is connected to the B-end, and the n-type drain region of the second substrate switching MOS transistor and the n-type drain region of the charge-discharge control MOS transistor are connected to the P-end.

By controlling the number of MOSFET units included in the first substrate switching MOS transistor M1, the charging and discharging control MOS transistor M0, and the second substrate switching MOS transistor M2, the first substrate switching MOS transistor M1 and the charging and discharging control MOS transistor can be controlled. M0, the size of the area of the second substrate switching MOS transistor M2, preferably, the area ratio between the first substrate switching MOS transistor M1, the charge and discharge control MOS transistor M0, and the second substrate switching MOS transistor M2 is 1: 4:1 to 1:32:1 range.

FIG. 8 exemplarily shows two cell structures in the first substrate switching MOS transistor M1, the charge and discharge control MOS transistor M0, and the second substrate switching MOS transistor M2, wherein the first substrate switching MOS transistor M1 includes 2 MOSFET units, the second substrate switching MOS transistor M2 includes 2 MOSFET units, and the charge and discharge control MOS transistor M0 includes 16 MOSFET units. The area ratio between the control MOS transistor M0 and the second substrate switching MOS transistor M2 is: 2:16:2=1:8:1.

When an abnormal phenomenon occurs during the charging and discharging of the battery, the first substrate switching MOS transistor M1 and the second substrate switching MOS transistor M2 can timely control the substrate voltage of the charging and discharging control MOS transistor MO, thereby controlling the charging and discharging control MOS transistor MO The conduction condition of the battery is controlled, and the entire charge and discharge circuit is controlled to ensure the safety of the battery charge and discharge.

Both the first substrate switching MOS tube and the second substrate switching MOS tube are embedded in the charge and discharge control MOS tube, which can effectively reduce the charge and discharge control MOS tube, the first substrate switching MOS tube and the second substrate switching MOS tube in the battery. The area occupied by the protection circuit chip. At the same time, the area ratio between the first substrate switching MOS transistor, the charge and discharge control MOS transistor, and the second substrate switching MOS transistor is set within an appropriate range, which can take into account the cost of the battery protection circuit chip and the stability of the battery protection circuit. sex.

In other embodiments of the present application, the first substrate-switching MOS transistor and the second substrate-switching MOS transistor are evenly embedded in the charge-discharge control MOS transistor, which can increase the withstand voltage as much as possible and have a high reverse breakdown voltage.

The invention integrates the basic protection circuit, the gate substrate control circuit, the charge and discharge control MOS tube, the over-temperature protection circuit and the clamping voltage circuit on the same semiconductor substrate, which can effectively reduce the size of the battery protection circuit chip and reduce the battery protection circuit The manufacturing cost of the chip can be reduced, and the internal resistance of the battery protection circuit chip can be reduced.

The present invention also provides a manufacturing process of a semiconductor structure with an integrated battery protection circuit. FIGS. 10 to 20 are process flow diagrams of an embodiment of the manufacturing process of a semiconductor structure with an integrated battery protection circuit provided by the present invention. Steps include:

First, as shown in FIG. 10 , a semiconductor substrate 100 is provided, the semiconductor substrate 100 is p-type doped, a shallow trench isolation structure 101 is formed on the semiconductor substrate 100 , and a control in the semiconductor substrate 100 is defined The circuit part, the main switch tube and the substrate switch the MOS tube part and the Zener tube part. FIG. 10 exemplarily shows the structure of the CMOS part (including the PMOS part and the NMOS part), the resistance part and the capacitor part of the control circuit, as well as the structure of the main switch transistor M0 and the substrate switching MOS transistor M1/M2 and the Zener The structure of the tube section.

Next, as shown in FIG. 11 , a pattern is formed by a photolithography process, and then n-type ion implantation is performed to form a first N-type deep well 11 in the structural positions of the PMOS part and the NMOS part, and the main switch transistors M0 and A second N-type deep well 21 is formed at the structural position of the substrate switching MOS transistors M1/M2.

Next, as shown in FIG. 12 , a pattern is first formed by a photolithography process, and then n-type ion implantation is performed to form a second N-type doped region 22 in the second N-type deep well 21, and in the Zener part A third N-type doped region 32 is formed at the structural position of .

Next, as shown in FIG. 13 , a pattern is first formed by a photolithography process, and then p-type ion implantation is performed. A first P-type doping region 12 is performed in the first N-type deep well 11 , and a second N-type deep well 12 is formed. A second P-type doped region 23 is formed in the well 21 .

Next, as shown in FIG. 14 , a pattern is first formed by a photolithography process, and then n-type ion implantation is performed to form a third N-type heavily doped region 33 in the third N-type doped region 32 .

Next, as shown in FIG. 15 , gate structures are formed on the first P-type doping region 12 , the second P-type doping region 23 , and the second N-type doping region 22 , respectively, and the semiconductor substrate 100 is formed. A polysilicon resistor 106 is formed thereon. Wherein, each gate includes a gate dielectric layer 102, a polysilicon gate 104, and gate spacers 103 located on both sides of the polysilicon gate.

Next, as shown in FIG. 16 , a pattern is first formed by a photolithography process, and then n-type ion implantation is performed to form a first N-type source region 13 and a first N-type drain region 14 in the first P-type doped region 12 , a second N-type source region 24 and a second N-type drain region 25 are formed in the second P-type doped region 23 , and a third N-type heavily doped region 34 and a second N-type heavily doped region 34 are formed in the third N-type doped region 32 Four N-type heavily doped regions 35 .

Next, as shown in FIG. 17 , a pattern is first formed by a photolithography process, and then p-type ion implantation is performed to form a second P-type source region 26 and a second P-type drain region 27 in the second N-type doped region 22 A first P-type heavily doped contact region 15 is formed in the first P-type doped region 12 , and a third P-type heavily doped contact region 36 is formed in the third N-type doped region 32 .

Next, as shown in FIG. 18, n-type ion doping is performed to adjust the resistivity of the polysilicon resistor 106; then a pattern is formed by a photolithography process, and then a metal silicide 201 for reducing contact resistance is formed.

Next, as shown in FIG. 19 , a first insulating dielectric layer 107 is deposited and formed, then a contact hole is formed in the first insulating dielectric layer 107, and then a metal layer is deposited and a first insulating layer is formed by a photolithography process and an etching process. A layer of interconnection metal 108 is formed. In this step, a first metal layer 301 of an MIM capacitor (Metal-Insulator-Metal Capacitor) is formed on the first insulating dielectric layer 107 at the same time.

Next, as shown in FIG. 20, the dielectric layer 302 of the MIM capacitor is formed, and then a second insulating dielectric layer 109 is deposited to form a contact hole in the second insulating dielectric layer 109, and then a metal layer is deposited and light is passed through. The etching process and the etching process form the second layer of interconnect metal 200 .

FIG. 20 is a specific embodiment of the finally completed battery protection circuit. Corresponding to FIG. 2 , from left to right in FIG. 20 are the CMOS (including the PMOS part and the NMOS part) part, the resistor part, the capacitor part, the main switch M0 and the substrate switching MOS transistor M1/M2 part and the Zener part. . The CMOS parts in the basic protection circuit, the over-temperature protection circuit and the gate substrate control circuit in FIGS. 2-5 are all formed by the CMOS part in FIG. 20 . All the resistors in Figs. 2-7 including the resistors in the clamping circuits in Figs. 6 and 7 are formed by the resistor portion in Fig. 20 . All capacitors in Figures 2-7 are formed from the capacitor section in Figure 20. The Zener tube in FIG. 6 is formed from the Zener tube part in FIG. 20 . The diode in FIG. 7 may be formed by selecting one of the PN junctions in FIG. 20 .

It should be noted that there should be a lot of MOS transistors in the control circuit part, but for the convenience of presentation, only one NMOS transistor and one PMOS transistor are illustrated in FIGS. 10-20 . Multiple NMOS transistors and multiple PMOS transistors can be simultaneously formed as required. At the same time, when both the first substrate switching MOS transistor and the second substrate switching MOS transistor are embedded in the charge-discharge control MOS transistor, there should be many MOSFET units in the PMOS part and the NMOS part, but for convenience of display, in Figure 10-Figure 20 only exemplarily shows the manufacturing process of one MOSFET unit. In actual manufacturing, according to the set area ratio of the first substrate switching MOS transistor, the second substrate switching MOS transistor, and the charge and discharge control MOS transistor, A set number of MOSFET cells can be fabricated simultaneously.

It should be noted that the above embodiments can be freely combined as required. The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.

Claims (7)

1. A semiconductor structure of an integrated battery protection circuit is characterized in that the battery protection circuit comprises a basic protection circuit, a grid substrate control circuit and a charge-discharge control MOS tube which are integrated on the same semiconductor substrate;

the basic protection circuit is used for detecting the charging and discharging conditions of the battery and sending a control signal to the grid substrate control circuit, and the grid substrate control circuit controls the charging and discharging of the battery by controlling the on and off of the charging and discharging control MOS tube according to the received control signal;

the grid substrate control circuit comprises a first substrate switching MOS tube and a second substrate switching MOS tube which are used for controlling the substrate voltage of the charge and discharge control MOS tube;

the first substrate switching MOS tube and the second substrate switching MOS tube are embedded into the charge and discharge control MOS tube;

the first substrate switching MOS transistor, the second substrate switching MOS transistor, and the charge and discharge control MOS transistor include: the semiconductor device comprises a semiconductor substrate, a first P-type doped region, a plurality of MOSFET units, a second P-type doped region and a gate structure, wherein the first P-type doped region is positioned in the semiconductor substrate;

the MOSFET units are divided into three parts and respectively form the first substrate switching MOS tube, the second substrate switching MOS tube and the charge and discharge control MOS tube, an n-type source region of the first substrate switching MOS tube and an n-type source region of the second substrate switching MOS tube are connected with the first P-type substrate contact region, an n-type drain region of the first substrate switching MOS tube is connected with an n-type source region of the charge and discharge control MOS tube, and an n-type drain region of the second substrate switching MOS tube is connected with an n-type drain region of the charge and discharge control MOS tube.

2. The semiconductor structure of an integrated battery protection circuit of claim 1, wherein: the area ratio of the first substrate switching MOS tube to the charge-discharge control MOS tube to the second substrate switching MOS tube is in the range of 1:4:1 to 1:32: 1.

3. The semiconductor structure of an integrated battery protection circuit of claim 1, wherein: the battery protection circuit also includes an over-temperature protection circuit integrated on the semiconductor substrate.

4. The semiconductor structure of an integrated battery protection circuit of claim 1, wherein: the battery protection circuit also includes a voltage clamping circuit integrated on the semiconductor substrate.

5. The semiconductor structure of an integrated battery protection circuit of claim 4, wherein: the clamping circuit comprises N diodes which are connected in series in a unidirectional mode or a divider resistor and N diodes which are connected in series in a unidirectional mode, wherein N is larger than or equal to 1;

when the voltage dividing resistor exists, one end of the voltage dividing resistor is connected to a power supply voltage VDD, the other end of the voltage dividing resistor is connected to the positive ends of the N unidirectional series-connected diodes, and the negative ends of the N unidirectional series-connected diodes are connected to a VSS end;

when only N unidirectional series diodes are arranged, the positive ends of the N unidirectional series diodes are connected to the power supply voltage VDD, and the negative ends of the N unidirectional series diodes are connected to the VSS end.

6. The semiconductor structure of an integrated battery protection circuit of claim 4, wherein: the clamping circuit comprises N Zener tubes which are connected in series in a unidirectional mode or a divider resistor and N Zener tubes which are connected in series in a unidirectional mode, wherein N is more than or equal to 1;

when the voltage dividing resistor exists, one end of the voltage dividing resistor is connected to a power supply voltage VDD, the other end of the voltage dividing resistor is connected to the cathode of the Zener tube which is connected in series in a unidirectional mode, and the anode of the Zener tube is connected to a VSS end;

when only N Zener tubes are connected in series in a unidirectional mode, the positive electrodes of the N Zener tubes connected in series in the unidirectional mode are connected to a power supply voltage VDD, and the negative stages of the N Zener tubes connected in series in the unidirectional mode are connected to a VSS end.

7. A process for manufacturing a semiconductor structure of an integrated battery protection circuit according to claim 1, wherein: the method comprises the following steps:

providing a semiconductor substrate, forming a shallow trench isolation structure on the semiconductor substrate, and defining a control circuit part, a main switch tube MO, a substrate switching MOS tube M1/M2 part and a Zener tube part which are positioned in the semiconductor substrate;

a first N-type deep well is formed in the main switching transistor M0 and the substrate switching MOS transistor M1/M2, and a second N-type deep well is formed in the control circuit part;

forming a second N-type doped region in the second N-type deep well, and forming a third N-type doped region in the Zener pipe part;

carrying out a first P-type doped region in the first N-type deep well, and forming a second P-type doped region in the second N-type deep well;

forming a third N-type heavily doped region in the third N-type doped region;

forming a grid structure of an MOS tube, and forming a polysilicon resistor on the semiconductor substrate;

forming a first N-type source region and a first N-type drain region in the first P-type doped region, forming a second N-type source region and a second N-type drain region in the second P-type doped region, and forming a third N-type heavily doped region and a fourth N-type heavily doped region in the third N-type doped region;

forming a second P-type source region and a second P-type drain region in the second N-type doped region, forming a first P-type heavily doped contact region in the first P-type doped region, and forming a third P-type heavily doped contact region in the third N-type doped region;

carrying out ion doping, and adjusting the resistivity of the polysilicon resistor;

forming a metal silicide for reducing contact resistance;

forming a first insulating dielectric layer, forming a contact hole in the first insulating dielectric layer, then forming a first layer of interconnection metal, and simultaneously forming a first metal layer of the MIM capacitor;

forming a dielectric layer and a second metal layer of the MIM capacitor;

and forming a second insulating medium layer, forming a contact hole in the second insulating medium layer, and then forming a second layer of interconnection metal.

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