CN111524885B - Power integrated circuit chip and manufacturing method thereof - Google Patents

Abstract

The application provides a power integrated circuit chip and a manufacturing method thereof, and relates to the technical field of semiconductors. The power integrated circuit chip comprises an N-type substrate, a P-type structure positioned at the periphery and the bottom of the N-type substrate and an active area positioned on the surface of the N-type substrate; the N-type substrate, the P-type structure and the active region form a unidirectional thyristor, a first diode and a second diode together, and a long base region and a short base region of the unidirectional thyristor are connected with the first diode and the second diode respectively. The power integrated circuit chip and the manufacturing method thereof provided by the application have the advantages of better consistency of devices and lower cost.

Description

A power integrated circuit chip and its manufacturing method

Technical Field

The present application relates to the field of semiconductor technology, and in particular to a power integrated circuit chip and a method for manufacturing the same.

Background technique

With the advent of the 5G communication era, there will be more and more communication base station equipment, and the reliability requirements for communication systems will become higher and higher. Once the communication system fails, it will cause communication interruption, equipment failure, large losses, and even cause information security accidents. Among them, lightning strikes are the main cause of communication system failures.

Based on this, overvoltage protection is generally performed in communication systems. The traditional protection solution is to use multiple single-channel components in parallel. This solution is costly and will not provide protection if the consistency between components is poor.

In summary, the current overvoltage protection has the problems of high cost and poor consistency between components.

Summary of the invention

The purpose of the present application is to provide a power integrated circuit chip and a method for manufacturing the same, so as to solve the problems of high overvoltage protection cost and poor consistency between components in the prior art.

On the one hand, an embodiment of the present application provides a power integrated circuit chip, the power integrated circuit chip comprising:

N-type substrate;

A P-type structure located around and at the bottom of the N-type substrate; and

An active region located on the surface of the N-type substrate; wherein,

The N-type substrate, the P-type structure and the active area together constitute a unidirectional thyristor, a first diode and a second diode, and the long base region and the short base region of the unidirectional thyristor are connected to the first diode and the second diode respectively.

Furthermore, the active region comprises:

a first electrode located on the surface of the N-type substrate, a first P-type region located on the surface of the N-type substrate, a first N-type region located below the first P-type region, a second N-type region located within the first P-type region, a second P-type region located on the surface of the N-type substrate, a third N-type region located within the second P-type region, a second electrode, a third electrode, and an interconnect metal layer, wherein:

The second N-type region is connected to the second electrode, the first P-type region is connected to the third N-type region through the interconnect metal layer, and the second P-type region is connected to the third electrode;

The first electrode, the N-type substrate and the P-type structure constitute a first diode;

The N-type substrate, the P-type structure, the first P-type region, the first N-type region, and the second N-type region constitute the unidirectional thyristor, and the first N-type region is used to adjust the trigger voltage of the unidirectional thyristor;

The second P-type region, the third N-type region and the third electrode constitute the second diode;

The power integrated circuit chip further includes a fourth electrode, and the fourth electrode is located at the bottom of the P-type structure.

Furthermore, the power integrated circuit chip also includes a first heavily doped region, the first heavily doped region is located in the N-type substrate, the conductivity type of the first heavily doped region is N-type, and the N-type substrate is in ohmic contact with the first electrode through the first heavily doped region.

Furthermore, the power integrated circuit chip also includes a second heavily doped region, the second heavily doped region is located in the first P-type region, the conductivity type of the second heavily doped region is P-type, and the first P-type region is in ohmic contact with the interconnect metal layer through the second heavily doped region.

Furthermore, the second N-type region is a heavily doped region, and an ohmic contact is established between the second N-type region and the second electrode.

Furthermore, a short-circuit hole is provided in the second N-type region.

On the other hand, an embodiment of the present application further provides a method for manufacturing a power integrated circuit chip, which is used to manufacture the above-mentioned power integrated circuit chip, and the method includes:

Providing an N-type substrate;

A P-type structure is fabricated at the bottom of the N-type substrate, and an active region is fabricated on the surface of the N-type substrate; wherein the N-type substrate, the P-type structure and the active region together constitute a unidirectional thyristor, a first diode and a second diode, and a long base region and a short base region of the unidirectional thyristor are respectively connected to the first diode and the second diode.

Furthermore, the step of manufacturing a P-type structure at the bottom of the N-type substrate and manufacturing an active area on the surface of the N-type substrate includes:

Preprocessing the N-type substrate;

Performing photolithography on the N-type substrate to form a P-type structure around and at the bottom of the N-type substrate;

Photolithography and diffusion are performed on the surface of the N-type substrate to form an active region on the surface of the N-type substrate.

Furthermore, the step of performing photolithography and diffusion on the surface of the N-type substrate to form an active area on the surface of the N-type substrate includes:

Performing a first photolithography on the surface of the N-type substrate to form a pattern of a first N-type region;

Performing ion implantation on the pattern of the first N-type region and forming the first N-type region by high temperature diffusion;

Performing a second photolithography on the surface of the N-type substrate to form patterns of a first P-type region and a second P-type region;

Performing ion implantation on the patterns of the first P-type region and the second P-type region, and forming the first P-type region and the second P-type region by high temperature diffusion;

Performing a third photolithography on the surface of the N-type substrate to form a pattern of a second N-type region;

Performing liquid source diffusion on the pattern of the second N-type region and forming the second N-type region by high temperature diffusion;

Performing a fourth photolithography on the surface of the N-type substrate to form a pattern of a third N-type region;

Performing ion implantation on the pattern of the third N-type region, and forming the third N-type region by high temperature diffusion;

Fabricate electrodes.

Compared with the prior art, this application has the following beneficial effects:

The present application provides a power integrated circuit chip and a method for manufacturing the same, wherein the power integrated circuit chip comprises an N-type substrate, a P-type structure located around and at the bottom of the N-type substrate, and an active area located on the surface of the N-type substrate; wherein the N-type substrate, the P-type structure, and the active area together constitute a unidirectional thyristor, a first diode, and a second diode, and the long base region and the short base region of the unidirectional thyristor are respectively connected to the first diode and the second diode. Since the power integrated circuit chip provided by the present application integrates a thyristor and two diodes on the same N-type substrate, the consistency of multiple devices is improved through integration. At the same time, multiple devices can be manufactured based on one N-type substrate during the manufacturing process, and the cost is reduced.

In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of the structure of a power integrated circuit chip provided in an embodiment of the present application.

FIG. 2 is another schematic diagram of the structure of a power integrated circuit chip provided in an embodiment of the present application.

FIG3 is an equivalent circuit diagram of a power integrated circuit chip provided in an embodiment of the present application.

FIG. 4 is a schematic diagram of the packaging of a power integrated circuit chip provided in an embodiment of the present application.

FIG5 is a flow chart of a method for manufacturing a power integrated circuit chip provided in an embodiment of the present application.

FIG. 6 is a flowchart of the sub-steps of S102 in FIG. 5 provided in an embodiment of the present application.

FIG. 7 is a flowchart of sub-steps of S102 - 3 in FIG. 6 provided in an embodiment of the present application.

FIG8 is a circuit diagram of a bidirectional overvoltage protection circuit provided in an embodiment of the present application.

In the figure: 100-power integrated circuit chip; 1-N-type substrate; 2-P-type structure; 21-third P-type region; 22-P-type penetration region; 3-active region; 31-first P-type region; 32-first N-type region; 33-second N-type region; 34-second P-type region; 35-third N-type region; 36-first electrode; 37-second electrode; 38-third electrode; 39-interconnect metal layer; 40-first heavily doped region; 41-second heavily doped region; 4-fourth electrode.

Detailed ways

In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

In the description of the present application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

First embodiment

As described in the background art, in order to prevent a communication system failure caused by a lightning surge, generally, an overvoltage protection circuit is provided in the communication system.

The traditional protection solution is to use multiple single-channel components in parallel, but this solution is costly and will not provide protection if the consistency between components is poor. Another solution is to use multiple overvoltage protection devices with programmable functions in parallel. Although this can solve the consistency problem, traditional programmable overvoltage protection devices are complex to manufacture and have poor lightning surge resistance.

In view of this, in order to solve the problems of high cost, complex device manufacturing and poor consistency in the overvoltage protection circuit in the prior art, the present application provides a power integrated circuit chip, which reduces the device cost and improves the consistency between devices by integrating multiple devices on the same substrate.

The following is an exemplary description of the power integrated circuit chip provided by the present application:

As an optional implementation method, referring to Figure 1, the power integrated circuit chip 100 provided in the present application may include an N-type substrate 1, a P-type structure 2 located around and at the bottom of the N-type substrate, and an active area 3 located on the surface of the N-type substrate; wherein the N-type substrate, the P-type structure 2 and the active area 3 together constitute a unidirectional thyristor, a first diode and a second diode, and the long base region and the short base region of the unidirectional thyristor are respectively connected to the first diode and the second diode.

By integrating the unidirectional thyristor, the first diode and the second diode on the same N-type substrate, it is possible to reduce costs and improve consistency between devices.

In addition, the active region 3 provided in the present application includes a first electrode 36 located on the surface of the N-type substrate, a first P-type region 31 located on the surface of the N-type substrate, a first N-type region 32 located at the bottom of the first P-type region 31, a second N-type region 33 located in the first P-type region 31, a second P-type region 34 located on the surface of the N-type substrate, a third N-type region 35 located in the second P-type region 34, a second electrode 37, a third electrode 38 and an interconnecting metal layer 39, wherein the second N-type region 33 is connected to the second electrode 37, and the first P-type region 31 and the third N-type region 35 are connected through the interconnecting metal layer 39 is connected, the second P-type region 34 is connected to the third electrode 38; the first electrode 36, the N-type substrate and the P-type structure 2 constitute a first diode; the N-type substrate, the P-type structure 2, the first P-type region 31, the first N-type region 32, and the second N-type region 33 constitute a unidirectional thyristor, and the first N-type region 32 is used to adjust the trigger voltage of the unidirectional thyristor; the second P-type region 34, the third N-type region 35 and the third electrode 38 constitute a second diode; at the same time, the cathode of the first diode is connected to the long base region of the unidirectional thyristor, and the cathode of the second diode is connected to the short base region of the unidirectional thyristor. In addition, the power integrated circuit chip 100 also includes a fourth electrode 4, which is located at the bottom of the P-type structure 2.

As an optional implementation, the N-type substrate may be an N-type substrate silicon wafer. It is understandable that a PN junction is formed between the N-type substrate and the P-type region. In this application, a first electrode 36 is provided on the surface of the N-type substrate. The first diode provided by the application is composed of an N-type substrate, a P-type region and a first electrode 36. The voltage of the first diode can be adjusted by adjusting the resistivity of the N-type substrate. Generally, the voltage requirement of the first diode is higher than 100V.

It should be noted that the P-type region provided in the present application actually includes a third P-type region 21 located at the bottom of the N-type substrate and a P-type penetration region 22 located around the N-type substrate, which can be formed simultaneously during the manufacturing process, and the two have the same doping concentration. In addition, since the P-type penetration region 22 surrounds the entire active region 3, the P-type penetration region 22 can also play an isolating role in the circuit layout, isolating the active region 3 from other devices, thereby achieving stable operation of the circuit.

At the same time, as an optional implementation, the first P-type region 31 and the second P-type region 34 are formed by diffusion at the same time, so that the concentrations of the two regions are consistent.

By adjusting the doping concentration and junction depth of the first N-type region 32 , the trigger voltage of the unidirectional thyristor can be adjusted. The trigger voltage is generally required to be higher than 100V.

It should be noted that the junction depth of the second N-type region 33 is smaller than the junction depth of the first P-type region 31. As an implementation method, a short-circuit hole is provided in the second N-type region 33, and the second N-type region 33 is a heavily doped region, so that when the second N-type region 33 is connected to the second electrode 37, the two can achieve ohmic contact.

Furthermore, the junction depth of the third N-type region 35 is smaller than the junction depth of the second P-type region 34 .

At the same time, in order to protect the active area 3, a passivation layer is also provided on the top of the power integrated circuit chip 100 provided in the present application. As an optional implementation, the material of the passivation layer can be silicon dioxide.

In order to better realize ohmic contact, please refer to FIG. 2 , the power integrated circuit chip 100 provided in the present application further includes a first heavily doped region 40, the first heavily doped region 40 is located in the N-type substrate, the conductivity type of the first heavily doped region 40 is N-type, and the N-type substrate is in ohmic contact with the first electrode 36 through the first heavily doped region 40. Since the second N-type region 33 is also a heavily doped N-type region, as an optional implementation method, the first heavily doped region 40 and the second N-type region 33 can be diffused and formed at the same time, and the third N-type region 35 is diffused and formed separately according to voltage requirements.

At the same time, the power integrated circuit chip 100 also includes a second heavily doped region 41, which is located in the first P-type region 31, and the conductivity type of the second heavily doped region 41 is P-type, and the first P-type region 31 is in ohmic contact with the interconnection metal layer 39 through the second heavily doped region 41, and the interconnection metal layer 39 is also connected to the third N-type region 35, and then the second heavily doped region 41 is connected to the third N-type region 35 through the interconnection metal layer 39, that is, the connection between the unidirectional thyristor and the second diode is realized. As an optional implementation method, the interconnection metal layer 39 can be made of aluminum material.

Furthermore, the second P-type region 34 is also connected to the third electrode 38 , and the fourth electrode 4 is located at the bottom of the P-type structure 2 .

The power integrated circuit chip 100 manufactured by the above structure can form a first diode through the N-type substrate, the P-type structure 2 and the first heavily doped region 40, form a second diode through the second P-type region 34 and the third N-type region 35, and form a unidirectional thyristor through the N-type substrate, the P-type structure 2, the first N-type region 32, the first P-type region 31 and the second N-type region 33.

Among them, the cathode of the first diode is connected to the long base region of the thyristor through a common N-type substrate, so the cathode metal electrode of the first diode (i.e., the first electrode 36) is the long base region driving gate of the unidirectional thyristor, and this gate is the first trigger gate of the unidirectional thyristor, and this gate is used to drive the negative signal; the cathode of the second diode is connected to the short base region of the unidirectional thyristor through the interconnection metal layer 39, so the anode metal of the second diode (i.e., the third electrode 38) is the second trigger gate of the unidirectional thyristor, and this gate is used to drive the positive signal. The second electrode 37 is the cathode electrode of the unidirectional thyristor, and the fourth electrode 4 is the anode electrode of the unidirectional thyristor.

Preferably, the power integrated circuit chip 100 provided by the present application can conveniently adjust the breakdown voltage values of different regions, thereby achieving a wider voltage protection range. By adjusting the impurity concentration and junction depth of the first N-type region 32 in the unidirectional thyristor, the voltage of the Zener diode formed by the first P-type region 31 and the first N-type region 32 can be adjusted, thereby adjusting the trigger voltage of the unidirectional thyristor; the first diode voltage can be adjusted by adjusting the resistivity of the N-type substrate; and the second diode voltage can be adjusted by adjusting the impurity concentration and junction depth of the second P-type region 34.

Based on the above structure, FIG3 shows the equivalent circuit original diagram of the power integrated circuit chip 100, wherein two transistors together constitute a unidirectional thyristor. Among them, D1 represents the first diode, D2 represents the second diode, and the two transistors together constitute the unidirectional thyristor. The A pin is the anode of the chip, the K pin is the cathode of the chip, G1 is the first trigger gate of the chip, and G2 is the second trigger gate of the chip.

Moreover, in practical applications, referring to FIG. 4 , the power integrated circuit chip 100 provided by the present application can be placed in a SOP8 package, and the lead pins are G1, G2, A, and K. In a bidirectional protection application where multiple SLIC lines are connected in parallel, the protection IC formed can be used in combination with a diode rectifier bridge to realize overvoltage protection of multiple SILC chips, and the solution is simple.

In summary, the power integrated circuit chip provided in the present application has the characteristics of convenient voltage adjustment, high integration, high consistency between devices, strong surge resistance, bidirectional positive and negative signals can be triggered, and bidirectional voltage is programmable.

Second embodiment

Based on the above embodiments, the present application also provides a method for manufacturing a power integrated circuit chip. Please refer to FIG5 . The method includes:

S101, providing an N-type substrate.

S102, making a P-type structure at the bottom of the N-type substrate, and making an active area on the surface of the N-type substrate; wherein the N-type substrate, the P-type structure and the active area together constitute a unidirectional thyristor, a first diode and a second diode, and the long base region and the short base region of the unidirectional thyristor are respectively connected to the first diode and the second diode.

This application is described by taking N-type as N-type and P-type as P-type as an example. As an implementation method, the N-type substrate can be made of N-type material with a resistivity of ρ=30-50Ω/cm, and the initial material sheet thickness is 260±10um.

Wherein, referring to FIG. 6 , S102 includes:

S102-1, pre-processing the N-type substrate.

S102-2, photolithography is performed on the N-type substrate to form a P-type structure around and at the bottom of the N-type substrate.

S102-3, performing photolithography and diffusion on the surface of the N-type substrate to form an active region on the surface of the N-type substrate.

Since the back of the N-type substrate provided in the present application needs to be made into a P-type structure and the surface needs to be made into an active area, both the front and back sides of the N-type substrate need to be processed during pretreatment. As an implementation method, the silicon wafer can be chemically etched first, and then both sides of the N-type substrate can be polished using a polishing machine. The thickness of the polished N-type substrate is 200±10um.

After pre-treating the N-type substrate, the N-type substrate needs to be cleaned and wet-oxidized at 1100-1180° C. for 3-5 hours to grow an oxide layer of 1.1-1.4 um, wherein the oxide layer can play a role in the convenient growth.

Then, the front side is uniformly photoresisted, and the front side is photolithographically processed using a mask to form a pattern of the through-diffusion area. As shown in Figure 2, the two sides of the N-type substrate after photolithography have a certain curvature to facilitate diffusion. By applying a liquid source, a high concentration of boron doping is introduced into the through-diffusion area pattern (around the N-type substrate) and the bottom of the N-type substrate at the same time, and the silicon wafer is cleaned. High-temperature diffusion is performed at 1270±10℃ for 60-120h, so that the front through-diffusion area and the P-type area are connected to form a P-type structure.

Optionally, referring to FIG. 7 , S102 - 3 includes:

S102-31, performing a first photolithography on the surface of the N-type substrate to form a pattern of a first N-type region.

S102-32, ion implantation is performed on the pattern of the first N-type region, and the first N-type region is formed by high temperature diffusion.

S102-33, performing a second photolithography process on the surface of the N-type substrate to form patterns of the first P-type region and the second P-type region.

S102-34, ion implantation is performed on the patterns of the first P-type region and the second P-type region, and the first P-type region and the second P-type region are formed by high temperature diffusion.

S102-35, performing a third photolithography process on the surface of the N-type substrate to form a pattern of a second N-type region.

S102-36, liquid source diffusion is performed on the pattern of the first N-type region, and a second N-type region is formed by high temperature diffusion.

S102-37, performing a fourth photolithography on the surface of the N-type substrate to form a pattern of a third N-type region.

S102-38, ion implantation is performed on the pattern of the third N-type region, and the third N-type region is formed by high temperature diffusion.

S102-39, making electrodes.

In the present application, phosphorus ions are implanted into the pattern of the first N-type region by ion implantation, and the implantation dose is adjusted according to the voltage. This embodiment requires >100V, and the implantation dose is preferably 3E14-6E14cm ^-2 . Then, high temperature and long time diffusion is performed, for example, the temperature is 1275±5℃, to form the first N-type region.

Similarly, when making the first P-type region and the second P-type region, front-side lithography is also used to form the corresponding pattern, and then boron ion implantation is performed from the front side with a dose of 1E15~4E15 cm ^-2 and an energy of 55~65keV. After cleaning, high-temperature diffusion is performed with a typical temperature of 1250±5℃ to form the first P-type region and the second P-type region at the same time.

Then, photolithography is performed again to form the pattern of the second N-type region. It should be noted that since the second N-type region adopts a heavily doped method, the doping type is the same as that of the first heavily doped region. Therefore, when performing photolithography of the second N-type region pattern, the first heavily doped region can also be formed by photolithography at the same time. Then, phosphorus impurities are introduced into the first heavily doped region and the second N-type region through diffusion of the POCL3 liquid source, and then high-temperature diffusion is performed, with a typical temperature of 1200±10°C, to form the first heavily doped region and the second N-type region at the same time. Of course, in some other embodiments, they can also be made separately, and this application does not limit this.

Then, photolithography is performed to form a pattern of the third N-type region, and phosphorus ions are implanted into the pattern of the third N-type region by ion implantation. The implantation dose is adjusted according to the voltage. This embodiment requires >100V, and the preferred implantation dose is 5E14-1E15 cm ^-2 . Then, the silicon wafer is cleaned and high-temperature diffused at 1180±20°C for 3-5h.

The front side is photolithographically processed again to form the pattern of the second heavily doped region, and boron ions are implanted into the pattern by ion implantation, with a typical implantation dose of 3E15 to 4E15 cm ^-2 . The silicon wafer is then cleaned and oxidized at 1100±20°C for 3-5h.

The front side is photolithographically processed again to form an ohmic contact hole, and the back oxide layer is removed at the same time. Al is evaporated on the front side to form a front metal electrode, and Ti-Ni-Ag is evaporated on the back side to form a back metal electrode. The front side is photolithographically processed again to etch out metal to form the electrode pattern of the first electrode, the second electrode, the third electrode and the interconnecting metal wire pattern, and alloy is formed, and the fourth electrode on the back side is also formed.

Third embodiment

Based on the first embodiment, the present application also provides a bidirectional overvoltage protection circuit, please refer to Figure 8, the bidirectional overvoltage protection circuit includes at least two power integrated circuit chips, and the positive and negative poles of the bidirectional overvoltage protection circuit are connected to at least one power integrated circuit chip, and one pin of the power integrated circuit chip is grounded, so that when a positive and/or negative surge occurs, the power integrated circuit chip is turned on to discharge the surge to the ground.

The chip described in the present invention is packaged in a SOP8 shape according to the connection method shown in Figure 4 to form a power integrated circuit chip, and the lead pins are G1, G2, A, and K respectively. In the bidirectional protection application of multiple SLIC lines in parallel, as shown in Figure 8, two power integrated circuit chips described in the present invention are required to achieve positive and negative bidirectional programmable overvoltage protection. The diode rectifier bridge is connected between each group of RING and TIP, and the positive pole output after rectification is connected to the anode (pin A) of the left power integrated circuit chip, and the cathode (pin K) of the left power integrated circuit chip is grounded. The negative pole output after rectification is connected to the cathode (pin K) of the right power integrated circuit chip, and the anode (pin A) of the right power integrated circuit chip is grounded. The positive supply voltage (+Vbat) is connected to the G1 pin of the left power integrated circuit chip, that is, the negative signal drives the gate; the negative supply voltage (-Vbat) is connected to the G2 pin of the right power integrated circuit chip, that is, the positive signal drives the gate. In the application environment shown in FIG8 , according to the schematic diagram of FIG3 , the first diode is in a reverse biased state under the action of the positive power supply voltage (+Vbat), and the diode D2 is also in a reverse biased state under the action of the negative power supply voltage (-Vbat), and the power integrated circuit chip does not operate. Due to some reasons, once a positive surge overvoltage occurs on the RING, the positive surge will flow through the diode rectifier and flow into the anode of the power integrated circuit chip on the left. When the surge voltage value is greater than the positive power supply voltage (+Vbat), the first diode is turned on, thereby opening the unidirectional thyristor and discharging the positive surge to the ground. Once a negative surge overvoltage occurs on the RING, the negative surge will flow out from the anode of the power integrated circuit chip on the right through the diode rectifier. When the negative surge voltage value is less than the negative power supply voltage (-Vbat), the diode D2 is turned on, thereby opening the unidirectional thyristor and discharging the negative surge to the ground.

In summary, the present application provides a power integrated circuit chip and a method for manufacturing the same, wherein the power integrated circuit chip comprises an N-type substrate, a P-type structure located around and at the bottom of the N-type substrate, and an active area located on the surface of the N-type substrate; wherein the N-type substrate, the P-type structure, and the active area together constitute a unidirectional thyristor, a first diode, and a second diode, and the long base region and the short base region of the unidirectional thyristor are respectively connected to the first diode and the second diode. Since the power integrated circuit chip provided by the present application integrates a thyristor and two diodes on the same N-type substrate, the consistency of multiple devices is improved through integration. At the same time, multiple devices can be manufactured based on one N-type substrate during the manufacturing process, and the cost is reduced.

The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims (8)

1. A power integrated circuit chip, characterized in that the power integrated circuit chip comprises: N-type substrate; A P-type structure located around and at the bottom of the N-type substrate; and An active region located on the surface of the N-type substrate; wherein, The N-type substrate, the P-type structure and the active area together constitute a unidirectional thyristor, a first diode and a second diode, and the long base region and the short base region of the unidirectional thyristor are connected to the first diode and the second diode respectively; The active region comprises: a first electrode located on the surface of the N-type substrate, a first P-type region located on the surface of the N-type substrate, a first N-type region located below the first P-type region, a second N-type region located within the first P-type region, a second P-type region located on the surface of the N-type substrate, a third N-type region located within the second P-type region, a second electrode, a third electrode, and an interconnect metal layer, wherein: The second N-type region is connected to the second electrode, the first P-type region is connected to the third N-type region through the interconnect metal layer, and the second P-type region is connected to the third electrode; The first electrode, the N-type substrate and the P-type structure constitute a first diode; The N-type substrate, the P-type structure, the first P-type region, the first N-type region, and the second N-type region constitute the unidirectional thyristor, and the first N-type region is used to adjust the trigger voltage of the unidirectional thyristor; The second P-type region, the third N-type region and the third electrode constitute the second diode; The junction depth of the second N-type region is smaller than the junction depth of the first P-type region, and the junction depth of the third N-type region is smaller than the junction depth of the second P-type region; Furthermore, the cathode of the first diode is connected to the long base region of the unidirectional thyristor, and the cathode of the second diode is connected to the short base region of the unidirectional thyristor; the power integrated circuit chip also includes a fourth electrode, which is located at the bottom of the P-type structure. 2. The power integrated circuit chip as described in claim 1 is characterized in that the power integrated circuit chip also includes a first heavily doped region, the first heavily doped region is located in the N-type substrate, the conductivity type of the first heavily doped region is N-type, and the N-type substrate is in ohmic contact with the first electrode through the first heavily doped region. 3. The power integrated circuit chip as described in claim 1 is characterized in that the power integrated circuit chip also includes a second heavily doped region, the second heavily doped region is located in the first P-type region, the conductivity type of the second heavily doped region is P-type, and the first P-type region is in ohmic contact with the interconnect metal layer through the second heavily doped region. 4 . The power integrated circuit chip according to claim 1 , wherein the second N-type region is a heavily doped region, and an ohmic contact is established between the second N-type region and the second electrode. 5 . The power integrated circuit chip according to claim 1 , wherein a short-circuit hole is provided in the second N-type region. 6. A method for manufacturing a power integrated circuit chip, for manufacturing the power integrated circuit chip according to any one of claims 1 to 5, characterized in that the method comprises: Providing an N-type substrate; A P-type structure is fabricated at the bottom of the N-type substrate, and an active region is fabricated on the surface of the N-type substrate; wherein the N-type substrate, the P-type structure and the active region together constitute a unidirectional thyristor, a first diode and a second diode, and a long base region and a short base region of the unidirectional thyristor are respectively connected to the first diode and the second diode. 7. The method for manufacturing a power integrated circuit chip according to claim 6, wherein the step of manufacturing a P-type structure at the bottom of the N-type substrate and manufacturing an active area on the surface of the N-type substrate comprises: Preprocessing the N-type substrate; Performing photolithography on the N-type substrate to form a P-type structure around and at the bottom of the N-type substrate; Photolithography and diffusion are performed on the surface of the N-type substrate to form an active region on the surface of the N-type substrate. 8. The method for manufacturing a power integrated circuit chip according to claim 7, wherein the step of performing photolithography and diffusion on the surface of the N-type substrate to form an active area on the surface of the N-type substrate comprises: Performing a first photolithography on the surface of the N-type substrate to form a pattern of a first N-type region; Performing ion implantation on the pattern of the first N-type region and forming the first N-type region by high temperature diffusion; Performing a second photolithography on the surface of the N-type substrate to form patterns of a first P-type region and a second P-type region; Performing ion implantation on the patterns of the first P-type region and the second P-type region, and forming the first P-type region and the second P-type region by high temperature diffusion; Performing a third photolithography on the surface of the N-type substrate to form a pattern of a second N-type region; Performing liquid source diffusion on the pattern of the second N-type region and forming the second N-type region by high temperature diffusion; Performing a fourth photolithography on the surface of the N-type substrate to form a pattern of a third N-type region; Performing ion implantation on the pattern of the third N-type region, and forming the third N-type region by high temperature diffusion; Fabricate electrodes.