CN110416257A - Display panel backplane structure, its preparation method and top emission display panel - Google Patents

Abstract

The application relates to a top emission display panel, including a substrate, a buffer layer, a gate, an insulating layer, an active layer, a protective layer, a source electrode, a drain electrode, an auxiliary electrode, a flat layer, a pixel electrode and a pixel definition layer. In the above-mentioned top emission display panel, the grid is embedded in the buffer layer and forms a flat surface with the buffer layer, the active layer is embedded in the insulating layer and forms a flat surface with the insulating layer, and the source, drain, and auxiliary electrodes are respectively embedded It is set in the protective layer and forms a flat surface with the protective layer, so that the entire substrate surface forms a flat surface after the TFT drive circuit process is completed, avoiding the uneven surface of the pixel electrode caused by the drive circuit of the top emission display panel, and effectively improving the top. The luminous uniformity of the emissive display panel improves the display effect.

Description

Display panel backplane structure, its preparation method and top emission display panel

technical field

The invention relates to the technical field of organic light-emitting electronic devices, in particular to a display panel backplane structure, a preparation method thereof and a top emission display panel.

Background technique

Organic light-emitting diodes (OLEDs) have become one of the main directions of display research because of their advantages such as self-luminescence, fast response, wide viewing angle, high brightness, and thinness. OLED displays are mainly produced by solution processing, which has the advantages of low cost, high productivity, and easy realization of large sizes, and has become an important direction for the development of display technology in the future. Among them, printing technology is considered to be the most effective way to realize low-cost OLED and large-area full-color display.

Since the OLED display panel needs to be compensated by a relatively complex driving circuit, a large part of its TFT backplane is covered by the driving circuit, resulting in a lower aperture ratio of the display panel with a bottom-emitting device structure, resulting in increased power consumption. Large, shortened device life and other issues. However, the use of a top-emitting device structure can greatly increase the aperture ratio of the display panel, avoiding problems such as increased power consumption and shortened device life due to too small aperture ratio.

However, when a top-emitting device is prepared by a printing process, the flatness requirement of the pixel electrode is much higher than that of an evaporation-type device. Since the pixel electrode of the top-emitting display panel covers the driving circuit, and the driving circuit is difficult to planarize in the pre-production process, the flatness of the surface of the pixel electrode is poor, resulting in uneven luminescence of the top-emitting OLED.

Contents of the invention

Based on this, it is necessary to provide a top emission display panel with a flat surface of the pixel electrodes.

In addition, the present application also provides a display panel backplane structure and a preparation method thereof.

A display panel backplane structure, comprising: a substrate;

a buffer layer disposed on the substrate, the buffer layer is embedded with a gate, and the surface of the gate away from the substrate is substantially flush with the surface of the buffer layer away from the substrate;

An insulating layer disposed on the buffer layer, the insulating layer is embedded with an active layer, the surface of the active layer away from the buffer layer is substantially flush with the surface of the insulating layer away from the buffer layer ;

A protective layer disposed on the insulating layer, the protective layer is embedded with a source and a drain, and the surfaces of the source and the drain away from the insulating layer are respectively separated from the protective layer away from the insulating layer The surfaces of are substantially flush, and both the source and the drain are at least partially in contact with the active layer;

A planar layer disposed on the protective layer, the planar layer is provided with a planar layer opening penetrating through the planar layer to expose at least part of the drain.

In one embodiment, at least one auxiliary electrode is embedded in the protective layer, and the surface of each auxiliary electrode away from the insulating layer is substantially flush with the surface of the protective layer away from the insulating layer.

A method for preparing a display panel backplane structure, comprising the following steps:

Provide the substrate;

forming a buffer layer on the substrate;

A buffer layer opening is formed in the buffer layer, and a gate material is deposited in the buffer layer opening to form a gate, so that the surface of the gate away from the substrate is substantially flush with the surface of the buffer layer away from the substrate flat;

forming an insulating layer on the surface of the gate and the buffer layer away from the substrate;

forming an insulating layer opening in the insulating layer, depositing an active material in the insulating layer opening to form an active layer, so that the surface of the active layer away from the buffer layer and the insulating layer away from the buffer layer The surface is substantially flush;

forming a protective layer on the surface of the active layer and the insulating layer away from the buffer layer;

A source protection layer opening and a drain protection layer opening are respectively formed in the protection layer through the protection village layer, and the source protection layer opening and the drain protection layer opening expose at least part of the active layer. , depositing a metal material in the opening of the source protective layer and the opening of the drain protective layer to form a source and a drain, so that the source and the drain are far away from the surface of the insulating layer and the protective layer. a surface of the layer remote from the insulating layer is substantially flush, and the source and drain are at least partially in contact with the active layer;

A planar layer is formed on the surface of the source electrode, the drain electrode and the protection layer away from the insulating layer, and a planar layer opening is formed in the planar layer, and the planar layer opening exposes at least part of the planar layer. drain.

In one of the embodiments, a buffer layer opening is formed in the buffer layer, and the method of depositing a gate material in the buffer layer opening to form a gate is as follows:

A patterned first photoresist layer is formed on the surface of the buffer layer away from the substrate, and the position of the buffer layer corresponding to the patterned area of the first photoresist layer is etched to form an opening in the buffer layer ;

Deposit a gate material on the surface of the first photoresist layer away from the buffer layer and in the opening of the buffer layer until the thickness of the gate material deposited is the same as the depth of the buffer layer opening, and the first The photoresist layer is peeled off from the gate material deposited on the surface of the first photoresist layer, and the gate material deposited in the opening of the buffer layer forms a gate.

In one of the embodiments, an insulating layer opening is formed in the insulating layer, and the method for depositing an active material in the insulating layer opening to form an active layer is as follows:

Forming a patterned second photoresist layer on the surface of the insulating layer away from the buffer layer, etching the position of the insulating layer corresponding to the patterned area of the second photogroup layer to form the insulating layer open mouth

Deposit an active material on the surface of the second photoresist layer away from the insulating layer and in the opening of the insulating layer until the thickness of the active material deposited is the same as the depth of the opening of the insulating layer, and the second The photoresist layer is peeled off from the active material deposited on the surface of the second photoresist layer, and the active material deposited in the opening of the insulating layer forms an active layer.

In one of the embodiments, a source protection layer opening and a drain protection layer opening penetrating through the protection layer are respectively formed in the protection layer, inside the source protection layer opening and within the drain protection layer opening The method of depositing metal material to form source and drain is:

A patterned third photoresist layer is formed on the surface of the protection layer away from the insulating layer, and the positions of the protection layer corresponding to the patterned regions of the third photoresist layer are etched to form the source electrodes respectively. a protective layer opening and the drain protective layer opening;

Deposit a metal material on the surface of the third photoresist layer away from the protection layer, in the opening of the source protection layer, and in the opening of the drain protection layer until the thickness of the deposition of the metal material is equal to the thickness of the protection layer. The thickness is the same, the third photoresist layer and the metal material deposited on the surface of the third photoresist layer are peeled off, the metal material deposited in the opening of the source protection layer forms a source, and is deposited on the drain The metal material within the opening of the protective layer forms the drain.

In one of the embodiments, the method for preparing the backplane structure of the above-mentioned display panel, after forming a protective layer on the surface of the active layer and the insulating layer away from the buffer layer, further includes the following steps:

Form at least one auxiliary electrode protection layer opening through the protection layer in the protection layer, and deposit a metal material in each of the auxiliary electrode protection layer openings to form an auxiliary electrode, so that each of the auxiliary electrodes is away from the insulation The surface of the layer is substantially flush with the surface of the protective layer remote from the insulating layer.

In one of the embodiments, at least one auxiliary electrode protection layer opening penetrating through the protection layer is formed in the protection layer, and the method for depositing a metal material in each opening of the auxiliary electrode protection layer to form an auxiliary electrode is as follows:

Etching the protection layer at a position corresponding to the patterned area of the third photoresist layer, and forming at least one auxiliary electrode protection layer opening;

A metal material is deposited in each opening of the auxiliary electrode protection layer, the thickness of the metal material deposited is the same as that of the protection layer, and the metal material deposited in the opening of the auxiliary electrode protection layer forms an auxiliary electrode.

A top-emitting display panel, comprising a display panel backplane structure and a pixel electrode and a pixel definition layer disposed on the display panel backplane structure; the display panel backplane structure includes a substrate;

a buffer layer disposed on the substrate, the buffer layer is embedded with a gate, and the surface of the gate away from the substrate is substantially flush with the surface of the buffer layer away from the substrate;

An insulating layer disposed on the buffer layer, the insulating layer is embedded with an active layer, the surface of the active layer away from the buffer layer is substantially flush with the surface of the insulating layer away from the buffer layer ;

A protective layer disposed on the insulating layer, the protective layer is embedded with a source and a drain, and the surfaces of the source and the drain away from the insulating layer are respectively separated from the protective layer away from the insulating layer The surfaces of are substantially flush, and both the source and the drain are at least partially in contact with the active layer;

a planar layer disposed on the protection layer, the planar layer is provided with a planar layer opening penetrating through the planar layer to expose at least part of the drain;

The pixel electrode is disposed in the opening of the flat layer and on the flat layer, and the pixel electrode is in contact with the drain;

The pixel definition layer is disposed on the planar layer, and the pixel definition layer is provided with sub-pixel openings to expose at least part of the pixel electrodes.

In one embodiment, the top emission display panel further includes sub-pixels, and the sub-pixels are disposed in the sub-pixel openings of the pixel definition layer.

In the above-mentioned top-emission display panel, the gate and the buffer layer form a flat surface, the active layer and the insulating layer form a flat surface, and the source and drain electrodes and the protective layer form a flat surface, so that the entire substrate surface forms a flat surface after the TFT drive circuit manufacturing process is completed. To avoid the unevenness of the surface of the pixel electrode caused by the driving circuit in the top emission display panel, effectively improve the uniformity of light emission of the top emission display panel, thereby improving the display effect.

Description of drawings

1 is a schematic structural view of a top emission display panel according to an embodiment;

FIG. 2 is a schematic structural diagram corresponding to step S110;

FIG. 3 is a schematic structural diagram corresponding to step S112;

4 and 5 are structural schematic diagrams corresponding to step S113;

FIG. 6 is a schematic structural diagram corresponding to step S115;

7 and 8 are structural schematic diagrams corresponding to step S116;

FIG. 9 is a schematic structural diagram corresponding to step S118;

FIG. 10 is a schematic structural diagram corresponding to step S119;

FIG. 11 is a schematic structural diagram corresponding to step S120;

FIG. 12 is a schematic structural diagram corresponding to step S121.

Detailed ways

In order to facilitate the understanding of the present invention, the following will describe the present invention more fully and give preferred embodiments of the present invention. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Please refer to FIG. 1 , a top emission display panel 1000 according to an embodiment includes a display panel backplane structure 100 and a pixel electrode 200 and a pixel definition layer 300 disposed on the display panel backplane structure 100 . Wherein, the display panel backplane structure 100 includes a substrate 10 , a buffer layer 20 , a gate 22 , an insulating layer 30 , an active layer 32 , a protective layer 40 , a source 42 , a drain 44 , an auxiliary electrode 46 and a flat layer 50 .

Further, there is a TFT driving array on the substrate 10, which is used to drive light-emitting components to realize image display.

Further, the buffer layer 20 is stacked on the substrate 10, and the buffer layer 20 is embedded with a gate 22, and the surface of the gate 22 away from the substrate 10 is substantially flush with the surface of the buffer layer 20 away from the substrate 10, forming a flat surface.

It should be noted that the fact that the surface of the gate 22 away from the substrate 10 is substantially flush with the surface of the buffer layer 20 away from the substrate 10 means that the height difference between the upper surface of the gate 22 and the upper surface of the buffer layer 20 does not exceed the thickness of the buffer layer 20 1%.

Further, the upper surface of the gate 22 is flush with the upper surface of the buffer layer 20 .

Wherein, the material of the buffer layer 20 is selected from at least one of silicon oxide (SiO _x ) and silicon nitride (SiN _x ).

It can be understood that, in other implementation manners, the material of the aforementioned buffer layer 20 may also be any existing material that can be used as the buffer layer 20 .

Further, the material of the gate 22 is conductive metal. In this embodiment, the material of the gate 22 is selected from at least one of copper-molybdenum alloy, aluminum and aluminum-molybdenum alloy.

It can be understood that the material of the above-mentioned gate 22 can also be any existing material that can be used as the gate 22 .

In this embodiment, the surface of the gate 22 close to the substrate 10 is located in the buffer layer 20 , as shown in FIG. 1 .

It can be understood that, in other implementation manners, the surface of the gate 22 close to the substrate 10 may also be substantially flush with the surface of the buffer layer 20 close to the substrate 10 to form a flat surface.

Further, the insulating layer 30 is stacked on the buffer layer 20 . The insulating layer 30 is embedded with an active layer 32 . The surface of the active layer 32 away from the buffer layer 20 is substantially flush with the surface of the insulating layer 30 away from the buffer layer 20 , forming a flat surface.

It should be noted that the surface of the active layer 32 away from the buffer layer 20 is substantially flush with the surface of the insulating layer 30 away from the buffer layer 20 means that the height difference between the upper surface of the active layer 32 and the upper surface of the insulating layer 30 is equal to More than 1% of the thickness of the insulating layer 30 .

Further, the upper surface of the active layer 32 is flush with the upper surface of the insulating layer 30 .

In this embodiment, the surface of the active layer 32 close to the buffer layer 20 is located in the insulating layer 30 , as shown in FIG. 1 .

Wherein, the material of the insulating layer 30 is selected from at least one of silicon oxide (SiO _x ) and silicon nitride (SiN _x ).

It can be understood that, in other implementation manners, the material of the insulating layer 30 may also be other gate insulating materials.

Further, the material of the active layer 32 is a semiconductor material, such as a metal oxide semiconductor or the like.

Further, the protective layer 40 is stacked on the insulating layer 30 . The protective layer 40 is embedded with a source 42 , a drain 44 and at least one auxiliary electrode 46 .

It can be understood that the auxiliary electrode 46 can be omitted.

Further, the material of the protection layer 40 is selected from at least one of silicon oxide (SiO _x ) and silicon nitride (SiN _x ).

It can be understood that, in other implementation manners, the material of the protective layer 40 can also be any existing material that can be used as the protective layer 40 .

Further, the material of the source electrode 42 , the drain electrode 44 and the auxiliary electrode 46 is conductive metal. In this embodiment, the material of the source electrode 42 , the drain electrode 44 and the auxiliary electrode 46 is selected from at least one of copper-molybdenum alloy, aluminum and aluminum-molybdenum alloy.

Further, the surfaces of the source electrode 42 , the drain electrode 44 and the auxiliary electrode 46 away from the insulating layer 30 are substantially flush with the surface of the protective layer 40 away from the insulating layer 30 , forming a flat surface.

It should be noted that: the surfaces of the source electrode 42, the drain electrode 44 and the auxiliary electrode 46 away from the insulating layer 30 are substantially flush with the surface of the protective layer 40 away from the insulating layer 30, which means: the upper surface of the source electrode 42, the drain electrode 44 The height difference between the upper surface of the upper surface of the auxiliary electrode 46 and the upper surface of the protective layer 40 does not exceed 1% of the thickness of the protective layer 40 .

Further, the top surfaces of the source electrode 42 , the drain electrode 44 , and the auxiliary electrode 46 are all flush with the top surface of the protection layer 40 .

Further, both the source electrode 42 and the drain electrode 44 are at least partially in contact with the active layer 32 . The auxiliary electrode 46 is externally connected to a power supply circuit.

Further, the flat layer 50 is stacked on the protection layer 40 . The flat layer 50 is provided with a flat layer opening 52 penetrating through the flat layer 50 to expose at least part of the drain electrode 44 , as shown in FIG. 12 .

Further, the planar layer 50 is an organic photoresist layer with a thickness of 1 μm, which plays a planar role.

Further, the pixel electrode 200 is disposed in the flat layer opening 52 and on the flat layer 50 . The pixel electrode 200 is in contact with the drain electrode 44 .

Further, the pixel electrode 200 is a conductive film layer, and the conductive film layer is a reflective conductive film layer, such as a high conductive metal film such as aluminum, silver, aluminum-silver alloy, or a reflective conductive film layer including a multi-layer structure such as ITO, Ag, and ITO. film.

Further, the pixel definition layer 300 is disposed on the flat layer 50 , and the pixel definition layer 300 is provided with sub-pixel openings (marked in the figure) to expose part of the pixel electrodes 200 .

In this embodiment, the sub-pixel openings expose all the pixel electrodes 200 .

Furthermore, the thickness of the pixel definition layer 300 is 800nm-1500nm, which is used to define the size of the light emitting area of each pixel, and the surface is lyophobic to prevent color mixing caused by ink overflow during the printing process.

In the above-mentioned top-emission display panel, the grid 22 and the buffer layer 20 form a flat surface, the active layer 32 and the insulating layer 30 form a flat surface, and the source 42, the drain 44, the auxiliary electrode 46 and the protective layer 40 form a flat surface, so that After the TFT driving circuit manufacturing process is completed, the entire substrate surface forms a flat surface, which avoids the problem of uneven surface of the pixel electrode caused by the driving circuit of the top emission display panel, effectively improves the uniformity of light emission of the top emission display panel, thereby improving the display effect.

Please refer to FIGS. 1-12 , a method for manufacturing a top emission display panel in an embodiment includes the following steps:

S110 , providing a substrate 10 , and forming a buffer layer 20 on the substrate 10 , as shown in FIG. 2 .

Specifically, materials such as silicon oxide and nitride silicide are deposited on the substrate 10 to form the buffer layer 20 .

S112 , forming a buffer layer opening 23 in the buffer layer 20 .

Specifically, a patterned first photoresist layer 21 is formed on the surface of the buffer layer 20 away from the substrate 10, and the patterned area of the buffer layer 20 corresponding to the first photoresist layer 21 is etched to form a buffer layer opening 23, as shown in FIG. 3.

Specifically, a photoresist material is coated on the surface of the buffer layer 20 away from the substrate 10 and photolithography is performed to form a patterned first photoresist layer 21 .

S113 , depositing gate material 25 in the opening 23 of the buffer layer to form the gate 22 , so that the surface of the gate 22 away from the substrate 10 is substantially flush with the surface of the buffer layer 20 away from the substrate 10 .

Specifically, the gate material 25 is deposited on the surface of the first photoresist layer 21 away from the buffer layer 20 and in the buffer layer opening 23 to the same deposition thickness as the buffer layer opening 23, as shown in FIG. 4 .

The first photoresist layer 21 and the gate material 25 deposited on the surface of the first photoresist layer 21 are peeled off, and the gate material deposited in the opening 23 of the buffer layer forms a gate 22 , as shown in FIG. 5 .

It can be understood that the gate 22 is the gate material 25 deposited in the opening 23 of the buffer layer.

S114 , forming an insulating layer 30 on the surface of the gate 22 and the buffer layer 20 away from the substrate 10 .

Specifically, a gate insulating material is deposited on the surface of the gate 22 and the buffer layer 20 away from the substrate 10 to form the insulating layer 30 .

S115 , forming an insulating layer opening 33 in the insulating layer 30 .

Specifically, a patterned second photoresist layer 31 is formed on the surface of the insulating layer 30 away from the buffer layer 20, and the position of the insulating layer 30 corresponding to the patterned area of the second photoresist layer 31 is etched to form an opening 33 in the insulating layer. ,As shown in Figure 6.

Specifically, a photoresist is coated on the surface of the insulating layer 30 away from the buffer layer 20 and photolithography is performed to form a patterned second photoresist layer 31 .

S116 , depositing the active material 35 in the insulating layer opening 33 to form the active layer 32 , so that the surface of the active layer 32 away from the buffer layer 20 is substantially flush with the surface of the insulating layer 30 away from the buffer layer 20 .

Specifically, an active material 35 is deposited on the surface of the second photoresist layer 31 away from the insulating layer 30 and in the opening 33 of the insulating layer. The deposition thickness of the active material 35 is the same as the depth of the insulating layer opening 33, as shown in FIG. 7 .

The second photoresist layer 31 and the active material 35 deposited on the surface of the second photoresist layer 31 are peeled off, and the active material deposited in the insulating layer opening 33 forms an active layer 32 , as shown in FIG. 8 .

It can be understood that the active layer 32 is the active material 33 deposited on the opening 33 of the insulating layer.

It should be noted that the active material 33 is a material forming the active layer 32 , such as a semiconductor material such as a metal oxide semiconductor.

S117 , forming a protective layer 40 on the surfaces of the active layer 32 and the insulating layer 30 away from the buffer layer 20 .

S118, respectively forming a source protection layer opening 43, a drain protection layer opening 45, and an auxiliary electrode protection layer opening 47 penetrating through the protection layer 40 in the protection layer 40, wherein the source protection layer opening 43 and the drain protection layer opening 45 are at least Part of the active layer 32 is exposed.

Specifically, a patterned third photoresist layer 41 is formed on the surface of the protection layer 40 away from the insulating layer 30, and the position of the protection layer 40 corresponding to the patterned area of the third photoresist layer 41 is etched to form a source protection layer The opening 43 , the drain protection layer opening 45 and the auxiliary electrode protection layer opening 47 , wherein both the source protection layer opening 43 and the drain protection layer opening 45 expose at least part of the active layer 32 , as shown in FIG. 9 .

It can be understood that if the auxiliary electrode is not required, the opening 47 of the auxiliary electrode protective layer may not be etched.

Specifically, a photoresist is coated on the surface of the protection layer 40 away from the insulating layer 30 and photolithography is performed to form a patterned third photoresist layer 41 .

S119. Deposit metal material 49 in the source protective layer opening 43, the drain protective layer opening 45 and the auxiliary electrode protective layer opening 47 to form the source electrode 42, the drain electrode 44 and the auxiliary electrode 46, so that the source electrode 42, the drain electrode The surfaces of the protective layer 44 and the auxiliary electrode 46 away from the insulating layer 30 are substantially flush with the surface of the protective layer 40 away from the insulating layer 30 , and both the source 42 and the drain 44 are at least partially in contact with the active layer 32 .

Specifically, a metal material 49 is deposited on the surface of the third photoresist layer 41 away from the protective layer 40, in the opening 43 of the source protective layer, in the opening 45 of the drain protective layer, and in the opening 47 of the auxiliary electrode protective layer. The metal material 49 The deposition thickness is the same as that of the protective layer 40, as shown in FIG. 10 .

It should be noted that the metal material 49 is a conductive metal material such as copper-molybdenum alloy, aluminum, and aluminum-molybdenum alloy.

The third photoresist layer 41 and the metal material 49 deposited on the surface of the third photoresist layer 41 are peeled off, the metal material deposited in the opening 43 of the source protection layer forms the source 42, and the metal material deposited in the opening 45 of the drain protection layer The metal material forms the drain electrode 44 , and the metal material 49 deposited in the opening 47 of the auxiliary electrode protective layer forms the auxiliary electrode 46 , as shown in FIG. 11 .

S120 , forming a flat layer 50 on the surface of the source electrode 42 , the drain electrode 44 , the auxiliary electrode 46 and the protection layer 40 away from the insulating layer 30 .

S121 , forming a flat layer opening 52 penetrating through the flat layer 50 in the flat layer 50 , the flat layer opening 52 exposing at least part of the drain electrode 44 .

Specifically, photolithography is performed on the planar layer 50 to form a planar layer opening 52 , and the planar layer opening 52 exposes at least part of the drain electrode 44 , as shown in FIG. 12 .

S122, forming a pixel electrode 200 in the flat layer opening 52 and on the surface of the flat layer 50 away from the protective layer 40, the pixel electrode 200 is in contact with the drain electrode 44, and forming a pixel electrode 200 on the surface of the flat layer 50 away from the protective layer 40 The pixel definition layer 300, on which sub-pixel openings (not marked) are arranged to expose at least part of the pixel electrodes 200, as shown in FIG. 1 .

Specifically, deposit highly conductive metal materials such as aluminum, silver, aluminum-silver alloy, etc. in the flat layer opening 52 and on the surface of the flat layer 50 away from the protective layer 40; or alternately deposit materials such as ITO, Ag, etc., and then perform photolithography to A patterned pixel electrode 200 is formed.

Specifically, the pixel definition layer material is deposited on the flat layer 50 corresponding to the patterned area of the pixel electrode 200 and the surface of the pixel electrode 200 away from the flat layer 50 , and then photolithography is performed to form the pixel definition layer 300 with sub-pixel openings.

In this embodiment, the sub-pixel openings expose all the pixel electrodes 200 .

The preparation method of the above-mentioned top-emission display panel is simple and feasible, and can prepare a backplane structure with a smooth pixel electrode surface, avoiding the problem of uneven surface of the pixel electrode caused by the driving circuit of the top-emission display panel, and effectively improving the performance of the top-emission display panel. Luminous uniformity, thereby improving the display effect.

The various technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, all possible blockings of the various technical features in the above-mentioned embodiments are not described. However, as long as the blocking of these technical features is not Where there is a contradiction, all should be deemed to be within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. a kind of display panel back board structure characterized by comprising substrate；

Buffer layer on the substrate is embedded with grid, surface of the grid far from the substrate in the buffer layer It is substantially flush with the buffer layer far from the surface of the substrate；

Insulating layer on the buffer layer is embedded with active layer in the insulating layer, and the active layer is far from the buffering The surface of layer is substantially flush with the insulating layer far from the surface of the buffer layer；

Protective layer on the insulating layer is embedded with source electrode and drain electrode in the protective layer, and the source electrode and drain electrode is separate The surface of the insulating layer is substantially flush with the protective layer far from the surface of the insulating layer respectively, and the source electrode and described Drain electrode is at least partly contacted with the active layer；

Flatness layer on the protective layer, the flatness layer is equipped with the flatness layer opening through the flatness layer, at least It drains described in exposed portion.

2. display panel back board structure according to claim 1, which is characterized in that be also embedded at least in the protective layer One auxiliary electrode, surface of each auxiliary electrode far from the insulating layer and the protective layer are far from the insulating layer Surface is substantially flush.

3. a kind of preparation method of display panel back board structure, which comprises the following steps:

Substrate is provided；

Buffer layer is formed on the substrate；

Buffer layer opening is formed in the buffer layer, deposition of gate material forms grid in the buffer layer is open, so that institute It states surface of the grid far from the substrate and is substantially flush with the buffer layer far from the surface of the substrate；

Insulating layer is formed far from the surface of the substrate in the grid and the buffer layer；

Insulating layer openings are formed in the insulating layer, active material is deposited in the insulating layer openings and is formed with active layer, so that Surface of the active layer far from the buffer layer is substantially flush with the insulating layer far from the surface of the buffer layer；

Protective layer is formed far from the surface of the buffer layer in the active layer and the insulating layer；

The source electrode protective layer opening and drain protective layer opening through the protective layer, the source are respectively formed in the protective layer Pole protective layer opening and drain protective layer opening at least active layer described in exposed portion, are open in the source electrode protective layer Deposited metal material in the interior and described drain protective layer opening, forms source electrode and drain electrode, so that the source electrode and drain electrode is far from institute The surface for stating insulating layer is substantially flush with the protective layer far from the surface of the insulating layer respectively, and the source electrode and drain electrode is equal At least partly contacted with the active layer；

Flatness layer is formed far from the surface of the insulating layer in the source electrode, drain electrode and the protective layer, in the flatness layer shape It is open at the flatness layer through the flatness layer, the flatness layer opening drains described at least exposed portion.

4. the preparation method of display panel back board structure according to claim 3, which is characterized in that in the buffer layer shape It is open at buffer layer, the method that deposition of gate material forms grid in the buffer layer is open are as follows:

Patterned first photoresist layer is formed far from the surface of the substrate in the buffer layer, it will be described in buffer layer correspondence The position of the pattered region of first photoresist layer is etched, to form the buffer layer opening；

Deposition of gate material is to described in surface of first photoresist layer far from the buffer layer and the buffer layer are open The thickness of gate material deposition is identical as the depth that the buffer layer is open, and by first photoresist layer and is deposited on described first The grid material of photoresist layer surface is removed, and the grid material being deposited in the buffer layer opening forms grid.

5. the preparation method of display panel back board structure according to claim 3, which is characterized in that in the insulating layer shape At insulating layer openings, the method that active material is formed with active layer is deposited in the insulating layer openings are as follows:

Patterned second photoresist layer is formed far from the surface of the buffer layer in the insulating layer, the insulating layer is corresponded into institute The position for stating the pattered region of the second photoresist layer is etched, to form the insulating layer openings；

Deposition active material is to described in surface of second photoresist layer far from the insulating layer and the insulating layer openings The thickness of active material deposition is identical as the depth of the insulating layer openings, by second photoresist layer and is deposited on described second The active material of photoresist layer surface is removed, and the active material being deposited in the insulating layer openings forms active layer.

6. the preparation method of display panel back board structure according to claim 3, which is characterized in that in the protective layer point Xing Cheng through the protective layer source electrode protective layer opening and drain protective layer opening, the source electrode protective layer opening in and Deposited metal material in the drain protective layer opening, the method for forming source electrode and drain electrode are as follows:

Patterned third photoresist layer is formed far from the surface of the insulating layer in the protective layer, the protective layer is corresponded into institute The position for stating the pattered region of third photoresist layer is etched, to be respectively formed the source electrode protective layer opening and the drain electrode Protective layer opening；

In surface of the third photoresist layer far from the protective layer, source electrode protective layer opening and the drain protective layer The thickness that deposited metal material to the metal material deposits in being open is identical as the thickness of the protective layer, by the third light Resistance layer and the metal material removing for being deposited on the third photoresist layer surface, the metal being deposited in the source electrode protective layer opening Material forms source electrode, and the metal material being deposited in the drain protective layer opening forms drain electrode.

7. the preparation method of display panel back board structure according to claim 6, which is characterized in that described described active It is further comprising the steps of after layer and the insulating layer form protective layer far from the surface of the buffer layer:

At least one auxiliary electrode protective layer opening through the protective layer is formed in the protective layer, in each auxiliary Deposited metal material forms auxiliary electrode in electrode protecting layer opening, so that each auxiliary electrode is far from the insulating layer Surface is substantially flush with the protective layer far from the surface of the insulating layer.

8. the preparation method of display panel back board structure according to claim 7, which is characterized in that in the protective layer shape It is open at least one auxiliary electrode protective layer through the protective layer, it is heavy in each auxiliary electrode protective layer opening The method that product metal material forms auxiliary electrode are as follows:

The position that the protective layer corresponds to the pattered region of the third photoresist layer is etched, it is auxiliary also to form at least one Electrode protecting layer is helped to be open；

The deposited metal material in each auxiliary electrode protective layer is open, the thickness of the metal material deposition and the guarantor The thickness of sheath is identical, and the metal material being deposited in the auxiliary electrode protective layer opening forms auxiliary electrode.

9. a kind of top emission type display panel, which is characterized in that including display panel back board structure and be set to the display panel Pixel electrode and pixel defining layer on back board structure；The display panel back board structure, including substrate；

Buffer layer on the substrate is embedded with grid, surface of the grid far from the substrate in the buffer layer It is substantially flush with the buffer layer far from the surface of the substrate；

Insulating layer on the buffer layer is embedded with active layer in the insulating layer, and the active layer is far from the buffering The surface of layer is substantially flush with the insulating layer far from the surface of the buffer layer；

Protective layer on the insulating layer is embedded with source electrode and drain electrode in the protective layer, and the source electrode and drain electrode is separate The surface of the insulating layer is substantially flush with the protective layer far from the surface of the insulating layer respectively, and the source electrode and described Drain electrode is at least partly contacted with the active layer；

Flatness layer on the protective layer, the flatness layer is equipped with the flatness layer opening through the flatness layer, at least It drains described in exposed portion；

The pixel electrode is set in flatness layer opening and on the flatness layer, and the pixel electrode connects with the drain electrode Touching；

The pixel defining layer is set on the flatness layer, and the pixel defining layer is open equipped with sub-pixel, at least exposed division Divide the pixel electrode.

10. top emission type display panel according to claim 9, which is characterized in that the top emission type display panel is also Including sub-pixel, the sub-pixel is set in the sub-pixel opening of the pixel defining layer.