CN109951059A - A bootstrap voltage circuit - Google Patents

Abstract

The invention provides a bootstrap voltage circuit, which adopts a low voltage diode and a high withstand voltage field effect transistor to replace the bootstrap diode, and also includes a gate turn-on voltage generator; when the power supply voltage Vb of the upper arm circuit of the bootstrap voltage circuit is smaller than the lower arm circuit When the power supply voltage Vcc is higher than When the power supply voltage Vb of the upper arm circuit is greater than or close to the power supply voltage Vcc of the lower arm circuit, the high withstand voltage field effect transistor is in an off state. The above-mentioned bootstrap voltage circuit is designed by using the existing devices of the process factory to achieve the purpose of replacing the function of the external bootstrap diode.

Description

A bootstrap voltage circuit

technical field

The invention relates to the technical field of single-phase or three-phase gate driving, in particular to a bootstrap voltage circuit.

Background technique

Figure 1 shows a typical circuit diagram of using an external bootstrap diode to generate the upper arm line voltage power supply, including the bootstrap diode, the voltage regulator capacitor for the lower arm power supply voltage (Vcc to COM), and the voltage regulator capacitor for the upper arm power supply voltage ( Vb to Vs), input control signal (HIN, LIN), output gate drive signal (HO, LO), upper arm power tube, lower arm power tube, high voltage drive power supply (eg 600V power supply voltage). The input control signals (HIN, LIN) control the output drive signals (HO, LO), and the output gate drive signals (HO, LO) drive the gates of the upper-arm power transistor and the lower-arm power transistor, thereby controlling the power transistor on or off break.

Figure 2 shows a typical gate drive internal module circuit diagram, including the lower arm circuit and the upper arm circuit. The lower arm circuit is responsible for receiving the input control signal, and then outputs the lower arm gate drive signal (LO) according to the input control signal (HIN, LIN), and transmits the input control signal through the high voltage level shifter circuit (HV level shifter). to the upper arm line. The power and ground of the lower arm circuit are Vcc and COM respectively. The upper arm circuit is responsible for demodulating the signal transmitted by the high voltage level shift circuit, and then outputs the upper arm gate drive signal (HO). And change (floating structure).

Taking the single-phase motor drive as an example, in its typical application, the upper arm and lower arm power tubes are divided into two working stages (periods). First assume that the power supply voltage Vcc of the lower arm circuit is fixed at 15V, the ground COM is fixed at 0V, and the supply voltage of the drain terminal DRAIN (as shown in the figure) of the upper arm power tube is 600V. In the first working stage, the lower arm power tube is turned on and the upper arm power tube is turned off. At this time, the ground (VS) of the upper arm circuit is close to 0V, and Vcc charges Vb through the external bootstrap diode. At this time, the bootstrap diode is positive To bias, Vb is close to 15V. In the second working stage, the lower arm power tube is turned off and the upper arm power tube is turned on. At this time, the ground (VS) of the upper arm circuit is pulled up by the upper arm power tube to approach the supply voltage of the upper arm power tube of 600V, and Vcc does not charge Vb because of this When the bootstrap diode is reverse biased, Vb will drop slightly, because it needs to provide power to the upper arm circuit, and the drop rate is determined by the power consumption of the upper arm circuit and the voltage stabilizing capacitor value between Vb and Vs. At this time, Vb is close to 615V. The first working stage and the second working stage will be repeated alternately, so that the power supply and ground of the upper arm circuit can be fully charged and supplied to the upper arm circuit. This is also the main function of the external bootstrap diode. Forward bias Provide charging when reverse biased, prevent leakage when reverse biased, and prevent breakdown by reverse biased high voltage.

As more and more integrated bootstrap diodes are used in the gate driver chip in the market to replace external bootstrap diodes to reduce costs. This integrated bootstrap diode is mostly a device developed by an integrated component manufacturer (Integrated Device Manufacturer, commonly known as IDM). Generally without their own fabs, also known as Fabless IC design houses, there is no source to obtain this integrated bootstrap diode device.

SUMMARY OF THE INVENTION

The main technical problem to be solved by the present invention is to propose a bootstrap voltage circuit that replaces the function of an external bootstrap diode, and is designed by using the existing devices of the process factory to achieve the purpose of integrating the bootstrap function into the gate driver chip.

In order to solve the above-mentioned technical problems, the present invention provides a bootstrap voltage circuit, which adopts a low voltage diode and a high withstand voltage field effect transistor to replace the bootstrap diode, and also includes a gate-on voltage generator; when the upper arm circuit of the bootstrap voltage circuit is used When the power supply voltage Vb is less than the power supply voltage Vcc of the lower arm circuit, the output voltage of the gate-on voltage generator keeps the high withstand voltage field effect transistor in an on state, and Vcc charges the Vb voltage through the low voltage diode and the high withstand voltage field effect transistor ; When the upper arm line power supply voltage Vb of the bootstrap voltage line is greater than or close to the power supply voltage Vcc of the lower arm circuit, the high withstand voltage field effect transistor is in an off state.

In a preferred embodiment: the anode of the low-voltage diode is connected to Vcc, the cathode of the low-voltage diode is connected to the source terminal of the high voltage field effect transistor, and the drain terminal of the high voltage field effect transistor is connected to Vb;

The output of the gate-on voltage generator is connected to the gate terminal of the high withstand voltage field effect transistor, and the input of the gate-on voltage generator is a high-frequency clock signal.

In a preferred embodiment: the output voltage of the gate-on voltage generator is close to twice the Vcc voltage.

In a preferred embodiment: the gate turn-on voltage generator is a charge pump circuit comprising a first diode and a second diode connected in series between Vcc and the gate of the high voltage field effect transistor ; A first capacitor is connected between the cathode of the first diode and the high-frequency clock input signal, and a second capacitor is connected between the cathode of the second diode and Vcc.

In a preferred embodiment: the gate turn-on voltage generator is a charge pump circuit, which includes a first NMOS transistor and a second NMOS transistor connected in series between Vcc and the gate of the high voltage field effect transistor; A first capacitor is connected between the drain of the first NMOS transistor and the high-frequency clock input signal, and a second capacitor is connected between the drain of the second NMOS transistor and Vcc;

The gate of the first NMOS transistor is connected to the source, and the gate of the second NMOS transistor is connected to the source.

In a preferred embodiment: the gate turn-on voltage generator is a charge pump circuit, which includes a first PMOS transistor and a second PMOS transistor connected in series between Vcc and the gate of the high voltage field effect transistor; The source and gate of the first PMOS transistor are connected to the high-frequency clock input signal through a first capacitor, and the source and gate of the second PMOS transistor are connected to Vcc through a second capacitor.

In a preferred embodiment, the gate-on voltage generator further has a comparator and a reference voltage Vref, and the output voltage value of the gate-on voltage generator is controlled through the comparator according to the reference voltage Vref.

In a preferred embodiment: a clamping circuit and a second gate turn-on voltage generator are further included, and the input of the clamping circuit is from the second gate turn-on voltage generator, which is used as a reference voltage of the clamping voltage;

The output of the clamping circuit is connected to the gate terminal of the high withstand voltage field effect transistor.

A bootstrap voltage circuit provided by the present invention adopts the existing high withstand voltage NMOS driving transistor and low withstand voltage diode or parasitic diode in a process factory, plus an appropriate gate driving voltage of the high withstand voltage NMOS driving transistor to generate Replacing the external bootstrap diode, the purpose of cost reduction is achieved, and the difficulty of obtaining the built-in bootstrap diode is solved.

Description of drawings

FIG. 1 is the background technology of the present invention, a typical application diagram of an external bootstrap diode.

FIG. 2 is a circuit diagram of a typical gate drive internal module in the background of the present invention.

3 is a circuit diagram of a high-voltage NMOS driving transistor and a low-voltage diode in the background technology of the present invention.

FIG. 4 is a block diagram of a preferred embodiment of the present invention.

FIG. 5 is a circuit diagram of the preferred embodiment 1 of the present invention.

FIG. 6 is a circuit diagram of the preferred embodiment 2 of the present invention.

FIG. 7 is a circuit diagram of the preferred embodiment 3 of the present invention.

FIG. 8 is a circuit diagram of a preferred embodiment 4 of the present invention.

FIG. 9 is a block diagram of the preferred embodiment 5 of the present invention.

FIG. 10 is a circuit diagram of the preferred embodiment 5 of the present invention.

Detailed ways

In order to make the technical solutions of the present invention clearer, the present invention will now be further described with reference to the embodiments and accompanying drawings.

First, a background technology is described first, which also uses a high-voltage NMOS driver tube and a low-voltage diode circuit. As shown in Figure 3, the circuit diagram of a high-voltage NMOS driver tube and a low-voltage diode is a high-voltage Bootstrap field effect transistor (bootstrap FET), its drain is connected to BOOT (that is, Vb), its source is connected to the cathode of the diode, and the anode of this diode is connected to Vcc. The gate of the bootstrap FET is driven by the line inside the dotted line below, which contains an inverter, a diode, and a capacitor. When the output of the inverter is high, the bootstrap FET is turned on. When the output of the inverter is low, the bootstrap FET is turned off. The input signal of the inverter and the control signals HVG and LVG that control the upper arm and lower arm power tubes need to be synchronized, and it is necessary to pay attention to the delay difference between them in order to make full use of the charging time in the first working stage. complex. Its working principle is that in the first working stage, the bootstrap FET is turned on, and Vcc charges BOOT (Vb) through the low-voltage diode through the turned-on bootstrap FET. . In the second working stage, the high withstand voltage bootstrap field effect transistor (bootstrap FET) is turned off at this time, so it is originally an external high withstand voltage bootstrap diode to prevent leakage and breakdown during high voltage reverse bias. Function, this time by the closed high voltage bootstrap field effect transistor to play. A low-voltage diode connected to the source of the bootstrap FET, since the bootstrap FET is in the off state, does not experience high voltage shocks.

Example 1

As an improvement to the above-mentioned prior art, the present embodiment provides a bootstrap voltage circuit, and its constituent elements and their connection relationships are first described below with the module of FIG. 4 . The components of the module of FIG. 4 include a low voltage diode, a high withstand voltage field effect transistor and a gate turn-on voltage generator. The anode of the low voltage diode is connected to Vcc, the cathode of the diode is connected to the source terminal of the high voltage field effect transistor, and the drain terminal of the high voltage field effect transistor is connected to Vb, which provides the power supply voltage of the upper arm circuit.

The output of the gate-on voltage generator is connected to the gate terminal of the high withstand voltage field effect transistor, and the input of the gate-on voltage generator is a high-frequency clock signal. The output of the gate turn-on voltage generator is Vcc plus the voltage that can turn on the high withstand voltage field effect transistor, which is 15V+5V=20V in this embodiment, and the voltage basically maintains a steady state and does not change.

Therefore, when the voltage of Vb is lower than the voltage of Vcc, the high voltage field effect transistor is turned on, and Vcc charges Vb through the low voltage diode and the high voltage field effect transistor. When the Vb voltage is raised to be greater than or close to Vcc, the high withstand voltage field effect transistor naturally enters the off state, and at the same time prevents the low voltage diode from being broken down by the high voltage.

Further referring to FIG. 5 , in this embodiment, the gate-on voltage generator is a charge pump circuit, which includes a first diode and a second two diodes connected in series between Vcc and the gate of the high voltage field effect transistor. A first capacitor is connected between the cathode of the first diode and the high-frequency clock input signal, and a second capacitor is connected between the cathode of the second diode and Vcc. The output voltage of the gate-on voltage generator in this embodiment is close to twice the Vcc voltage.

Example 2

Referring to FIG. 6 , the difference between this embodiment and Embodiment 1 is that the gate turn-on voltage generator is a charge pump circuit, which includes a first NMOS transistor connected in series between Vcc and the gate of the high voltage field effect transistor and a second NMOS tube; a first capacitor is connected between the drain of the first NMOS tube and the high-frequency clock input signal, and a second capacitor is connected between the drain of the second NMOS tube and Vcc;

The gate of the first NMOS transistor is connected to the source, and the gate of the second NMOS transistor is connected to the source.

Example 3

Referring to FIG. 7 , the difference between this embodiment and Embodiment 1 is that the gate turn-on voltage generator is a charge pump circuit, which includes a first PMOS transistor connected in series between Vcc and the gate of the high voltage field effect transistor and the second PMOS tube; the source and gate of the first PMOS tube are connected, and are connected to the high-frequency clock input signal through the first capacitor, and the source and gate of the second PMOS tube are connected, and are connected through the second capacitor. Connect with Vcc.

Example 4

Referring to FIG. 8 , the difference between this embodiment and Embodiment 1 is that the gate turn-on voltage generator also has a comparator and a reference voltage Vref, and the gate turn-on voltage generator is controlled through the comparator according to the reference voltage Vref. output voltage value.

Example 5

There is a parasitic capacitance between the drain terminal and the gate terminal of the high withstand voltage field effect transistor. When the upper arm power tube is turned on, Vb(BOOT) will generate a rising edge, and this rising edge will pass through the high withstand voltage field effect transistor. The parasitic capacitance of the gate terminal is coupled to the gate terminal of the high withstand voltage field effect transistor to generate a spur.

In order to solve this problem, in this embodiment, referring to FIG. 9 and FIG. 10 , a clamping circuit and a second gate turn-on voltage generator are further included, and the input of the clamping circuit comes from the second gate turn-on voltage generator, which serves as a clamp The reference voltage of the voltage;

The output of the clamping circuit is connected to the gate terminal of the high withstand voltage field effect transistor, so as to avoid the voltage spike at the gate terminal.

The clamping circuit is composed of a comparator and an NMOS transistor

The above are only the preferred embodiments of the present invention, but the scope of the present invention is not limited thereto, and those skilled in the art can easily think of variations or technical scopes disclosed in the present invention. Alternatives are intended to be included within the scope of this invention. Therefore, the protection scope of the present invention should be determined by the scope of the claims.

Claims (8)

1. a kind of bootstrap voltage mode route, it is characterised in that: using low pressure diode, high voltage field effect transistor substitution bootstrapping two Pole pipe further includes gate turn-on voltage generator；

When the upper arm line power voltage Vb of bootstrap voltage mode route is less than the power source voltage Vcc of lower arm circuit, the grid is opened The output voltage for opening voltage generator is in the open state by high voltage field effect transistor, and Vcc passes through low pressure diode and height Pressure-resistant field effect transistor charges to Vb voltage；When the upper arm line power voltage Vb of bootstrap voltage mode route is greater than or close to lower arm When the power source voltage Vcc of circuit, the high voltage field effect transistor is in an off state.

2. a kind of bootstrap voltage mode route according to claim 1, it is characterised in that: the low pressure diode anode is connected to Vcc, the cathode of low pressure diode are connected to the source of high voltage field effect transistor, and the drain terminal of high voltage field effect transistor connects It is connected to Vb；

The output of the gate turn-on voltage generator is connected to the grid end of high voltage field effect transistor, and gate turn-on voltage produces The input of raw device is a high frequency clock signal.

3. a kind of bootstrap voltage mode route according to claim 2, it is characterised in that: the gate turn-on voltage generator Output voltage is close to 2 times of Vcc voltages.

4. a kind of bootstrap voltage mode route according to claim 3, it is characterised in that: the gate turn-on voltage generator is Charge pump route comprising the first diode being connected in series between Vcc and high voltage field effect transistor gate and second Diode；It is connected with first capacitor between the cathode and high frequency clock input signal of the first diode, the second diode The second capacitor is connected between cathode and Vcc.

5. a kind of bootstrap voltage mode route according to claim 3, it is characterised in that: the gate turn-on voltage generator is Charge pump route comprising the first NMOS tube and second being connected in series between Vcc and high voltage field effect transistor gate NMOS tube；The drain electrode of first NMOS tube is connected with first capacitor, the second NMOS tube between high frequency clock input signal Drain electrode and Vcc between be connected with the second capacitor；

The grid of first NMOS tube is connected with source electrode, and the grid of the second NMOS tube is connected with source electrode.

6. a kind of bootstrap voltage mode route according to claim 3, it is characterised in that: the gate turn-on voltage generator is Charge pump route comprising the first PMOS tube and second being connected in series between Vcc and high voltage field effect transistor gate PMOS tube；The source electrode of first PMOS tube is connected with grid, and is connect by first capacitor with high frequency clock input signal, The source electrode of second PMOS tube is connected with grid, and is connect by the second capacitor with Vcc.

7. a kind of bootstrap voltage mode route according to claim 1 to 6, it is characterised in that: the grid opens electricity Pressing also has comparator and reference voltage Vref inside generator, opened according to reference voltage Vref through comparator to control grid Open the output voltage values of voltage generator.

8. a kind of bootstrap voltage mode route according to claim 1 to 6, it is characterised in that: further include clamper route Input with second grid cut-in voltage generator, clamper route comes from second grid cut-in voltage generator, as clamper electricity The reference voltage of pressure；

The output of clamper route is connected to the grid end of high voltage field effect transistor.