CN106712469A - Gate drive circuit used for charge pump - Google Patents

Abstract

The invention provides a gate drive circuit used for a charge pump, and belongs to the technical field of an analog integrated circuit. The drive circuit is suitable for a switching type charge pump and power supply is realized by the output voltage Vcp of the charge pump without additional power supply voltage. The drain electrode of a first PMOS transistor MA1 outputs first power supply voltage V1, and the drain electrode of a third PMOS transistor MA3 outputs second power supply voltage V2. The power supply voltage can effectively provide drive voltage required for each gate electrode of the suitable charge pump so that correct startup and turn-off of each switching device in the working cycle can be realized, the voltage loss of the charge pump in each multiplication process can be reduced and the conversion efficiency can be enhanced; and a second capacitor CA2 and a fourth capacitor CA4 are introduced so as to reduce the power consumption of the gate drive circuit.

Description

A gate drive circuit for a charge pump

technical field

The invention belongs to the technical field of analog integrated circuits, and in particular relates to a gate drive circuit for a charge pump.

Background technique

The applicable charge pump of the present invention is used for the low-dropout linear voltage regulator LDO of the N-type regulator tube, and needs about twice the V _charge voltage, as shown in FIG. 1 .

In the field of analog integrated circuit design, the charge pump acts as a voltage multiplier and is an important part of it.

As shown in Figure 2, the traditional Dickson charge pump is composed of diode-connected PMOS or NMOS in series. During the working process of the charge pump, the voltage of the previous stage charges the capacitor of the latter stage, and the charging path has the substrate parasitic diode of the MOS transistor. This results in the loss of the forward conduction voltage drop of the PN junction for every MOS transistor connected by a diode. The advantage of the traditional charge pump circuit is that the circuit structure is simple, but the disadvantage is that each stage of voltage gain will have a large voltage loss, which will affect the efficiency.

The switch-type Dickson charge pump is shown in Figure 3. The gain of each stage is realized by a switch-type MOS tube, which can effectively reduce the voltage loss during the multiplication process of each stage. But the difficulty lies in that, for each switch tube, a gate voltage that ensures the normal shutdown of the switch tube without leakage will be given.

Contents of the invention

In view of the above difficulties, the present invention proposes a gate drive circuit for a switch-type Dickson charge pump. The present invention does not need an additional power supply voltage, but realizes power supply through the output voltage V _cp of the charge pump itself, and the power supply voltage can effectively provide the driving voltage required by the gates of each stage of the charge pump, and realize that the switching devices of each stage are working correct turn-on and turn-off during the cycle.

Technical scheme of the present invention is as follows:

A gate drive circuit for a charge pump, comprising a first PMOS transistor MA1, a second PMOS transistor MA2, a third PMOS transistor MA3, a fourth PMOS transistor MA4, a first NMOS transistor MA5, a second NMOS transistor MA6, a Three NMOS transistors MA7, first transistor QA1, second transistor QA2, first capacitor CA1, second capacitor CA2, third capacitor CA3, fourth capacitor CA4, first inverter INV1, second inverter Device INV2 and current source I _b ;

The first triode QA1 and the second triode QA2 adopt a diode connection form, and their bases and collectors are interconnected and connected to the power supply voltage V _CP ;

The current source _Ib provides current bias for the current mirror composed of the first NMOS transistor MA5, the second NMOS transistor MA6 and the third NMOS transistor MA7, the first NMOS transistor MA5, the second NMOS transistor MA6 and the third NMOS transistor MA7 The aspect ratio is 1:1:1, and the current source _Ib is connected to the gates of the first NMOS transistor MA5, the second NMOS transistor MA6, the third NMOS transistor MA7 and the drain of the third NMOS transistor MA7; the first NMOS transistor MA5 , the sources of the second NMOS transistor MA6 and the third NMOS transistor MA7 are grounded;

The drain of the second NMOS transistor MA6 is connected to the gate and drain of the fourth PMOS transistor MA4 and the gate of the third PMOS transistor MA3, and the drain of the first NMOS transistor MA5 is connected to the gate and drain of the second PMOS transistor MA2 and the gate of the first PMOS transistor MA1; the sources of the third PMOS transistor MA3 and the fourth PMOS transistor MA4 are connected and connected to the emitter of the first triode QA1, and the sources of the first PMOS transistor MA1 and the second PMOS transistor MA2 Pole connected and connected to the emitter of the second triode QA2;

The first capacitor CA1 is connected between the drain of the first PMOS transistor MA1 and the output terminal of the second inverter INV2, and the second capacitor CA2 is connected between the drain of the second PMOS transistor MA2 and the input of the second inverter INV2 Between the terminals, the third capacitor CA3 is connected between the drain of the third PMOS transistor MA3 and the output terminal of the first inverter INV1, and the fourth capacitor CA4 is connected between the drain of the fourth PMOS transistor MA4 and the first inverter INV1 Between the input and output terminals of the inverter INV1; the input terminal of the first inverter INV1 is connected to the clock signal CLK, and the input terminal of the second inverter INV2 is connected to the reverse clock signal CLKB.

Specifically, the gate drive circuit is suitable for a switch-type charge pump.

Specifically, the drain of the first PMOS transistor MA1 outputs the first power supply voltage V1, and the drain of the third PMOS transistor MA3 outputs the second power supply voltage V2, which are respectively connected to the gates of the charge pump PMOS transistors used, Provides the drive voltage required for the gates of the charge pump stages.

Specifically, the supply voltage V _CP is the output voltage of the charge pump used.

The beneficial effects of the present invention are: the power supply is realized through the output voltage V _cp of the charge pump itself, and no additional power supply voltage is needed; the power supply voltage generated by the present invention can effectively provide the drive required by the gates of the applicable charge pump stages Voltage, to realize the correct turn-on and turn-off of each stage switching device in the working cycle, reduce the voltage loss of the charge pump in the multiplication process of each stage, and improve the conversion efficiency; the introduction of the second capacitor CA2 and the fourth capacitor CA4 reduces the gate voltage. The power consumption of the pole drive circuit itself.

Description of drawings

FIG. 1 is an explanatory diagram of application of a charge pump to which the present invention is applied.

FIG. 2 is a schematic structural diagram of a traditional Dickson charge pump.

FIG. 3 is a schematic structural diagram of a typical switch-type Dickson charge pump applicable to the present invention.

FIG. 4 is a schematic diagram of a gate drive circuit for a charge pump provided by the present invention.

FIG. 5 is a timing diagram of a gate drive circuit for a charge pump provided by the present invention.

detailed description

Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

The present invention uses a PMOS switch tube to replace a traditional diode-connected MOS tube, so as to reduce the problem of voltage loss in the multiplication process. Figure 3 is a typical switch-type charge pump, there are 2 switch-type PMOSs, and their gate voltages are V1 and V2 respectively. In order to achieve efficient voltage multiplication, it is necessary to provide accurate gate drive signals to ensure strict turn-on and turn-off of MOS transistors at all levels.

The following is the working principle of the 2x charge pump shown in Figure 3:

The input signals are VIN, CLK and the gate drive signals of each switch tube. In some embodiments, the input signal VIN is 5V, and CLK is a clock signal generated by an oscillator. It is assumed that the high potential of the clock is 5V and the low potential is 0.

The input signal is 5V, the gate voltage V1 of the M1 tube is low, the M1 tube is turned on, and the CLK is low, and the input charges the capacitor C1. At this time, the gate voltage V2 of the M2 tube is high, and the M2 is turned off. When CLK jumps high, the voltage of the positive plate of capacitor C1 is raised to about 10V. At this time, the gate voltage of M1 tube is high, the gate voltage of M2 tube is low, M1 tube is turned off, M2 tube is turned on, and capacitor C2 is charged. To turn off the M1 tube at this time, the voltage of the gate voltage V1 of the M1 tube must be close to about 10V. To turn off the M2 tube, the gate voltage V2 of the M2 tube needs to be about 10V.

According to the above analysis of the circuit principle of the 2-fold charge pump in Figure 3, the maximum voltages of the two gates we need to obtain are 10V and 10V respectively. In order for the two switch tubes to be turned on normally, the gate voltage of the gate voltage V1 of the M1 tube must be lower than 5V-|V _thp |, where V _thp is the threshold voltage of the PMOS tube, and the lowest voltage of the gate voltage V2 of the M2 tube To be lower than 10-|V _thp |.

The gate drive circuit for the charge pump shown in FIG. 3 provided by the present invention is shown in FIG. 4 .

Including the first PMOS transistor MA1, the second PMOS transistor MA2, the third PMOS transistor MA3, the fourth PMOS transistor MA4, the first NMOS transistor MA5, the second NMOS transistor MA6, the third NMOS transistor MA7, the first triode QA1, The second triode QA2, the first capacitor CA1, the second capacitor CA2, the third capacitor CA3, the fourth capacitor CA4, the first inverter INV1, the second inverter INV2 and the current source _Ib ;

The first triode QA1 and the second triode QA2 adopt a diode connection form, and their bases and collectors are interconnected and connected to the power supply voltage V _CP ;

The current source _Ib provides current bias for the current mirror composed of the first NMOS transistor MA5, the second NMOS transistor MA6 and the third NMOS transistor MA7, the first NMOS transistor MA5, the second NMOS transistor MA6 and the third NMOS transistor MA7 The aspect ratio is 1:1:1, and the current source _Ib is connected to the gates of the first NMOS transistor MA5, the second NMOS transistor MA6, the third NMOS transistor MA7 and the drain of the third NMOS transistor MA7; the first NMOS transistor MA5 , the sources of the second NMOS transistor MA6 and the third NMOS transistor MA7 are grounded;

The drain of the second NMOS transistor MA6 is connected to the gate and drain of the fourth PMOS transistor MA4 and the gate of the third PMOS transistor MA3, and the drain of the first NMOS transistor MA5 is connected to the gate and drain of the second PMOS transistor MA2 and the gate of the first PMOS transistor MA1; the sources of the third PMOS transistor MA3 and the fourth PMOS transistor MA4 are connected and connected to the emitter of the first triode QA1, and the sources of the first PMOS transistor MA1 and the second PMOS transistor MA2 Pole connected and connected to the emitter of the second triode QA2;

The first capacitor CA1 is connected between the drain of the first PMOS transistor MA1 and the output terminal of the second inverter INV2, and the second capacitor CA2 is connected between the drain of the second PMOS transistor MA2 and the input of the second inverter INV2 Between the terminals, the third capacitor CA3 is connected between the drain of the third PMOS transistor MA3 and the output terminal of the first inverter INV1, and the fourth capacitor CA4 is connected between the drain of the fourth PMOS transistor MA4 and the first inverter INV1 Between the input and output terminals of the inverter INV1; the input terminal of the first inverter INV1 is connected to the clock signal CLK, and the input terminal of the second inverter INV2 is connected to the reverse clock signal CLKB.

Because the output of the charge pump is about 10V, and the highest voltage of the gate drive is also about 10V, the output V _CP of the charge pump can be used as the power supply voltage of the gate drive circuit.

The power supply of the inverters INV1 and INV2 is 5V. CLK is a clock signal, CLKB is a clock signal opposite to CLK, and the highest voltage is 5V.

When the clock signal CLK is low, the output voltage V4 of the inverter INV1 is high, and the third capacitor CA3 raises the drain voltage V2 of the third PMOS transistor MA3 to V4+V _CA3 , causing the third PMOS transistor MA3 to enter the linear region , V2=V _CP -V _be , V _be is the BE junction voltage of the first diode QA1, at this time, CLKB is high, and the voltage on the positive plate of the capacitor CA2 is raised to a very high value by the second capacitor CA2, The second PMOS transistor MA2 and the first PMOS transistor MA1 are thus turned off, and the drain voltage V1 of the first PMOS transistor MA1 is maintained at V _CA1 ; when the clock signal CLK is high, the output voltage V4 of the inverter INV1 is Low, the fourth capacitor CA4 raises the positive plate voltage of the capacitor to a very high value, the third PMOS transistor MA3 and the fourth PMOS transistor MA4 are turned off, and the drain voltage V2 of the third PMOS transistor MA3 is maintained at V _CA3 , at this time, CLKB is low, the output voltage V3 of the inverter INV2 is high, and the drain voltage V1 of the first PMOS transistor MA1 is raised to V3+V _CA1 , causing the first PMOS transistor MA1 to enter the linear region, V1=V _CP -V _be .

The situation described above is the voltage change situation of the final steady state. The voltage on the actual capacitor is a process that increases every cycle. Due to the limitation of the circuit reaching a steady state, the lowest voltage of the drain voltage V1 of the first PMOS transistor MA1 can only reach 5V-|V _thp | in the end, and the voltage of the drain voltage V2 of the third PMOS transistor MA3 is finally affected by each cycle Limits the bias current to charge capacitor CA3.

The second capacitor CA2 and the fourth capacitor CA4 mainly have two functions. The first one is that when the clock signal CLK is high, the voltage of the positive plate of the fourth capacitor CA4 can be raised to the point where the third PMOS transistor MA3 and the fourth PMOS transistor MA4 are turned off, then the left half of the driving circuit will not generate power consumption; similarly, when CLKB is high, the second capacitor CA2 also has the same effect. The second function is that when the third PMOS transistor MA3 and the fourth PMOS transistor MA4 are turned off, the voltage of the drain voltage V2 of the third PMOS transistor MA3 will be maintained at a stable low level, instead of a voltage being controlled by the third PMOS transistor MA3. The drain current of the transistor MA3 is charged with a slowly rising ramp-like level; similarly, the second capacitor CA2 also has a similar effect.

Organize the timing of V2, V1 and CLK, CLKB in Figure 4: if CLK is high, V1, V3 are high, V2, V4 are low; if CLK is low, V1, V3 are low, V2, V4 are high. The voltages corresponding to the double charge pump in FIG. 3 are: the drain voltage V1 of the first PMOS transistor MA1 corresponds to the gate voltage of the M1 transistor, and the drain voltage V2 of the third PMOS transistor MA3 corresponds to the gate voltage of the M2 transistor. The simulation diagram of the drive circuit is shown in Figure 5.

To sum up, the present invention proposes a precise gate drive circuit for the switch-type Dickson charge pump, which realizes the complete opening and closing of the switch MOS transistors at all levels in the normal switching cycle, which greatly reduces the charge pump at each stage. The voltage loss during the doubling process improves the conversion efficiency. The gate drive circuit uses the output voltage of its own charge pump as the power supply voltage, avoiding the introduction of an additional power supply. At the same time, the second capacitor CA2 and the fourth capacitor CA4 are introduced to reduce the power consumption of the gate drive circuit itself.

Those skilled in the art will appreciate that the embodiments described here are to help readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (4)

1. A gate drive circuit for a charge pump, comprising a first PMOS transistor (MA1), a second PMOS transistor (MA2), a third PMOS transistor (MA3), a fourth PMOS transistor (MA4), a first NMOS transistor tube (MA5), second NMOS tube (MA6), third NMOS tube (MA7), first transistor (QA1), second transistor (QA2), first capacitor (CA1), second capacitor ( CA2), the third capacitor (CA3), the fourth capacitor (CA4), the first inverter (INV1), the second inverter (INV2) and the current source (I _b ); The first triode (QA1) and the second triode (QA2) adopt a diode connection form, and their bases and collectors are interconnected and connected to the power supply voltage (V _CP ); The current source (I _b ) provides current bias for the current mirror composed of the first NMOS transistor (MA5), the second NMOS transistor (MA6) and the third NMOS transistor (MA7). The first NMOS transistor (MA5), the second The width-to-length ratio of the NMOS transistor (MA6) and the third NMOS transistor (MA7) is 1:1:1; the current source (I _b ) is connected to the first NMOS transistor (MA5), the second NMOS transistor (MA6) and the third NMOS transistor The gate of the tube (MA7) and the drain of the third NMOS tube (MA7); the sources of the first NMOS tube (MA5), the second NMOS tube (MA6) and the third NMOS tube (MA7) are grounded; The drain of the second NMOS transistor (MA6) is connected to the gate and drain of the fourth PMOS transistor (MA4) and the gate of the third PMOS transistor (MA3), and the drain of the first NMOS transistor (MA5) is connected to the second PMOS The grid and drain of the tube (MA2) and the grid of the first PMOS tube (MA1); the sources of the third PMOS tube (MA3) and the fourth PMOS tube (MA4) are connected and connected to the first triode (QA1 ), the source of the first PMOS transistor (MA1) and the second PMOS transistor (MA2) is connected and connected to the emitter of the second triode (QA2); The first capacitor (CA1) is connected between the drain of the first PMOS transistor (MA1) and the output terminal of the second inverter (INV2), and the second capacitor (CA2) is connected to the drain of the second PMOS transistor (MA2). Between the pole and the input terminal of the second inverter (INV2), the third capacitor (CA3) is connected between the drain of the third PMOS transistor (MA3) and the output terminal of the first inverter (INV1). The four capacitors (CA4) are connected between the drain of the fourth PMOS transistor (MA4) and the input and output terminals of the first inverter (INV1); the input terminal of the first inverter (INV1) is connected to the clock signal (CLK) , the input terminal of the second inverter (INV2) is connected to the inverted clock signal (CLKB). 2. A gate drive circuit for a charge pump according to claim 1, wherein the gate drive circuit is suitable for a switch-type charge pump. 3. A gate drive circuit for a charge pump according to claim 1, characterized in that, the drain of the first PMOS transistor (MA1) outputs a first supply voltage (V1), and the third The drain of the PMOS transistor (MA3) outputs the second supply voltage (V2), which is respectively connected to the gates of the charge pump MOS transistors used to provide the driving voltage required by the gates of the charge pump stages. 4. A gate drive circuit for a charge pump according to claim 1, wherein the supply voltage (V _CP ) is the output voltage of the charge pump used.