CN109904063A - MEMS device and its manufacturing method - Google Patents
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Abstract
The invention discloses a kind of MEMS device, comprising: the main part of MEMS device is formed on the first Silicon Wafer, and CMOS integrated circuit is formed on the second Silicon Wafer.It realizes that eutectic is strong by the strong conjunction structure of eutectic between first and second Silicon Wafers to close；Strong the first bonded layer for closing structure of eutectic includes the germanium layer being formed on the first Silicon Wafer, and the second bonded layer is the top layer metallic layer for being formed in the second silicon wafer surface；It is also formed on the first Silicon Wafer and the limiting structure and bonded substrate layer that chemical wet etching is formed simultaneously is carried out by first medium layer, the inner evenness of the etching of first medium layer is greater than the inner evenness of silicon etching, and the first bonded layer is formed in the surface of bonded substrate layer and extends to external silicon and form the contact with silicon.The invention also discloses a kind of manufacturing methods of MEMS device.The present invention can improve the inner evenness of device, to improve the performance of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit, more particularly to a kind of MEMS device.The invention further relates to a kind of MEMS
The manufacturing method of device.
Background technique
It is the device architecture schematic diagram in each step of manufacturing method of existing MEMS device as shown in Figure 1A to Fig. 1 F, it is existing
There is method to include the following steps:
As shown in Figure 1A, Silicon Wafer 101 is provided.
As shown in Figure 1B, the etching for carrying out silicon forms limiting structure (stopper) 102 on the surface of Silicon Wafer 101, simultaneously
Bonded substrate layer 102a is formed, the position of the two is defined using photoetching process.In Figure 1B, limiting structure 102 is arranged in Silicon Wafer
At 101 both sides of the edge.
As shown in Figure 1 C, side wall 102b is formed in the side of limiting structure 102 and bonded substrate layer 102a.
As shown in figure iD, the first bonded layer 103 is formed on the surface of bonded substrate layer 102a.In existing method, the first key
It closes layer 103 and generallys use germanium layer, by first depositing germanium layer, carry out photoetching again later and select forming region, then perform etching and to be formed
It is only located at the structure on the surface bonded substrate layer 102a.
As referring to figure 1E, the main part 104 of MEMS device, the main body of the MEMS device are formed in Silicon Wafer 101
Part 104 includes fixed electrode and movable electrode, is separated with groove between fixing between electrode and movable electrode.Main part 104 is main
If forming what groove was formed by carrying out silicon etching, i.e., first using the selected region for needing to form groove of photoetching, later again into
Row etching forms groove, and groove needs to cut through Silicon Wafer 101.
As shown in fig. 1F, the Silicon Wafer 105 for being formed with CMOS integrated circuit 106, the top of CMOS integrated circuit 106 are provided
It is formed with interlayer film, there is metal layer between each layer interlayer film, wherein top layer metallic layer (TM) is used as the second bonded layer, top-gold
The material for belonging to layer is usually aluminium.
Situation when Fig. 1 F show the first bonded layer 103 and the second bonded layer has just been directed at contact, it is subsequent to need to carry out germanium
Eutectic bonding between aluminium forms eutectic bonding structure, carries out eutectic bonding between the first bonded layer 103 and the second bonded layer
Afterwards, Silicon Wafer 101 and the second Silicon Wafer 105 can be bonded together, and realize electrical connection.In eutectic bonding, the first bonded layer
103 and second the superposition thickness of bonded layer can gradually decrease, wherein limiting structure 102 is exactly to limit the first bonded layer 103
Minimum thickness after being bonded with the second bonded layer, if also just the superposition thickness of the first bonded layer 103 and the second bonded layer is too small
When, the surface of limiting structure 102 will withstand the surface of Silicon Wafer 105, to prevent the first bonded layer 103 and the second bonded layer
Superposition thickness continue to reduce.
In Fig. 1 F, the bottom panel (Bottom positioned at 104 bottom of main part is also formed on the surface of Silicon Wafer 105
Plate) structure 107 further include liner (Pad) structure 108 for the exit of the extraction of CMOS integrated circuit 106.
In existing method, in the step shown in Figure 1B, the height of limiting structure 102 is usually 2 microns~3 microns, is made
The etch amount that must carry out silicon etching is 2 microns~3 microns.So thick silicon etching is easy to produce in wafer (Within
Wafer, WIW) the poor defect of uniformity, so that the offspring of the height of the limiting structure 102 and bonded substrate layer 102a that are formed
Uniformity is also all poor, can finally beat the performance requirement less than MEMS device.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of MEMS device, can improve the inner evenness of device, from
And improve the performance of device.For this purpose, the present invention also provides a kind of manufacturing methods of MEMS device.
In order to solve the above technical problems, MEMS device provided by the invention includes:
First Silicon Wafer, the main part of MEMS device are formed on first Silicon Wafer, the master of the MEMS device
Body portion includes fixed electrode and movable electrode, is separated with groove between fixing between electrode and movable electrode.
Second Silicon Wafer, CMOS integrated circuit are formed on second Silicon Wafer, and the top of CMOS integrated circuit is formed
There is multilayer interlayer film, there is metal layer between each layer interlayer film.
It realizes that eutectic is strong by the strong conjunction structure of eutectic between first Silicon Wafer and second Silicon Wafer to close.
Strong the first bonded layer for closing structure of the eutectic includes the germanium layer being formed on first Silicon Wafer, the second bonding
Layer is the top layer metallic layer for being formed in second silicon wafer surface.
Limiting structure and bonded substrate layer, the limiting structure and the bonding are also formed on first Silicon Wafer
Substrate layer is formed simultaneously by carrying out chemical wet etching to the first medium layer for being formed in first silicon wafer surface, described the
The inner evenness of the etching of one dielectric layer is greater than the inner evenness of silicon etching, to improve the limiting structure and the key
Close the inner evenness of the height of substrate layer.
The forming region of first bonded layer is arranged in the bonded substrate layer, and first bonded layer is formed in institute
State top surface and side and the surface for extending to first Silicon Wafer outside the bonded substrate layer of bonded substrate layer, institute
The first bonded layer is stated to contact by the silicon of the part and first Silicon Wafer that extend to outside the bonded substrate layer.
First bonded layer and second bonded layer thickness during eutectic bonding can be reduced, the limiting structure
For limiting the minimum thickness of the eutectic bonding structure.
A further improvement is that side wall is also formed in the side of the bonded substrate layer, to promote the bonding lining
The side gradient of bottom.
A further improvement is that being also formed with side wall in the side of the limiting structure.
A further improvement is that the material of the first medium layer is oxide layer, the material of the side wall is oxide layer.
A further improvement is that the height of the limiting structure is 2 microns~3 microns.
A further improvement is that first bonded layer further includes Ti and TiN layer, the germanium layer is located at the Ti and TiN
The contact of the silicon of the surface of layer, the Ti and TiN layer and first Silicon Wafer simultaneously forms Titanium silicide in contact position.
A further improvement is that the material of the top layer metallic layer is aluminium.
In order to solve the above technical problems, the manufacturing method of MEMS device provided by the invention includes the following steps:
Step 1: providing the first Silicon Wafer, first medium layer is formed on the surface of first Silicon Wafer.
Step 2: lithographic definition goes out the forming region of limiting structure and bonded substrate layer, the first medium is carried out later
The etching of layer forms the limiting structure and bonded substrate layer, and the inner evenness of the etching of the first medium layer is carved greater than silicon
The inner evenness of erosion, to improve the inner evenness of the height of the limiting structure and the bonded substrate layer.
Step 3: forming the first bonded layer on the surface of first Silicon Wafer and carrying out photoetching to first bonded layer
And etching technics, first bonded layer includes germanium layer, and first bonded layer after etching is formed in the bonded substrate layer
Top surface and side and the surface for extending to first Silicon Wafer outside the bonded substrate layer, first bonded layer
Pass through the silicon contact of the part and first Silicon Wafer that extend to outside the bonded substrate layer.
Step 4: adding the method for etching in the main part of first Silicon Wafer formation MEMS device using lithographic definition
Including fixed electrode and movable electrode, it is separated between fixing between electrode and movable electrode and shape is performed etching to first Silicon Wafer
At groove.
Step 5: providing the second Silicon Wafer, CMOS integrated circuit, the CMOS collection are formed on second Silicon Wafer
At multilayer interlayer film is formed at the top of circuit, there is metal layer between each layer interlayer film；Second silicon wafer surface
Top layer metallic layer be the second bonded layer.
The strong conjunction of eutectic is formed Step 6: first bonded layer and second bonded layer are contacted and carry out eutectic bonding
Structure；First bonded layer and second bonded layer thickness during eutectic bonding can be reduced, and the limiting structure is used
In the minimum thickness for limiting the eutectic bonding structure.
A further improvement is that step 2 is after forming the bonded substrate layer, it further include in the bonded substrate layer
Side formed side wall the step of, to promote the side gradient of the bonded substrate layer.
A further improvement is that in the side of the limiting structure while side of the bonded substrate layer forms side wall
Face also forms side wall.
A further improvement is that the material of the first medium layer is oxide layer, the material of the side wall is oxide layer.
A further improvement is that the height of the limiting structure is 2 microns~3 microns.
A further improvement is that in step 3, first bonded layer further includes Ti and TiN layer, be initially formed the Ti and
TiN layer forms the germanium layer on the surface of the Ti and TiN layer again later.
Later, carry out rapid thermal treatment is further comprised the steps of:, the Ti and TiN layer and the silicon of first Silicon Wafer is made to exist
Contact position forms Titanium silicide.
A further improvement is that the material of the top layer metallic layer is aluminium.
A further improvement is that it is 400 DEG C that the process conditions of the eutectic bonding of step 6, which include: temperature, pressure is
20kN~40kN.
The present invention carries out chemical wet etching using the first medium layer different from silicon in the main part for forming MEMS device
The limiting structure and bonded substrate layer of formation, relative to silicon etching, the etching technics of first medium layer is more easier to control, and can make
The inner evenness of the etching of first medium layer is greater than the inner evenness of silicon etching, to improve limiting structure and bonded substrate
The inner evenness of the height of layer, finally can improve the inner evenness of entire device and improve the performance of device.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Fig. 1 F is the device architecture schematic diagram in each step of manufacturing method of existing MEMS device；
Fig. 2 is the structural schematic diagram of MEMS device of the embodiment of the present invention；
Fig. 3 A- Fig. 3 H is the device architecture schematic diagram in each step of manufacturing method of MEMS device of the embodiment of the present invention.
Specific embodiment
As shown in Fig. 2, being the structural schematic diagram of MEMS device of the embodiment of the present invention, MEMS device packet of the embodiment of the present invention
It includes:
First Silicon Wafer 1, the main part 3 of MEMS device are formed on first Silicon Wafer 1, the MEMS device
Main part 3 includes fixed electrode and movable electrode, is separated with groove between fixing between electrode and movable electrode.
Second Silicon Wafer 2, CMOS integrated circuit 9 are formed on second Silicon Wafer 2, the top of CMOS integrated circuit 9
It is formed with multilayer interlayer film, there is metal layer between each layer interlayer film.
It realizes that eutectic is strong by the strong conjunction structure of eutectic between first Silicon Wafer 1 and second Silicon Wafer 2 to close.
Strong the first bonded layer for closing structure of the eutectic includes the germanium layer 8 being formed on first Silicon Wafer 1, the second key
Closing layer is the top layer metallic layer for being formed in 2 surface of the second Silicon Wafer.
It is also formed with limiting structure 4 and bonded substrate layer 5 on first Silicon Wafer 1, the limiting structure 4 and described
Bonded substrate layer 5 is by carrying out chemical wet etching shape simultaneously to the first medium layer 201 for being formed in 1 surface of the first Silicon Wafer
At the inner evenness of the etching of the first medium layer 201 is greater than the inner evenness of silicon etching, to improve the limitation
The inner evenness of structure 4 and the height of the bonded substrate layer 5, first medium layer 201 please refer to shown in Fig. 3 B.
The forming region of first bonded layer is arranged in the bonded substrate layer 5, and first bonded layer is formed in
The top surface of the bonded substrate layer 5 and side and the table for extending to first Silicon Wafer 1 outside the bonded substrate layer 5
Face, first bonded layer are contacted by the silicon of the part and first Silicon Wafer 1 that extend to outside the bonded substrate layer 5.
First bonded layer and second bonded layer thickness during eutectic bonding can be reduced, the limiting structure
4 for limiting the minimum thickness of the eutectic bonding structure.
It is also formed with side wall 6 in the side of the bonded substrate layer 5, the side to promote the bonded substrate layer 5 is inclined
Gradient.
Side wall 6 is also formed in the side of the limiting structure 4.
The material of the first medium layer 201 is oxide layer, and the material of the side wall 6 is oxide layer.
The height of the limiting structure 4 is 2 microns~3 microns.
First bonded layer further includes Ti and TiN layer 7, and the germanium layer 8 is located at the surface of the Ti and TiN layer 7, described
The contact of the silicon of Ti and TiN layer 7 and first Silicon Wafer 1 simultaneously forms Titanium silicide 7a in contact position.
The material of the top layer metallic layer is aluminium.The eutectic key of the eutectic bonding structure is Al-Ge eutectic key.
In Fig. 2, it is also formed with the bottom panel structure 10 positioned at 3 bottom of main part on the surface of the second Silicon Wafer 2, also
The gasket construction 11 of exit including the extraction for CMOS integrated circuit 9
The embodiment of the present invention formed MEMS device main part 3 on using different from silicon first medium layer 201 into
The limiting structure 4 and bonded substrate layer 5 that row chemical wet etching is formed, relative to silicon etching, the etching technics of first medium layer 201 is more
Add and be easy to control, the inner evenness of the etching of first medium layer 201 can be made to be greater than the inner evenness of silicon etching, to improve
The inner evenness of the height of limiting structure 4 and bonded substrate layer 5 can finally improve inner evenness and the raising of entire device
The performance of device.
It is that the device architecture in each step of manufacturing method of MEMS device of the embodiment of the present invention shows as shown in Fig. 3 A to Fig. 3 H
It is intended to, the manufacturing method of MEMS device of the embodiment of the present invention includes the following steps:
Step 1: as shown in Figure 3A, providing the first Silicon Wafer 1.As shown in Figure 3B, on the surface of first Silicon Wafer 1
Form first medium layer 201.
Step 2: as shown in Figure 3 C, lithographic definition goes out the forming region of limiting structure 4 and bonded substrate layer 5, carries out later
The etching of the first medium layer 201 forms the limiting structure 4 and bonded substrate layer 5, the etching of the first medium layer 201
Inner evenness be greater than silicon etching inner evenness, to improve the height of the limiting structure 4 and the bonded substrate layer 5
The inner evenness of degree.
It further include described after forming the bonded substrate layer 5 as shown in Figure 3D in present invention method
The side of bonded substrate layer 5 forms the step of side wall 6, to promote the side gradient of the bonded substrate layer 5.
Side wall is also formed in the side of the limiting structure 4 while the side of the bonded substrate layer 5 forms side wall 6
6.The side wall 6 is formed in the bonded substrate layer 5 and the limit using comprehensive etching autoregistration is carried out after deposited overall
The side of structure 4 processed.
The material of the first medium layer 201 is oxide layer, and the material of the side wall 6 is oxide layer.
The height of the limiting structure 4 is 2 microns~3 microns.
Step 3: as shown in FIGURE 3 E, forming the first bonded layer on the surface of first Silicon Wafer 1 and to first key
It closes layer and carries out lithography and etching technique, first bonded layer includes germanium layer 8, and first bonded layer after etching is formed in institute
State the top surface and side and the table for extending to first Silicon Wafer 1 outside the bonded substrate layer 5 of bonded substrate layer 5
Face, first bonded layer are contacted by the silicon of the part and first Silicon Wafer 1 that extend to outside the bonded substrate layer 5.
In present invention method, first bonded layer further includes Ti and TiN layer 7, is initially formed the Ti and TiN layer
7, the germanium layer 8 is formed on the surface of the Ti and TiN layer 7 again later.
Later, it further comprises the steps of: as illustrated in Figure 3 F, carries out rapid thermal treatment, make the Ti and TiN layer 7 and described first
The silicon of Silicon Wafer 1 forms Titanium silicide 7a in contact position.
Step 4: as shown in Figure 3 G, forming MEMS device in first Silicon Wafer 1 using the method for lithographic definition plus etching
The main part 3 of part includes fixed electrode and movable electrode, is separated between fixing between electrode and movable electrode to first silicon
Wafer 1 performs etching the groove to be formed.
Step 5: as shown in figure 3h, providing the second Silicon Wafer 2, the integrated electricity of CMOS is formed on second Silicon Wafer 2
Road 9, the top of the CMOS integrated circuit 9 are formed with multilayer interlayer film, have metal layer between each layer interlayer film；It is described
The top layer metallic layer on 2 surface of the second Silicon Wafer is the second bonded layer.
It is also formed with the bottom panel structure 10 positioned at 3 bottom of main part on the surface of the second Silicon Wafer 2, further includes using
In the gasket construction 11 of the exit of the extraction of CMOS integrated circuit 9
Step 6: as shown in figure 3h, first bonded layer and second bonded layer are contacted；As shown in Fig. 2, later
It carries out eutectic bonding and forms the strong conjunction structure of eutectic；First bonded layer and second bonded layer are thick during eutectic bonding
Degree can be reduced, and the limiting structure 4 is used to limit the minimum thickness of the eutectic bonding structure.
In present invention method, the material of the top layer metallic layer is aluminium.The process conditions packet of the eutectic bonding
Include: temperature is 400 DEG C, and pressure is 20kN~40kN.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of MEMS device characterized by comprising
First Silicon Wafer, the main part of MEMS device are formed on first Silicon Wafer, the main part of the MEMS device
Dividing includes fixed electrode and movable electrode, is separated with groove between fixing between electrode and movable electrode；
Second Silicon Wafer, CMOS integrated circuit are formed on second Silicon Wafer, are formed at the top of CMOS integrated circuit more
Layer interlayer film, has metal layer between each layer interlayer film；
It realizes that eutectic is strong by the strong conjunction structure of eutectic between first Silicon Wafer and second Silicon Wafer to close；
Strong the first bonded layer for closing structure of the eutectic includes the germanium layer being formed on first Silicon Wafer, and the second bonded layer is
It is formed in the top layer metallic layer of second silicon wafer surface；
Limiting structure and bonded substrate layer, the limiting structure and the bonded substrate are also formed on first Silicon Wafer
Layer is formed simultaneously by carrying out chemical wet etching to the first medium layer for being formed in first silicon wafer surface, and described first is situated between
The inner evenness of the etching of matter layer is greater than the inner evenness of silicon etching, to improve the limiting structure and bonding lining
The inner evenness of the height of bottom；
The forming region of first bonded layer is arranged in the bonded substrate layer, and first bonded layer is formed in the key
Close top surface and side and the surface for extending to first Silicon Wafer outside the bonded substrate layer of substrate layer, described the
One bonded layer is contacted by the silicon of the part and first Silicon Wafer that extend to outside the bonded substrate layer；
First bonded layer and second bonded layer thickness during eutectic bonding can be reduced, and the limiting structure is used for
Limit the minimum thickness of the eutectic bonding structure.
2. MEMS device as described in claim 1, it is characterised in that: be also formed with side in the side of the bonded substrate layer
Wall, to promote the side gradient of the bonded substrate layer.
3. MEMS device as claimed in claim 2, it is characterised in that: be also formed with side wall in the side of the limiting structure.
4. MEMS device as claimed in claim 2 or claim 3, it is characterised in that: the material of the first medium layer is oxide layer, institute
The material for stating side wall is oxide layer.
5. MEMS device as described in claim 1, it is characterised in that: the height of the limiting structure is 2 microns~3 microns.
6. MEMS device as described in claim 1, it is characterised in that: first bonded layer further includes Ti and TiN layer, described
Germanium layer is located at the silicon contact of the surface of the Ti and TiN layer, the Ti and TiN layer and first Silicon Wafer and in contact position shape
At Titanium silicide.
7. MEMS device as described in claim 1, it is characterised in that: the material of the top layer metallic layer is aluminium.
8. a kind of manufacturing method of MEMS device, which comprises the steps of:
Step 1: providing the first Silicon Wafer, first medium layer is formed on the surface of first Silicon Wafer；
Step 2: lithographic definition goes out the forming region of limiting structure and bonded substrate layer, the first medium layer is carried out later
Etching forms the limiting structure and bonded substrate layer, and the inner evenness of the etching of the first medium layer is greater than silicon etching
Inner evenness, to improve the inner evenness of the height of the limiting structure and the bonded substrate layer；
Step 3: forming the first bonded layer on the surface of first Silicon Wafer and carrying out photoetching and quarter to first bonded layer
Etching technique, first bonded layer includes germanium layer, and first bonded layer after etching is formed in the top of the bonded substrate layer
Portion surface and side and the surface for extending to first Silicon Wafer outside the bonded substrate layer, first bonded layer pass through
Extend to the silicon contact of the part outside the bonded substrate layer and first Silicon Wafer；
Step 4: including using the main part that lithographic definition adds the method for etching to form MEMS device in first Silicon Wafer
Fixed electrode and movable electrode, between fixed electrode and movable electrode between be separated with to perform etching first Silicon Wafer to be formed
Groove；
Step 5: providing the second Silicon Wafer, CMOS integrated circuit, the integrated electricity of the CMOS are formed on second Silicon Wafer
It is formed with multilayer interlayer film at the top of road, there is metal layer between each layer interlayer film；The top of second silicon wafer surface
Layer metal layer is the second bonded layer；
The strong conjunction knot of eutectic is formed Step 6: first bonded layer and second bonded layer are contacted and carry out eutectic bonding
Structure；First bonded layer and second bonded layer thickness during eutectic bonding can be reduced, and the limiting structure is used for
Limit the minimum thickness of the eutectic bonding structure.
9. the manufacturing method of MEMS device as claimed in claim 8, it is characterised in that: step 2 is forming the bonded substrate
After layer, further include the steps that forming side wall in the side of the bonded substrate layer, to promote the side of the bonded substrate layer
Plane inclination.
10. the manufacturing method of MEMS device as claimed in claim 9, it is characterised in that: in the side of the bonded substrate layer
Side wall is also formed in the side of the limiting structure while forming side wall.
11. the manufacturing method of the MEMS device as described in claim 9 or 10, it is characterised in that: the material of the first medium layer
Material is oxide layer, and the material of the side wall is oxide layer.
12. the manufacturing method of MEMS device as claimed in claim 8, it is characterised in that: the height of the limiting structure is 2 micro-
Rice~3 microns.
13. the manufacturing method of MEMS device as claimed in claim 8, it is characterised in that: in step 3, first bonded layer
Further include Ti and TiN layer, be initially formed the Ti and TiN layer, forms the germanium layer on the surface of the Ti and TiN layer again later；
Later, carry out rapid thermal treatment is further comprised the steps of:, the Ti and TiN layer and the silicon of first Silicon Wafer are being contacted
Place forms Titanium silicide.
14. the manufacturing method of MEMS device as claimed in claim 8, it is characterised in that: the material of the top layer metallic layer is
Aluminium.
15. the manufacturing method of MEMS device as claimed in claim 14, it is characterised in that: the eutectic bonding of step 6
Process conditions include: that temperature is 400 DEG C, and pressure is 20kN~40kN.
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| CN111762754A (en) * | 2020-06-30 | 2020-10-13 | 上海华虹宏力半导体制造有限公司 | Test structure for measuring eutectic bonding alignment deviation |
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