CN109795980A - The manufacturing method of MEMS device - Google Patents
The manufacturing method of MEMS device Download PDFInfo
- Publication number
- CN109795980A CN109795980A CN201910014732.9A CN201910014732A CN109795980A CN 109795980 A CN109795980 A CN 109795980A CN 201910014732 A CN201910014732 A CN 201910014732A CN 109795980 A CN109795980 A CN 109795980A
- Authority
- CN
- China
- Prior art keywords
- layer
- bonded
- silicon wafer
- mems device
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 69
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 67
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000001259 photo etching Methods 0.000 claims abstract description 23
- 230000005496 eutectics Effects 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims description 138
- 229910052732 germanium Inorganic materials 0.000 claims description 20
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 23
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000009194 climbing Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 238000006664 bond formation reaction Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Micromachines (AREA)
Abstract
The invention discloses a kind of manufacturing methods of MEMS device, comprising steps of Step 1: providing the first Silicon Wafer and forming limiting structure and bonded substrate layer；Step 2: forming dielectric layer side wall in the side of limiting structure and bonded substrate layer；Step 3: forming the first bonded layer；Step 4: carrying out being lithographically formed the first photoetching offset plate figure, carrying out silicon etching in formation groove and the main part of MEMS device, the structure that dielectric layer side wall makes the first photoetching offset plate figure have middle section thinner than fringe region being consequently formed；Step 5: providing the second Silicon Wafer for being formed with CMOS integrated circuit, the top layer metallic layer of the second silicon wafer surface is the second bonded layer；The strong conjunction structure of eutectic is formed Step 6: the first and second bonded layers are contacted and carry out eutectic bonding.The present invention can make photoresist in the etching of the groove of MEMS device while meet the requirement of requirement and the protection to the fringe region of Silicon Wafer of the smaller width of groove.
Description
Technical field
The present invention relates to a kind of manufacturing methods of semiconductor integrated circuit, more particularly to a kind of manufacturer of MEMS device
Method.
Background technique
It is the device architecture schematic diagram in each step of manufacturing method of existing MEMS device as shown in Figure 1A to Fig. 1 E, it is existing
There is method to include the following steps:
As shown in Figure 1A, Silicon Wafer 101 is provided.
As shown in Figure 1B, the etching for carrying out silicon forms limiting structure (stopper) 102 on the surface of Silicon Wafer 101, simultaneously
Bonded substrate layer 103 is formed, the position of the two is defined using photoetching process.In Figure 1B, limiting structure 102 is arranged in Silicon Wafer
At 101 both sides of the edge.
As shown in Figure 1 C, germanium side wall 104 is formed in the side of limiting structure 102 and bonded substrate layer 103.The germanium side wall
104 are formed in the side of limiting structure 102 and bonded substrate layer 103 by depositing germanium layer and carrying out comprehensive etching autoregistration of germanium
Face.
As shown in Figure 1 C, the first bonded layer 105 is formed on the surface of bonded substrate layer 103.In existing method, the first bonding
Layer 105 generallys use germanium layer, by first depositing germanium layer, carries out photoetching again later and selectes forming region, then perform etching and to be formed only
Structure positioned at 103 surface of bonded substrate layer.
As shown in figure iD, the main part 107 of MEMS device, the main body of the MEMS device are formed in Silicon Wafer 101
Part 107 includes fixed electrode and movable electrode, is separated with groove 106 between fixing between electrode and movable electrode.Main part 107
It mainly forms what groove 106 was formed by carrying out silicon etching, i.e., first uses the selected region for needing to form groove 106 of photoetching,
It performs etching to form groove 106 again later, groove 106 needs to cut through Silicon Wafer 101.
As referring to figure 1E, the Silicon Wafer 108 for being formed with CMOS integrated circuit 109, the top of CMOS integrated circuit 109 are provided
It is formed with interlayer film, there is metal layer between each layer interlayer film, wherein top layer metallic layer (TM) is used as the second bonded layer, top-gold
The material for belonging to layer is usually aluminium.
Situation when Fig. 1 E show the first bonded layer 105 and the second bonded layer has just been directed at contact, it is subsequent to need to carry out germanium
Eutectic bonding between aluminium forms eutectic bonding structure, carries out eutectic bonding between the first bonded layer 105 and the second bonded layer
Afterwards, Silicon Wafer 101 and the second Silicon Wafer 108 can be bonded together, and realize electrical connection.In eutectic bonding, the first bonded layer
105 and second the superposition thickness of bonded layer can gradually decrease, wherein limiting structure 102 is exactly to limit the first bonded layer 105
Minimum thickness after being bonded with the second bonded layer, if also just the superposition thickness of the first bonded layer 105 and the second bonded layer is too small
When, the surface of limiting structure 102 will withstand the surface of Silicon Wafer 108, to prevent the first bonded layer 105 and the second bonded layer
Superposition thickness continue to reduce.
In Fig. 1 E, the bottom panel (Bottom positioned at 107 bottom of main part is also formed on the surface of Silicon Wafer 108
Plate) structure 110 further include liner (Pad) structure 111 for the exit of the extraction of CMOS integrated circuit 109.
In existing method, in the step shown in Figure 1B, the height of limiting structure 102 is usually 2 microns~3 microns, is made
The etch amount that must carry out silicon etching is 2 microns~3 microns.
In existing method, it is unfavorable to generate in the step of germanium side wall 104 can form groove 106 shown in Fig. 1 D
It influences.Reason is, in the forming region of lithographic definition groove 106, photoresist can be across the institute at the edge positioned at Silicon Wafer 101
The germanium side wall 104 of limiting structure 102 and its side is stated, photoresist is easy during climbing jump germanium side wall 104 in the limitation
The lateral position of structure 102 forms relatively thin photoresist.If the thickness mistake of the photoresist of the lateral position of the limiting structure 102
It is thin, then it is easy to generate germanium damage in subsequent deeper silicon etching, it also can be due to the protective capability of photoresist with regard to germanium side wall 104
Not strong and be etched, germanium etching can bring the polymer of weight, and the polymer of weight will affect etching cavity, that is, etching cavity
Generate pollution and and then meeting polluted product.So germanium damages in order to prevent, need to increase the thickness of photoresist.
But the thickness of photoresist needs to meet the needs of the line width of groove 106 again simultaneously, usually according to groove 106
Minimum feature size (CD) thickness of photoresist is set, CD is smaller, and the thickness of photoresist is thinner.So in existing method,
Requirement of the CD of requirement and lesser groove 106 of the germanium side wall 104 to thicker photoresist to relatively thin photoresist is exactly the opposite,
So that product requirement often cannot achieve.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of MEMS device, can be in the ditch of MEMS device
Make photoresist in the etching of slot while meeting the requirement of the smaller width of groove and meeting the guarantor to the fringe region of Silicon Wafer
The requirement of shield can enhance product performance and avoid generating pollution to etching cavity simultaneously.
In order to solve the above technical problems, the manufacturing method of MEMS device provided by the invention includes the following steps:
Step 1: providing the first Silicon Wafer, lithographic definition goes out the forming region of limiting structure and bonded substrate layer, it is laggard
Row silicon etching forms the limiting structure and the bonded substrate layer.
Step 2: deposit first medium layer and etch in the side of the limiting structure to the first medium layer comprehensively
Face and the side of the bonded substrate layer form dielectric layer side wall.
Step 3: the top surface in the bonded substrate layer forms the first bonded layer.
Step 4: carrying out being lithographically formed the first photoetching offset plate figure, silicon quarter is carried out by mask of first photoetching offset plate figure
The main part for forming groove in first Silicon Wafer and MEMS device being consequently formed is lost, the main part includes fixing
Electrode and movable electrode, there is the groove at interval between the fixed electrode and the movable electrode.
The main part is located at the middle section of first Silicon Wafer, and the limiting structure is located at the bonded substrate
The outside of layer and the main part and the fringe region for being located at first Silicon Wafer.
It is located at described the by what the dielectric layer side wall of the side of the limiting structure increased by first photoetching offset plate figure
Knot of the thickness of the fringe region of one Silicon Wafer to make first photoetching offset plate figure have middle section thinner than fringe region
The dielectric layer side wall of structure, the limiting structure meets in conjunction with the thickness of the fringe region of first photoetching offset plate figure in the silicon
To the protection of the fringe region of first Silicon Wafer in etching, the thickness of the middle section of first photoetching offset plate figure meets
The requirement of the minimum widith of the groove.
Step 5: providing the second Silicon Wafer, CMOS integrated circuit, the CMOS collection are formed on second Silicon Wafer
At multilayer interlayer film is formed at the top of circuit, there is metal layer between each layer interlayer film；Second silicon wafer surface
Top layer metallic layer be the second bonded layer.
The strong conjunction of eutectic is formed Step 6: first bonded layer and second bonded layer are contacted and carry out eutectic bonding
Structure；First bonded layer and second bonded layer thickness during eutectic bonding can be reduced, and the limiting structure is used
In the minimum thickness for limiting the eutectic bonding structure.
A further improvement is that the material of the first medium layer is oxide layer.
A further improvement is that the thickness of the dielectric layer side wall and side inclination angle are adjustable, adjusting method are as follows: will be required
It wants the first medium layer of thickness to be split as multiple first medium sublayers, is sequentially depositing each first medium sublayer, and
Each first medium sublayer deposition carries out primary etching comprehensively after completing and forms the corresponding sub- side of the first medium sublayer
Wall is superimposed by each sub- side wall and forms the dielectric layer side wall.
A further improvement is that the height of the limiting structure is 2 microns~3 microns.
A further improvement is that the material of the top layer metallic layer is aluminium.
A further improvement is that it is 400 DEG C that the process conditions of the eutectic bonding of step 6, which include: temperature, pressure is
20kN~40kN.
A further improvement is that being also formed with the bottom faces positioned at main part bottom on the surface of second Silicon Wafer
Hardened structure further includes the exit gasket construction for the extraction of CMOS integrated circuit.
A further improvement is that including step by step in step 3:
The first bonded layer is formed on the surface of first Silicon Wafer.
Lithography and etching is carried out to first bonded layer, first bonded layer after etching is formed in the bonding lining
The top surface of bottom.
A further improvement is that first bonded layer includes germanium layer.
The present invention etches after being formed in limiting structure and bonded substrate layer, and is formed before the first bonded layer, this hair
The bright formation process that dielectric layer side wall has been carried out in the side of limiting structure and the side of bonded substrate layer, passes through dielectric layer side wall
The germanium side wall in existing method is replaced, the present invention can improve in the etching of the groove of the main part of subsequent MEMS device
The thickness of the photoresist of the fringe region of first Silicon Wafer, and photoresist generates during the climbing of limiting structure getting over
Relatively thin photoresist can't bring adverse effect to the etching of groove, because the medium of dielectric layer side wall can also be used as silicon etching
Mask；In this way, the thickness of the corresponding photoresist of etching groove of the present invention be entirely capable of it is wide according to the minimum of the groove of middle section
The requirement of the i.e. minimum CD of degree is configured, so that it is able to satisfy the requirement of product, so, the present invention can be in the groove of MEMS device
Make photoresist in etching while meeting the requirement of the smaller width of groove and meeting the protection to the fringe region of Silicon Wafer
It is required that can enhance product performance and avoid generating pollution to etching cavity simultaneously.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Fig. 1 E is the device architecture schematic diagram in each step of manufacturing method of existing MEMS device；
Fig. 2 is the flow chart of the manufacturing method of MEMS device of the embodiment of the present invention；
Fig. 3 A- Fig. 3 F is the device architecture schematic diagram in each step of manufacturing method of MEMS device of the embodiment of the present invention.
Specific embodiment
As shown in Fig. 2, be the flow chart of the manufacturing method of MEMS device of the embodiment of the present invention, as shown in Fig. 3 A to Fig. 3 F,
It is the device architecture schematic diagram in each step of manufacturing method of MEMS device of the embodiment of the present invention, MEMS device of the embodiment of the present invention
Manufacturing method include the following steps:
Step 1: as shown in Figure 3A, providing the first Silicon Wafer 1.
As shown in Figure 3B, lithographic definition goes out the forming region of limiting structure 2 and bonded substrate layer 3, carries out silicon etching later
Form the limiting structure 2 and the bonded substrate layer 3.
In the embodiment of the present invention, the height of the limiting structure 2 is 2 microns~3 microns.
Step 2: as shown in Figure 3 C, deposit first medium layer and etch described to the first medium layer comprehensively
The side of limiting structure 2 and the side of the bonded substrate layer 3 form dielectric layer side wall 4.
In the embodiment of the present invention, the material of the first medium layer is oxide layer.
The thickness of the dielectric layer side wall 4 and side inclination angle are adjustable, adjusting method are as follows: by described the of required thickness
One dielectric layer is split as multiple first medium sublayers, is sequentially depositing each first medium sublayer, and in each first medium
Sublayer deposition carries out primary etching comprehensively and forms the corresponding sub- side wall of the first medium sublayer after completing, by each sub- side
Wall is superimposed to form the dielectric layer side wall 4.Namely: it is deposition -> etching -> deposit-using multiple deposit in the embodiment of the present invention
> etch to adjust the thickness and angle of side wall.
Step 3: as shown in Figure 3D, forming the first bonded layer 5 in the top surface of the bonded substrate layer 3.
Include step by step in step 3:
The first bonded layer 5 is formed on the surface of first Silicon Wafer 1.First bonded layer 5 includes germanium layer.
Lithography and etching is carried out to first bonded layer 5, first bonded layer 5 after etching is formed in the bonding
The top surface of substrate layer 3.
It is to cover with first photoetching offset plate figure Step 4: as shown in FIGURE 3 E, carrying out being lithographically formed the first photoetching offset plate figure
Mould carries out silicon etching and forms groove 6 in first Silicon Wafer 1 and the main part 7 of MEMS device, the master is consequently formed
Body portion 7 includes fixed electrode and movable electrode, and there is the groove 6 at interval between the fixed electrode and the movable electrode.
The main part 7 is located at the middle section of first Silicon Wafer 1, and the limiting structure 2 is located at the bonding
The outside of substrate layer 3 and the main part 7 and the fringe region for being located at first Silicon Wafer 1.
It is described to increase being located at for first photoetching offset plate figure by the dielectric layer side wall 4 of the side of the limiting structure 2
The thickness of the fringe region of first Silicon Wafer 1 is to make first photoetching offset plate figure have middle section thinner than fringe region
The dielectric layer side wall 4 of structure, the limiting structure 2 meets in conjunction with the thickness of the fringe region of first photoetching offset plate figure in institute
State the protection of the fringe region in silicon etching to first Silicon Wafer 1, the thickness of the middle section of first photoetching offset plate figure
Degree meets the requirement of the minimum widith of the groove 6.
Step 5: as illustrated in Figure 3 F, providing the second Silicon Wafer 8, the integrated electricity of CMOS is formed on second Silicon Wafer 8
Road 9, the top of the CMOS integrated circuit 9 are formed with multilayer interlayer film, have metal layer between each layer interlayer film；It is described
The top layer metallic layer on 8 surface of the second Silicon Wafer is the second bonded layer.
The material of the top layer metallic layer is aluminium.
It is also formed with the bottom panel structure 10 positioned at 7 bottom of main part on the surface of second Silicon Wafer 8, is also wrapped
Include the exit gasket construction 11 for the extraction of CMOS integrated circuit 9.
It is good for Step 6: first bonded layer 5 and second bonded layer are contacted and carry out eutectic bonding formation eutectic
Close structure；First bonded layer 5 and second bonded layer thickness during eutectic bonding can be reduced, the limiting structure
2 for limiting the minimum thickness of the eutectic bonding structure.
The process conditions of the eutectic bonding include: that temperature is 400 DEG C, and pressure is 20kN~40kN.
The embodiment of the present invention is after limiting structure 2 and the etching of bonded substrate layer 3 are formed, and forms the first bonded layer 5
Before, the embodiment of the present invention has carried out the formation of dielectric layer side wall 4 in the side of limiting structure 2 and the side of bonded substrate layer 3
Technique replaces the germanium side wall in existing method by dielectric layer side wall 4, and the embodiment of the present invention can be in the master of subsequent MEMS device
In the etching of the groove 6 of body portion 7, the thickness of the photoresist of the fringe region of the first Silicon Wafer 1 is improved, and photoresist is being got over
The relatively thin photoresist generated during the climbing of limiting structure 2 can't bring adverse effect to the etching of groove 6, because
The medium of dielectric layer side wall 4 also can be as the mask of silicon etching；In this way, groove of the embodiment of the present invention 6 etches corresponding photoresist
Thickness be entirely capable of being configured according to the requirement of the i.e. minimum CD of minimum widith of the groove 6 of middle section, to be able to satisfy production
The requirement of product, so, the embodiment of the present invention can make photoresist in the etching of the groove 6 of MEMS device while meet groove 6
The requirement of smaller width and the requirement for meeting the protection to the fringe region of Silicon Wafer, can enhance product performance and avoid simultaneously
Pollution is generated to etching cavity.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (9)
1. a kind of manufacturing method of MEMS device, which comprises the steps of:
Step 1: providing the first Silicon Wafer, lithographic definition goes out the forming region of limiting structure and bonded substrate layer, carries out silicon later
Etching forms the limiting structure and the bonded substrate layer；
Step 2: deposition first medium layer and to the first medium layer carry out comprehensively etching the limiting structure side and
The side of the bonded substrate layer forms dielectric layer side wall；
Step 3: the top surface in the bonded substrate layer forms the first bonded layer；
Step 4: carrying out being lithographically formed the first photoetching offset plate figure, silicon etching is carried out as mask using first photoetching offset plate figure and is existed
Groove is formed in first Silicon Wafer and the main part of MEMS device is consequently formed, and the main part includes fixed electrode
And movable electrode, there is the groove at interval between the fixed electrode and the movable electrode；
The main part is located at the middle section of first Silicon Wafer, the limiting structure be located at the bonded substrate layer and
The outside of the main part and the fringe region for being located at first Silicon Wafer；
By the dielectric layer side wall of the side of the limiting structure increase by first photoetching offset plate figure be located at first silicon
Structure of the thickness of the fringe region of wafer to make first photoetching offset plate figure have middle section thinner than fringe region, institute
The dielectric layer side wall for stating limiting structure meets in conjunction with the thickness of the fringe region of first photoetching offset plate figure in the silicon etching
In protection to the fringe region of first Silicon Wafer, described in the thickness of the middle section of first photoetching offset plate figure meets
The requirement of the minimum widith of groove；
Step 5: providing the second Silicon Wafer, CMOS integrated circuit, the integrated electricity of the CMOS are formed on second Silicon Wafer
It is formed with multilayer interlayer film at the top of road, there is metal layer between each layer interlayer film；The top of second silicon wafer surface
Layer metal layer is the second bonded layer；
The strong conjunction knot of eutectic is formed Step 6: first bonded layer and second bonded layer are contacted and carry out eutectic bonding
Structure；First bonded layer and second bonded layer thickness during eutectic bonding can be reduced, and the limiting structure is used for
Limit the minimum thickness of the eutectic bonding structure.
2. the manufacturing method of MEMS device as described in claim 1, it is characterised in that: the material of the first medium layer is oxygen
Change layer.
3. the manufacturing method of MEMS device as claimed in claim 1 or 2, it is characterised in that: the thickness of the dielectric layer side wall
It is adjustable with side inclination angle, adjusting method are as follows: the first medium layer of required thickness is split as multiple first medium
Layer is sequentially depositing each first medium sublayer, and progress is primary comprehensive after each first medium sublayer deposition is completed
Etching forms the corresponding sub- side wall of the first medium sublayer, is superimposed by each sub- side wall and forms the dielectric layer side wall.
4. the manufacturing method of MEMS device as described in claim 1, it is characterised in that: the height of the limiting structure is 2 micro-
Rice~3 microns.
5. the manufacturing method of MEMS device as described in claim 1, it is characterised in that: the material of the top layer metallic layer is
Aluminium.
6. the manufacturing method of MEMS device as claimed in claim 5, it is characterised in that: the work of the eutectic bonding of step 6
Skill condition includes: that temperature is 400 DEG C, and pressure is 20kN~40kN.
7. the manufacturing method of MEMS device as described in claim 1, it is characterised in that: the surface of second Silicon Wafer also
It is formed with the bottom panel structure positioned at main part bottom, further includes the exit liner for the extraction of CMOS integrated circuit
Structure.
8. the manufacturing method of MEMS device as described in claim 1, it is characterised in that: include step by step in step 3:
The first bonded layer is formed on the surface of first Silicon Wafer；
Lithography and etching is carried out to first bonded layer, first bonded layer after etching is formed in the bonded substrate layer
Top surface.
9. the manufacturing method of MEMS device as claimed in claim 8, it is characterised in that: first bonded layer includes germanium layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910014732.9A CN109795980B (en) | 2019-01-08 | 2019-01-08 | Method for manufacturing MEMS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910014732.9A CN109795980B (en) | 2019-01-08 | 2019-01-08 | Method for manufacturing MEMS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109795980A true CN109795980A (en) | 2019-05-24 |
| CN109795980B CN109795980B (en) | 2020-09-29 |
Family
ID=66556851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910014732.9A Active CN109795980B (en) | 2019-01-08 | 2019-01-08 | Method for manufacturing MEMS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109795980B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691313A (en) * | 2001-05-31 | 2005-11-02 | 松下电器产业株式会社 | Power component and manufacturing method thereof |
| CN104377298A (en) * | 2014-12-11 | 2015-02-25 | 北京工业大学 | Flip-chip bonding electrode structure of surface-type semiconductor laser device |
| CN105480936A (en) * | 2014-09-17 | 2016-04-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN105513983A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN105990165A (en) * | 2015-02-02 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| US9673063B2 (en) * | 2015-10-26 | 2017-06-06 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Terminations |
| US20180159503A1 (en) * | 2016-12-02 | 2018-06-07 | Skyworks Solutions, Inc. | Electronic devices formed in a cavity between substrates and including a via |
-
2019
- 2019-01-08 CN CN201910014732.9A patent/CN109795980B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691313A (en) * | 2001-05-31 | 2005-11-02 | 松下电器产业株式会社 | Power component and manufacturing method thereof |
| CN105480936A (en) * | 2014-09-17 | 2016-04-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN105513983A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN104377298A (en) * | 2014-12-11 | 2015-02-25 | 北京工业大学 | Flip-chip bonding electrode structure of surface-type semiconductor laser device |
| CN105990165A (en) * | 2015-02-02 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| US9673063B2 (en) * | 2015-10-26 | 2017-06-06 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Terminations |
| US20180159503A1 (en) * | 2016-12-02 | 2018-06-07 | Skyworks Solutions, Inc. | Electronic devices formed in a cavity between substrates and including a via |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109795980B (en) | 2020-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8455364B2 (en) | Sidewall image transfer using the lithographic stack as the mandrel | |
| CN110636422B (en) | Semiconductor device and method of forming the same | |
| TWI658739B (en) | Piezoelectric microphone with deflection control and method of making the same | |
| KR0178823B1 (en) | Semiconductor device and manufacturing method | |
| CN109151690B (en) | Method for manufacturing microphone | |
| EP3119533A1 (en) | Cmut device and manufacturing method | |
| EP2933829B1 (en) | Method for reducing defects in shallow trench isolation | |
| JPH07321345A (en) | Method of forming micromechanism structure | |
| JP2001338979A (en) | Semiconductor device and its manufacturing method | |
| CN106098544A (en) | The method improving groove type double-layer grid MOS dielectric layer pattern | |
| WO2021035931A1 (en) | Array substrate, manufacturing method for array substrate, and display panel | |
| US20230223349A1 (en) | Method for forming overlay marks and semiconductor structure | |
| US20200348198A1 (en) | Capacitive Pressure Sensors and Other Devices Having a Suspended Membrane and Having Rounded Corners at an Anchor Edge | |
| CN109795980A (en) | The manufacturing method of MEMS device | |
| CN111969111B (en) | Capacitor and manufacturing method thereof | |
| JP2009123818A (en) | Method for manufacturing magnetic sensor device | |
| US20230202835A1 (en) | Actuator layer patterning with topography | |
| US10745270B2 (en) | Actuator layer patterning with topography | |
| CN102198925B (en) | MEMS device and forming method thereof | |
| CN109904063A (en) | MEMS device and its manufacturing method | |
| CN103094188B (en) | A kind of method and fuse window making fuse window on chip | |
| TWI775227B (en) | Capacitive pressure sensor and method of manufacturing the same | |
| KR100774795B1 (en) | Multi-gate insulating film formation method | |
| KR100758641B1 (en) | MEMS device comprising a method for forming a microstructure on a silicon substrate integrated with the CMOS circuit and the microstructure formed by the method | |
| KR100548584B1 (en) | Gate electrode formation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |