CN109884940A - Ageing system - Google Patents
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- CN109884940A CN109884940A CN201910139748.2A CN201910139748A CN109884940A CN 109884940 A CN109884940 A CN 109884940A CN 201910139748 A CN201910139748 A CN 201910139748A CN 109884940 A CN109884940 A CN 109884940A
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- 230000032683 aging Effects 0.000 title claims abstract description 230
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- 238000001514 detection method Methods 0.000 claims abstract description 42
- 230000007246 mechanism Effects 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims description 34
- 238000004891 communication Methods 0.000 claims description 19
- 230000005611 electricity Effects 0.000 claims description 13
- 238000005086 pumping Methods 0.000 claims description 9
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- 238000013461 design Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000007670 refining Methods 0.000 description 5
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000005284 excitation Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
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- 230000010355 oscillation Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
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- 230000033228 biological regulation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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Abstract
The embodiment of the present application discloses a kind of ageing system, which includes: at least one piece of ageing motherboard and at least one piece of ageing daughter board；Ageing motherboard includes motherboard circuit plate, motherboard control device, and motherboard control device is set on motherboard circuit plate；Ageing daughter board includes daughter board circuit board, daughter board control device, daughter board control device is set on daughter board circuit board, daughter board circuit board is electrically connected with motherboard circuit plate, and the first interface circuit for connecting chip to be tested is arranged on daughter board circuit board, provides the second interface circuit of the temperature feeding mechanism of ageing temperature environment to chip to be tested for connecting；Wherein, ageing motherboard sends control information to corresponding ageing daughter board through motherboard control device, ageing daughter board controls corresponding chip to be tested through daughter board control device and temperature feeding mechanism carries out ageing test, and daughter board control device receives the detection information of corresponding ageing daughter board and is sent to motherboard control device.
Description
Technical field
This application involves the tests of chip ageing, and in particular to a kind of ageing system.
Background technique
Chip generally requires before factory and carries out ageing test.Ageing test, which refers to, applies chip under hot conditions
Electric power stress and temperature stress accelerate the reliability test for causing initial failure mechanism to occur.The hair to be failed by accelerating circuit
It is raw make non-defective unit as early as possible into the random failure period in the middle part of its reliability service life i.e. tub curve, avoid sending out using early stage
Raw failure.Ageing test is a kind of nondestructive test, only fall out effect is played to the circuit for having latent defect, without drawing
It plays the new failure mechanism after circuit overall screen is selected or changes its invalid cost.And if tested without ageing, much partly lead
Body finished product will appear many problems in use due to device and manufacturing process defect etc..Therefore, it is necessary to by old
Refining system does high temperature accelerated life test to chip, to filter out reliable and stable chip.
In the related technology, muti-piece chip to be tested is placed on same aging board, and muti-piece aging board is placed on ageing
Unified heating, is connect by the power supply outside high temperature resistant connector, high temperature resistant wire and ageing incubator with functional circuit in incubator.By
It needs to integrate in each aging board and is placed in ageing incubator unified heating, for different chips to be tested, be unable to satisfy independent survey
The demand of examination；In addition, system needs continuous tens even hundreds and thousands of a hour continuous non-stop runs when ageing is tested, when old
When refining that 1 piece or muti-piece aging board break down in incubator, if closing ageing incubator checks failure, other aging boards are influenced in this way
Test leads to the phenomenon that testing repeatedly occur, low so as to cause testing efficiency, difficult in maintenance.
Summary of the invention
In view of this, the embodiment of the present application provides a kind of ageing system, it is intended to realize to the independent old of chip to be tested
Refining test, improves the versatility of test.
The technical solution of the embodiment of the present application is achieved in that
A kind of ageing system, comprising: at least one piece of ageing motherboard and at least one piece of ageing daughter board；The ageing motherboard includes
Motherboard circuit plate, motherboard control device, the motherboard control device are set on the motherboard circuit plate；The ageing daughter board packet
Enclosed tool plate circuit board, daughter board control device, the daughter board control device are set on the daughter board circuit board, the daughter board circuit
Plate is electrically connected with the motherboard circuit plate, and the first interface electricity for connecting chip to be tested is arranged on the daughter board circuit board
Road provides the second interface circuit of the temperature feeding mechanism of ageing temperature environment to the chip to be tested for connecting；Wherein,
The ageing motherboard sends control information to the corresponding ageing daughter board, the ageing daughter board warp through the motherboard control device
The daughter board control device controls the corresponding chip to be tested and the temperature feeding mechanism carries out ageing test, the son
Plate control device receives the detection information of corresponding ageing daughter board and is sent to the motherboard control device.
In technical solution provided by the embodiments of the present application, by the cooperation of ageing motherboard and ageing daughter board, it may be implemented same
The ageing test of one piece or muti-piece ageing daughter board on one ageing motherboard, and on each ageing daughter board chip to be measured model and test
Temperature can be same or different, improves the versatility of test, the test relative to heating unified in existing ageing incubator
Scheme controls each daughter board control device by motherboard control device and carries out ageing test to corresponding each chip to be tested, meets
Synchronizations or asynchronous testing requirement of the different chips to be tested under same or different test temperature, and it is conducive to individually dimension
Shield, reduces maintenance cost.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of ageing system in one embodiment of the application；
Fig. 2 is the structural schematic diagram of motherboard circuit plate in one embodiment of the application；
Fig. 3 is the structural schematic diagram of motherboard control device in one embodiment of the application；
Fig. 4 is the structural schematic diagram of ageing daughter board in one embodiment of the application；
Fig. 5 is the structural schematic diagram of daughter board circuit board in one embodiment of the application；
Fig. 6 is the structural schematic diagram of daughter board control device in one embodiment of the application.
Specific embodiment
Technical scheme is further described in detail with reference to the accompanying drawings and specific embodiments of the specification.It should
Understand, embodiment mentioned herein is only used to explain the application, is not used to limit the application.In addition, provided below
Embodiment be section Example for implementing the application, rather than provide the whole embodiments for implementing the application, do not conflicting
In the case where, the embodiment of the present application record technical solution can mode in any combination implement.
Unless otherwise defined, all technical and scientific terms used herein and the technical field for belonging to the application
The normally understood meaning of technical staff is identical.The term used in the description of the present application is intended merely to description tool herein
The purpose of the embodiment of body, it is not intended that in limitation the application.Term as used herein "and/or" includes one or more phases
Any and all combinations of the listed item of pass.
Referring to Fig. 1, the embodiment of the present application provides a kind of ageing system 100, which includes: at least one piece
Ageing motherboard 4 and at least one piece of ageing daughter board 1.Ageing motherboard 4 includes motherboard circuit plate 41, motherboard control device 5, motherboard control
Device 5 is set on motherboard circuit plate 41.Referring to Fig. 4, ageing daughter board 1 includes daughter board circuit board 11, daughter board control device 2,
Daughter board control device 2 is set to 11 on daughter board circuit board, and daughter board circuit board 11 is electrically connected with motherboard circuit plate 41, daughter board circuit board
First interface circuit (not shown) for connecting chip to be tested is set on 11, provides ageing to chip to be tested for connecting
The second interface circuit (not shown) of the temperature feeding mechanism of temperature environment.Ageing motherboard 4 sends through motherboard control device 5 and controls
Information gives corresponding ageing daughter board 1, and ageing daughter board 1 controls corresponding chip to be tested through daughter board control device 2 and temperature is supplied
Device carries out ageing test, and daughter board control device 2 receives the detection information of corresponding ageing daughter board and by the detection of ageing daughter board
Information is sent to motherboard control device 5.
The present embodiment by the cooperation of ageing motherboard 4 and ageing daughter board 1, may be implemented on same ageing motherboard 4 one piece or
The ageing of person's muti-piece ageing daughter board 1 is tested, and the model of chip to be measured can be same or different on each ageing daughter board 1, ageing
Test temperature can be same or different, improves the versatility and flexibility of test, relative to uniting in existing ageing incubator
The testing scheme of one heating controls each daughter board control device by motherboard control device and carries out always to corresponding each chip to be tested
Refining test meets synchronization or asynchronous testing requirement of the different chips to be tested at same or different temperature, and is conducive to
It separately maintains, reduces maintenance cost.
In some embodiments, the quantity of ageing motherboard 4 is muti-piece, and muti-piece ageing motherboard 4 is set in cabinet, each ageing
Muti-piece ageing daughter board 1 is set on motherboard 4, to realize the integrated test of muti-piece chip to be tested on cabinet, improves test speed
Degree.
Optionally, cabinet includes cabinet, the multilayer guide rail on cabinet and the roller type with each layer guide rail corresponding matching
Drawer fixes an ageing motherboard 4 on each layer roller type drawer, opens up multiple fixations on the motherboard circuit plate 41 of the ageing motherboard 4
Hole 413, for example, the multiple fixation holes 413 being opened in 41 surrounding of motherboard circuit plate, motherboard circuit plate 41 pass through fixation hole 413
It is fixed on each roller type drawer of cabinet, the concentration ageing test of muti-piece ageing motherboard 4 in the chassis may be implemented.And it uses
The structure of roller type drawer, convenient for replacing chip to be tested in the chassis.
Optionally, in some embodiments, setting and the one-to-one Switching Power Supply of each ageing motherboard 4 in cabinet, are respectively opened
Powered-down source individually gives corresponding ageing motherboard 4 to power, and relative to the bulk supply of multiple ageing motherboards 4, improve power supply can
By property, even if some Switching Power Supply is damaged, the normal work of other ageing motherboards 4 is not also influenced.It is set on motherboard circuit plate 41
Power circuit 42 is set, power circuit 42 supplies electricity to motherboard control device 5 and ageing daughter board 1.The power circuit 42 can use 8
M8 copper stud accesses 1 road direct current 12V high power switching power supply, and 4 are connecing power supply just in 8 copper studs, and 4 connect power supply and bear, thus
Respectively ageing daughter board 1 and motherboard control device 5 provide DC12V power supply.
Optionally, in some embodiments, communication interface 43 is also set up on motherboard circuit plate 41, connects motherboard control device
5, for motherboard control device 5 and external control equipment to be communicated to connect.The communication interface 43 can be wired or wireless
Communication interface.Here, motherboard control device 5 is that communication interface 43 provides DC3V3 power supply, and motherboard control device 5 passes through connection
RX/TX and communication interface 43 communicate to connect, and can receive external control information, for example, receive what ageing control equipment issued
Information is controlled, which includes: the heating device of start and stop ageing seat, the radiator of start and stop ageing seat, the single core of setting
One of piece shell temperature offset (base temperature), setting information such as whole cabinet chip shell temperature offset (offset temperature) or
Person is a variety of.The detection information that each ageing daughter board 1 uploads can also be uploaded to ageing control through communication interface 43 by motherboard control device 5
Control equipment, ageing control equipment can obtain the corresponding detection information of each ageing daughter board.Motherboard control device 5 can pass through 32 pairs
High-speed differential signal (CLK P/N<0:7>, CS P/N<0:7>, DI P/N<0:7>, DO P/N<0:7>) acquires each ageing daughter board 1
Corresponding detection information, which includes: daughter board number, daughter board whether there is, whether chip shell temperature, chip work just
Often, one or more of information such as chip operating voltage, ageing seat ambient temperature.Optionally, communication interface 43 is set
Manual reset switch RST is set, when communication interface 43, which works, occurs abnormal, reset can be restarted by manual reset switch.
In one example, 8 pieces of ageing motherboards 4 can be put in a cabinet, and 8 pieces of ageing daughter boards can be placed on each ageing motherboard 4
1, so as to 64 chips to be tested of ageing simultaneously.Cabinet introduces 220V alternating current through outside, is respectively 8 big to cabinet inside
Power 12V Switching Power Supply power supply, thus through each Switching Power Supply to each individually power supply of ageing motherboard 4.8 pieces of ageing motherboards 4 are used respectively
Cable is connect with the interchanger in cabinet, unified to go out 1 cable and cabinet rear end network interface connection by interchanger, by cabinet back-end network
Mouth is communicated with the ageing control equipment being located at outside cabinet.It in another embodiment, can will be all old if ageing cabinet is more
Mill box back network interface is connected to an external switch, then is communicated by the external switch with ageing control equipment.Every piece of ageing mother
The communication interface 43 of plate 4 by regulation sets IP address, and (when muti-piece ageing motherboard is put into cabinet, it is female that user can pass through ageing
The IP address of the communication interface 43 of plate 4 indexes unique corresponding ageing motherboard, checks the chip ageing number of corresponding ageing motherboard
According to), and IP address is written in database, it searches and modifies convenient for user.
Referring to Fig. 2, motherboard circuit plate 41 is equipped with for installing the first installing zone 411 of motherboard control device 5, being used for
Second installing zone 412 of ageing daughter board is installed.As shown in Fig. 2, in one embodiment, motherboard circuit plate 41 is equipped with eight second
Installing zone 412 and first installing zone 411, eight pieces of ageing daughter boards 1 are corresponding to be installed on each second installing zone 412, motherboard control
Device 5 is installed on the first installing zone 411, and each second installing zone 412 is electrically connected (for example, Ke Yijing with the first installing zone 411
The copper wire electrical connection being laid in motherboard circuit plate 41), to realize control of the motherboard control device 5 to eight pieces of ageing daughter boards 1
System.
Referring to Fig. 3, motherboard control device 5 includes: first control circuit plate 51 and the first controller.First control circuit
Plate 51 is installed on motherboard circuit plate 41 and is electrically connected with motherboard circuit plate 41.First controller is set to first control circuit plate
On 51, to ageing daughter board 1 and the corresponding detection information of ageing daughter board 1 is received for sending control information.
Motherboard control device 5 controls one piece be set on motherboard circuit plate 41 or muti-piece ageing daughter board 1, and
There is motherboard control device 5 individual first control circuit plate 51 to subtract to simplify the wires design on motherboard circuit plate 41
Lack the interference that cabling transmits signal, and it is different can to meet each ageing daughter board 1 by the independent control to ageing daughter board 1
The testing requirement of ageing test.
In some embodiments, the first controller being set on first control circuit plate 51 includes that primary scene is programmable
Gate array FPGA 52, first microprocessor MCU 53.First FPGA 52 is communicated to connect with motherboard circuit plate 41；First MCU 53
It is communicated to connect with the first FPGA 52 and motherboard circuit plate 41.First MCU 53 is for sending control information to the first FPGA
52, the first FPGA 52 are used to receive the corresponding detection information of ageing daughter board 1 and be sent to the first MCU 53, and according to the first MCU
The 53 corresponding ageing daughter boards of control information control sent carry out ageing test.
By using the operating mode that the first MCU 52 and the first FPGA 53 cooperate, the first MCU 52 may be implemented to the
One FPGA 53 carries out data configuration and not only simplifies circuit to save the configuration memory circuit of the first FPGA 53, also saves
Hardware cost.
Referring to Fig. 3, the first connector 54 is set, and first control circuit plate 51 is through the first connection on first control circuit plate 51
Device 54 with motherboard circuit plate 41 is detachable is electrically connected.In this way, motherboard control device 5 can be separated with motherboard circuit plate 41, it is female
Plate control device 5 and motherboard circuit plate 41 can reuse, so that it is fault-tolerant to increase design.When motherboard circuit plate 41 or
When motherboard control device 5 breaks down, it is only necessary to the part of failure is replaced, it is convenient for safeguarding.First connector 54
It can be winding displacement or golden finger connector, motherboard circuit plate 41 is correspondingly provided with slot in the first installing zone 411, to realize motherboard
Being electrically connected between control device 5 and motherboard circuit plate 41.
Optionally, power supply circuit 55 is also set up on first control circuit plate 51, power supply circuit 55 receives motherboard circuit plate 41
The DC power supply of offer and it is converted after supply electricity to the first controller.In one embodiment, power supply circuit 55 is by motherboard circuit plate
The 41 DC12V power supplys provided through the first connector 54 are converted to DC3V3, DC1V2 operating voltage, and power supply circuit 55 is the first FPGA
52 provide DC3V3, DC1V2 operating voltage, provide DC3V3 operating voltage for the first MCU 53.
In some embodiments, the first FPGA 52 is through JTAG (Joint Test Action Group, joint test behavior
Tissue) interface downloading exploitation debugging FPGA program.First FPGA 52 can generate clock signal clk by the first MCU 53,
Clock signal can be generated by the reserved crystal oscillator in outside, in this way, can use when the first MCU 53 output clock signal is abnormal
The clock signal that the reserved crystal oscillator in outside generates, to improve system stability.First FPGA 52 can be generated by the first MCU 53
Reset signal RST can also carry out external hand reset through external RST, to improve system stability.First FPGA 52 connects
Connect configuration circuit, for according to FPGA user's manual by FPGA work normally institute must pin draw high or drag down processing.First
FPGA 52 can connect Flash flash memory, after normally being powered on for the first FPGA 52,53 tranmitting data register signal of the first MCU
(CLK) the first FPGA 52, the first FPGA 52 is given to read FPGA from Flash by spi bus interface with reset signal (RST)
Configuration file is loaded into the first FPGA 52.First FPGA 52 can receive control of the first MCU 53 to FPGA configuration pin
System reduces the plate face of control circuit board, and the flexible configuration of FPGA pin may be implemented to simplify hardware circuit design.The
One MCU 53 configures daughter board selection signal OPNO<0:3>, ageing daughter board 1 is numbered by 4 bits, so that motherboard
Eight corresponding ageing daughter boards 1 of the second installing zone 412 have unique corresponding coding on circuit board 41, realize to single ageing
The independent control of plate 1.Optionally, the first FPGA 52 has reserved the reserved I/O pin communicated with the first MCU 53, in order into
Row functions expanding.
First FPGA 52 by 32 pairs of high-speed differential signals (CLK P/N<0:7>, CS P/N<0:7>, DI P/N<0:7>,
DO P/N<0:7>) it is communicated with 8 pieces of ageing daughter boards 1, the corresponding detection information of each ageing daughter board 1 is acquired, which includes:
Daughter board number, daughter board whether there is, whether chip shell temperature, chip are working properly, chip operating voltage, ageing seat ambient enviroment temperature
One or more of information such as degree.First FPGA 52 is communicated by 32 pairs of high-speed differential signals with 8 pieces of ageing daughter boards 1, root
The control information control ageing daughter board sent according to the first MCU 53 carries out ageing test.The control information includes: start and stop ageing seat
Heating device, start and stop ageing seat radiator, setting one single chip shell temperature offset (base temperature), setting whole cabinet
One or more of information such as chip shell temperature offset (offset temperature).
First FPGA 52 is communicated by spi bus interface with the first MCU 53, and 8 pieces of ageing daughter boards 1 of acquisition are corresponding
Detection information passes to the first MCU 53, and receives the control information that the first MCU 53 is sent.
In some embodiments, optionally, motherboard control device 5 further include: the first indicator light 521, the first indicator light 521
The first FPGA 52 is connected, the working condition of the first FPGA 52 is used to indicate.Specifically, 52 program of the first FPGA load is completed,
DONE pin exports high level, and it is bright that program loads indicator light.Indicator light is loaded by the program, the first FPGA can be observed in real time
Whether 52 program loads completion, consequently facilitating quickly checking failure.
In some embodiments, power supply circuit 55 is that the first MCU 53 provides DC3V3 working power, and the first MCU 53 is by interior
Portion's crystal oscillator generates clock, is reserved with external crystal-controlled oscillation.First MCU 53 supports external hand to reset and house dog software reset.First
MCU 53 updates MCU program by serial ports (UART) downloading, to meet the demand for control of different ageing tests.Optionally, first
MCU 53 can control 52 configuration pin of FPGA.First MCU 53 is equipped with download configuration port, by jump cap that bouncing pilotage on plate is short
It connects, boot0 and 3V3 are connected, and program downloading is completed, and jump cap are pulled up, to realize that program is downloaded.
First MCU 53 is communicated to connect by connection RX/TX and motherboard circuit plate 41, and the first MCU 53 can receive always
Control information is simultaneously handed down to the first FPGA 52 by the control information of refining control equipment transmission, can also send the first FPGA 52
The corresponding detection information of ageing daughter board 1 through motherboard circuit plate 41 be sent to ageing control equipment.In one example, motherboard circuit
Communication interface 43 is set on plate 41, and the first connection of MCU 53 communication interface 43 can receive ageing and control the control that equipment issues
The corresponding detection information of each ageing daughter board is simultaneously sent to ageing control equipment by information processed, to realize ageing control equipment pair
The centralized control of each ageing daughter board, and ageing control equipment can obtain the corresponding detection information of each ageing daughter board.
In some embodiments, motherboard control device 5 further include: the second indicator light 531, the second indicator light 531 connection the
One MCU 53, is used to indicate the working condition of the first MCU 53.For example, the LED_WORK working properly of the first MCU 53 exports low electricity
Flat, indicator light is bright, can observe the working condition of the first MCU 53, in real time convenient for the quick investigation of failure.
In some embodiments, motherboard control device 5 further include: display device 56, first control of the connection of display device 56
Device, for showing the corresponding detection information of ageing daughter board 1.In one example, display device 56 is light-emitting diode display, power supply circuit
55 provide DC3V3 working power to light-emitting diode display, which receives ageing that the first MCU 53 is obtained through spi bus
The corresponding detection information of plate can be set time interval switching 8 pieces of ageing daughter board informations of display.For example light-emitting diode display is shown
Content are as follows: whether the 1st row daughter board number, the 2nd row daughter board work normally；3rd row daughter board temperature.In other embodiments, display dress
Setting 56 can also be charactron.
In some embodiments, multiple fixation holes 511 are offered on first control circuit plate 51 be for example opened in first
Multiple fixation holes 511 in 51 surrounding of control circuit board, first control circuit plate 51 are fixed on motherboard circuit by fixation hole 511
On first installing zone 411 of plate 41.
Referring to Fig. 4, ageing daughter board 1 includes: daughter board circuit board 11, first interface circuit is set on daughter board circuit board 11
(not shown), second interface circuit (not shown), first interface circuit connection chip to be tested, second interface circuit connection temperature
Daughter board control device 2 is arranged on daughter board circuit board 11 for feeding mechanism.In one embodiment, chip to be tested is installed through ageing seat 3
In on daughter board circuit board 11.Bullet for accommodating the receiving area of chip to be tested and positioned at ageing seat bottom is set in ageing seat 3
Spring needle stand, chip to be tested abut the spring needle stand in ageing seat, and the spring needle of the spring needle stand draws with chip to be tested
Foot is corresponding, which includes the one-to-one contact of each spring needle with spring needle stand.Chip installation to be tested is just
Behind position, each pin of chip to be tested is through the first interface circuit connection on spring needle stand and daughter board circuit board 11.On ageing seat 3
It also sets up for providing the temperature feeding mechanism of ageing temperature environment to chip to be tested, the temperature feeding mechanism is through second interface
Circuit connection daughter board circuit board 11.
In one embodiment, temperature feeding mechanism includes heating device corresponding with chip to be tested, heating device warp
Second interface circuit connection daughter board circuit board 11.Optionally, temperature feeding mechanism further includes heat dissipation corresponding with chip to be tested
Device, the radiator, to cooperate with heating device, are realized to be tested through second interface circuit connection daughter board circuit board 11
The ageing temperature of chip accurately controls.
Referring to Fig. 5, daughter board circuit board 11 is equipped with for installing the third installing zone 111 of daughter board control device 2, being used for
The 4th installing zone 112, the second connector 12 for being electrically connected with motherboard circuit plate 41 of ageing seat are installed.Motherboard circuit plate 41
On one piece or muti-piece daughter board circuit board 11 can be set.The present embodiment ageing daughter board 1, independently by daughter board control device 2
Ageing test is carried out to the chip to be tested on daughter board circuit board 11, simplifies the wires design on daughter board circuit board 11, is reduced
The interference that cabling transmits signal.Chip to be tested is installed on the 4th installing zone 112, and the 4th installing zone 112 through ageing seat
It is correspondingly arranged first interface circuit, second interface circuit, so that the chip to be tested and temperature feeding mechanism on ageing seat are electrically connected
Connect daughter board circuit board.Daughter board control device 2 has scalability, versatility, recuperability.Optionally, daughter board control device 2 is reserved
A large amount of pins, user can program customized according to actual needs.Daughter board control device 2 can be combined with different daughter board circuit boards 11,
To meet the testing requirement to different chips to be tested.Daughter board control device 2 is not only simplified using inserting moduleization design
Wires design on daughter board circuit board 11, reduces the interference that cabling transmits signal, moreover it is possible to recycle Reusability.In addition,
For different chips to be tested, replacement daughter board control device 2 can not had to, it is only necessary to replace corresponding daughter board circuit board i.e.
Can, so that motherboard circuit plate, motherboard control device and daughter board control device are reused, good compatibility.
Daughter board control device 2 receives son by 4 pairs of high-speed differential signals (CLK P/N, CS P/N, DI P/N, DO P/N)
The control information (the control information can be sent by ageing motherboard and be transmitted through daughter board circuit board 11) that plate circuit board 11 transmits, should
Control information includes: the heating device of start and stop ageing seat, the radiator of start and stop ageing seat, setting one single chip shell temperature offset
One or more of information such as (base temperature), the chip shell temperature offset (offset temperature) that whole cabinet is set.Son
Plate control device 2 issues control signal to ageing seat 3 according to the control information.For example, thermal control signals are sent to ageing
Heating device or radiating control signal on seat is to the radiator on ageing seat.Daughter board control device 2 also sends excitation letter
Number to the chip to be tested in ageing seat 3.Daughter board control device 2 receives the corresponding detection signal of chip to be tested (i.e. daughter board electricity
The corresponding detection signal of road plate) and detection information is generated, the corresponding detection of chip to be tested is believed by 4 pairs of high-speed differential signals
Breath through daughter board circuit board 11 passes to ageing motherboard 4, which includes: the survey whether working properly of chip shell temperature, chip
It is test result, cpu chip operating voltage, one or more kinds of in the information such as ambient temperature of ageing seat.
In some embodiments, temperature feeding mechanism includes heating device corresponding with the chip to be tested.Optionally,
The heating device is set in ageing seat, the heating device under the control of daughter board control device, for in ageing seat to
Test chip is heated.Optionally, temperature feeding mechanism further includes radiator corresponding with chip to be tested, heat dissipation dress
Setting can be the radiator fan being set in ageing seat, and the working condition of the radiator fan is controlled by daughter board control device, from
And improve the control precision to ageing temperature.
In some embodiments, ageing daughter board 1 further include: temperature sensor, the temperature sensor are electrically connected the son
Plate circuit board 11, for detecting the corresponding shell temperature of the chip to be tested.Optionally, which is set to ageing seat
In receiving, for the corresponding chip shell temperature of detection chip to be tested.It in some embodiments, further include for detecting ageing seat
The temperature acquisition chip of ambient temperature.It is realized by temperature sensor, temperature acquisition chip to chip shell temperature, ageing seat week
The Simultaneous Monitoring of the environment temperature on side.Temperature collection circuit 15 is set on daughter board circuit board 11, and temperature sensor acquires core in real time
Piece shell temperature and/or the environment temperature on ageing seat periphery are simultaneously converted into thermo-electromotive force, are transmitted to the temperature on daughter board circuit board through circuit
It spends in Acquisition Circuit 15.The thermo-electromotive force of temperature sensor acquisition back is transferred to son through filtering processing by temperature collection circuit 15
Plate control module 2, in order to which daughter board control module 2 generates control signal according to temperature signal.
In the present embodiment, daughter board circuit board 11 is equipped with power module 13, which receives motherboard circuit plate 41
The DC power supply of offer and it is converted after supply electricity to daughter board control device 2.Power interface 16, power supply are set on daughter board circuit board 11
Interface 16 receives the DC power supply that motherboard circuit plate provides and supplies electricity to ageing seat 3.Optionally, power module 13 uses DC-DC
Power module, in one example, power module 13 include 6 tunnel DC-DC power modules, wherein and 5 road power modules are 12V input,
0.8V-17V/6A output；Other 1 road power module is 12V input, and 0.7V-3.6V/30A output supplies for chip core power supply
Electricity.DC-DC power module output voltage values can export different voltages value with ratio according to module difference resistance.User can also root
DC-DC power module is increased or decreased according to the actually required operating voltage quantity of chip, and DC-DC power module can recycle benefit repeatedly
With.
In some embodiments, optionally, the work electricity for detecting the chip to be tested is set on daughter board circuit 11
The voltage observation point 14 of pressure.The operating voltage of chip to be tested, can be with other than carrying out automatic detection through daughter board control module
Realize detection by the cooperation of voltage observation point 14 on the measuring devices such as oscillograph and daughter board circuit board 11, convenient for artificial detection and
Whether the operating voltage for verifying chip to be tested is normal.
In some embodiments, it is additionally provided with multiple fixation holes 113 on daughter board circuit board 11, for example, is opened in daughter board circuit
Multiple fixation holes 113 in 11 surrounding of plate, daughter board circuit board 11 are fixed on motherboard plate circuit board 41 by fixation hole 113.
Referring to Fig. 6, daughter board control device 2 includes: second control circuit plate 21 and second controller.Second control circuit
Plate 21 is installed on daughter board circuit board 11 and is electrically connected with daughter board circuit board 11.Second controller is set to second control circuit
On plate 21, temperature feeding mechanism, and reception pair are given for sending stimulus signals to corresponding chip to be tested, sending control signal
The detection information for the chip to be tested answered.Second controller is in ageing seat through control signal control temperature feeding mechanism
Chip to be tested provides suitable ageing temperature, realizes the independent heating to chip to be tested, and second controller sends excitation
The internal element that signal controls chip to be tested works at a temperature of corresponding ageing, and receives the corresponding inspection of daughter board circuit board 11
Signal is surveyed, and then determines the corresponding working condition of chip to be tested on daughter board circuit board 11.
In the present embodiment, daughter board control device 2 is installed on daughter board circuit board 11 through second control circuit plate 21, the daughter board
Control device 2 independently can carry out ageing test to the chip to be tested on daughter board circuit board 11, simplify daughter board circuit board
On wires design, reduce the interference that cabling transmits signal, and daughter board can be passed through by individually controlling chip to be tested
The combination of circuit board can satisfy the testing requirement to different chips to be tested.In addition, being tested to different chips
When, it is only necessary to daughter board circuit board is replaced, daughter board control device 2, motherboard circuit plate, motherboard control device can reuse,
So that compatibility is more preferable.In addition, when daughter board circuit board 11 or daughter board control device 2 break down, it is only necessary to failure
Part is replaced, convenient for safeguarding.
In some embodiments, the second controller being set on second control circuit plate 21 includes that the secondary scene is programmable
Gate array FPGA 22, the second Micro-processor MCV 23.Third connector 24, the second control are set on second control circuit plate 21
Circuit board 21 is electrically connected through third connector 24 with daughter board circuit board 11.2nd FPGA 22 is communicated to connect with daughter board circuit board 11；
2nd MCU 23 and the 2nd FPGA 22 and daughter board circuit board 11 are communicated to connect.2nd MCU 23 is for controlling daughter board circuit board
11, the control signal, the working condition of control temperature feeding mechanism, control core to be tested that the 2nd FPGA 22 is issued are received
Piece electric sequence receives the corresponding detection signal of daughter board circuit board 11 and is uploaded to the 2nd FPGA 22.2nd FPGA 22 is used for
The corresponding chip to be tested is sent stimulus signals to control the work of the internal element of the chip to be tested, and according to institute
It states the internal element of the chip to be tested corresponding output signal under the pumping signal and determines that the chip to be tested is corresponding
Test result issues control signal to the 2nd MCU 23 and receives the corresponding inspection of daughter board circuit board 11 uploaded through the 2nd MCU 23
Survey signal.For example, using cpu chip as chip to be tested, the 2nd FPGA 22 loads pumping signal to cpu chip, for testing
Cpu chip is in corresponding ageing temperature environment center Core, Double Data Rate synchronous DRAM DDR, serial computer
Expansion bus PCIE, universal input/output GPIO, memory Memory, phase-locked loop pll, serial peripheral equipment interface SPI, I2C
(Inter-Integrated Circuit), bridge protocol conversion circuitry GMAC, LPC (Low Pin Count), JTAG (Joint
Test Action Group, joint test behavior tissue), universal asynchronous receiving-transmitting transmitter UART, interrupt control unit, directly in
It accesses DMA controller, reset whether the internal elements such as RES, clock CLK are working properly, and specific test mode can be using use
Family input customized energisation mode, BIST (Built-in Self Test, built-in self-test) measuring technology or be based on JTAG
The Boundary-scan test technology of standard.The internal element that 2nd FPGA 22 receives cpu chip is corresponding under the pumping signal
Output signal obtains test result, and then determines whether cpu chip internal element function is normal.
2nd MCU 23 is communicated by spi bus interface or parallel communication interface with the 2nd FPGA 22, and the 2nd FPGA is received
The control signal issued, and according to the working condition of control signal control daughter board circuit board.In some embodiments, the 2nd FPGA
22 according to motherboard circuit plate send control information issues control signal, the control information include: start and stop ageing seat heating device,
Whole the radiator of start and stop ageing seat, setting single cpu shell temperature offset (base temperature), setting cabinet CPU shell temperature deviate
Measure one or more of information such as (offset temperature).2nd MCU 23 also receives the corresponding detection of the daughter board circuit board
Signal is simultaneously uploaded to the 2nd FPGA 22, and then determines the corresponding working condition of chip to be tested on daughter board circuit board 11.The
Two FPGA 22 the corresponding detection signal of daughter board circuit board 11 and determine that the corresponding test of the chip to be tested is tied based on the received
Fruit sends detection information and is sent to ageing control to the motherboard control device 5 on motherboard circuit plate 41, then through motherboard control device 5
Equipment.The detection information includes the detection signal of the chip to be tested and the test result of the chip to be tested.
By using the operating mode that the 2nd MCU and the 2nd FPGA cooperates, the 2nd MCU may be implemented, the 2nd FPGA is carried out
Data configuration not only simplifies circuit to save the configuration memory circuit of the 2nd FPGA, also saves hardware cost.
Second control circuit plate 21 also sets up power circuit 25, which obtains daughter board electricity through third connector 24
The DC power supply that road plate 11 provides, and the DC power supply is converted into suitable operating voltage and supplies electricity to the 2nd FPGA 22, second
MCU 23.In one embodiment, power circuit 25 by direct current DC12V power supply it is converted after export DC3V3 and DC1V2.Optionally,
DC12V is set on second control circuit plate 21 and debugs power interface 251, in order to individually be debugged to daughter board control device.
In some embodiments, daughter board control device 2 further include: voltage sample module 26, the voltage sample module 26 connect
The 2nd MCU 23 is met, for detecting the operating voltage of the chip to be tested and passing to the 2nd MCU 23.The relevant technologies
In, ageing test is general first to carry out high temperature test, re-test chip electrical characteristic to chip, therefore can not judge hot environment pair
The influence of chip operation performance.Some chips exist under the high temperature conditions electrical characteristic performance decline even failure but at room temperature
Electrical characteristic restores normal phenomenon again, and what traditional ageing test can not filter out chip restores failpoint.The present embodiment
By the operating voltage of 26 acquisition chip of voltage sample module, electrical characteristic survey can be carried out while realizing in ageing test
Examination, capable of effectively identifying chip, the decline of electrical characteristic performance is even failed under the high temperature conditions but electrical characteristic is again extensive at room temperature
Multiple normal phenomenon.Optionally, which provides DC3V3 operating voltage by power circuit 25.The voltage sample
The voltage clock signal sampling module CLK of module 26 can be provided by the 2nd FPGA 22, and reset signal RST and logic export
DRDY can be controlled by the 2nd MCU 23.The voltage sample module 26 can receive second by serial peripheral equipment interface SPI bus
The operating voltage of the chip acquired in real time is simultaneously passed to the 2nd MCU 23 by the control signal of MCU 23.
In some embodiments, temperature sensor, daughter board control device further include: analog-to-digital conversion are set on daughter board circuit board
Device 29, analog-digital converter 29 connect the 2nd MCU 23, and the transducing signal for acquiring the temperature sensor is converted to number
Signal simultaneously passes to the 2nd MCU 23.
In some embodiments, temperature feeding mechanism includes heating device corresponding with the chip to be tested；Daughter board control
Device processed includes: heat control unit 27, connects the second controller, for controlling the working condition of the heating device.
The heat control unit 27 connects the 2nd MCU 23, which can be metal-oxide-semiconductor or other switching circuits, root
According to the heating enable signal (EN) that the 2nd MCU 23 is sent, heat control unit 27 sends thermal control signals and controls heating device
Work.Optionally, the 2nd MCU 23 is compared according to the first temperature threshold of setting with the temperature that temperature sensor detects, root
Heating enable signal is generated according to comparison result, to realize the control to heating device.
In some embodiments, optionally, the temperature feeding mechanism further includes dissipates corresponding with the chip to be tested
Thermal；The daughter board control device further include: radiating control unit 28 connects the second controller, described for controlling
The working condition of radiator.The radiating control unit 28 connects the 2nd MCU 23, which can be metal-oxide-semiconductor
Or other switching circuits, according to the heat dissipation enable signal (EN) that the 2nd MCU 23 is sent, radiating control unit 28 sends heat dissipation
Control signal control radiator work.Optionally, the 2nd MCU 23 is according to the second temperature threshold value and temperature sensor of setting
The temperature of detection is compared, and heat dissipation enable signal is generated according to comparison result, to realize the control to radiator.
In some embodiments, the operating voltage of the 2nd FPGA 22 is DC3V3, DC1V2, and the 2nd FPGA is by power circuit
25 power supplies.2nd FPGA 22 downloads the 2nd FPGA program of exploitation debugging through JTAG.2nd FPGA 22 can be by the 2nd MCU
23 generate clock signal clk, can also generate clock by the reserved crystal oscillator in outside.2nd FPGA 22 can be generated by the 2nd MCU 23
Reset signal RST can also be resetted by external hand.The 2nd connection configuration circuit of FPGA 22, for according to the 2nd FPGA user hand
Volume by the 2nd FPGA work normally institute must pin draw high or drag down processing.2nd FPGA 22 receives the 2nd MCU 23 to the
The control of two FPGA configuration pins.2nd FPGA 22 can connect Flash flash memory, after normally being powered on for the 2nd FPGA 22,
2nd MCU, 23 tranmitting data register signal (CLK) and reset signal (RST) give the 2nd FPGA 22, and the 2nd FPGA 22 is total by SPI
Line interface reads the second FPGA configuration file from Flash, is loaded into the 2nd FPGA 22.
In some embodiments, optionally, daughter board control device 2 further include: third indicator light 221, third indicator light 221
The 2nd FPGA 22 is connected, the working condition of the 2nd FPGA 22 is used to indicate.Specifically, 22 program of the 2nd FPGA load is completed,
DONE pin exports high level, and it is bright that program loads indicator light；2nd FPGA 22 is working properly, and HEART pin exports low level,
Working station indicator is bright.
In some embodiments, the 2nd FPGA 22 by 4 pairs of high-speed differential signals (CLK P/N, CS P/N, DI P/N,
DO P/N) the corresponding detection information of chip to be tested passed into the motherboard control device 5 in ageing motherboard 4 through ageing daughter board 1,
The test information includes: chip shell temperature, chip test result whether working properly, chip operating voltage, around ageing seat
It is one or more kinds of in the information such as environment temperature.2nd FPGA, 22 output drive signal gives chip to be tested, and for example the excitation is believed
It number include: timing, chip controls signal, I/O foot pumping signal, special pin pumping signal (the 2nd FPGA needed for test chip
I/O pin be connected on third connector 24, for test different chips when, reserve load pumping signal or receive chip
The pin of output signal).
In some embodiments, the 2nd FPGA 22 receives the control information of ageing motherboard 4 by 4 pairs of high-speed differential signals,
Control information includes: the heating device of start and stop ageing seat, the radiator of start and stop ageing seat, setting one single chip shell temperature offset
The information such as (base temperature), the chip shell temperature offset (offset temperature) that whole cabinet is set.2nd FPGA 22 is according to described
Control information issues control signal to the 2nd MCU 23.
2nd FPGA 22 is communicated by spi bus interface or parallel communication interface with the 2nd MCU 23, and the 2nd MCU is received
The corresponding detection signal of the daughter board circuit board of acquisition, the detection signal include: chip shell temperature, the operating voltage of chip, ageing seat
One or more of information such as ambient temperature.2nd FPGA 22 receives chip I/O foot and the output of special pin is believed
Number, and it is pocessed analysis, whether normal judge chip interior Elementary Function, and then whether the internal element for obtaining chip is normal
Test result.
In some embodiments, power circuit 25 is that the 2nd MCU 23 provides DC3V3 working power, and the 2nd MCU 23 is by interior
Portion's crystal oscillator generates clock, is reserved with external crystal-controlled oscillation.2nd MCU 23 supports external hand to reset and house dog software reset.Second
MCU 23 updates the 2nd MCU program by serial ports (UART) downloading, to meet the demand for control of different ageing tests.Optionally,
2nd MCU 23 can control 22 configuration pin of the 2nd FPGA.
2nd MCU 23 is communicated by spi bus interface or parallel communication interface with the 2nd FPGA 22, and by the son of acquisition
The corresponding detection signal of plate circuit board passes to the 2nd FPGA 22.The corresponding detection signal of the daughter board circuit board includes: chip shell
Temperature, chip are under pumping signal in the information such as corresponding output signal, the operating voltage of chip, ageing stand ambient temperature
One or more.
2nd MCU 23 is communicated by spi bus interface or parallel communication interface with the 2nd FPGA 22, and motherboard circuit is received
After plate is to the control information of daughter board circuit board, the working condition of daughter board circuit board is controlled, control information includes: start and stop ageing seat
Whole heating device, the radiator of start and stop ageing seat, setting single cpu shell temperature offset (base temperature), setting cabinet CPU
One or more of information such as shell temperature offset (offset temperature).
2nd MCU 23 controls the working condition of voltage sample module 26 by spi bus and receives voltage sample module 26
The operating voltage of the chip of acquisition back, and judge whether normal.2nd MCU 23 simultaneously passes through real-time voltage and judging result
Spi bus or parallel communication interface pass to the 2nd FPGA 22.2nd MCU 23 to 26 reset signal of voltage sample module and/
Or control module logic output.
The temperature information acquired in real time can be compared by the 2nd MCU 23 with ageing temperature range set by user, root
Heating enable signal is sent to heat control unit according to different situations.When chip shell temperature is less than user's set temperature, the 2nd MCU
23 send effective enable signal, heating device heated at constant temperature to heat control unit.When chip shell temperature is set more than or equal to user
When temperature or environment temperature are greater than 85 DEG C, the 2nd MCU 23 sends invalid enable signal to heat control unit, and heating device stops
Only heat.
2nd MCU 23 can send heat dissipation enable signal to radiating control unit, control the working condition of radiator.
For example, by taking radiator fan as an example, when chip shell temperature, which is more than or equal to user, sets the exothermic temperature upper limit, the 2nd MCU 23 is to heat dissipation
Control unit transmission has heat dissipation effect enable signal, the radiator fan rotation on ageing seat；Heat dissipation temperature is set when temperature is less than user
When spending lower limit, the 2nd MCU 23 sends invalid enable signal to radiating control unit, the radiator fan stalling on ageing seat.
In some embodiments, optionally, daughter board control device further include: the 4th indicator light 231 connects the 2nd MCU
23, it is used to indicate the working condition of chip to be tested.Specifically, the second indicator light 231 may include: work light, heating
Indicator light one or more of samples indicator light, powers on indicator light, temperature indicator, self-test indicator light.For example, chip
Working properly, ALIVE pin exports low level, and work light is bright.Heating device is heating, and the output of HEATING pin is low
Level, heating lamp are bright.Voltage sample module is working properly, and SAMPLING pin exports low level, and sampling indicator light is bright.Core
Piece powers on completion, and PWRGOOD pin exports low level, it is bright to power on indicator light.Chip temperature in user's specified for temperature ranges,
TEMPOK pin exports low level, and temperature indicator is bright.Ageing System self-test is completed, and DEBUG pin exports low level, and self-test refers to
Show that lamp is bright.
In some embodiments, multiple fixation holes 211 are offered on second control circuit plate 21 be for example opened in second
Multiple fixation holes 211 in control circuit board surrounding, second control circuit plate 21 are fixed on daughter board circuit board by fixation hole 211
On 11 third installing zone 111.
The above, the only specific embodiment of the application, but the protection scope of the application is not limited thereto, it is any
Those familiar with the art within the technical scope of the present application, can easily think of the change or the replacement, and should all contain
Lid is within the scope of protection of this application.Therefore, the protection scope of the application should be based on the protection scope of the described claims.
Claims (10)
1. a kind of ageing system characterized by comprising at least one piece of ageing motherboard and at least one piece of ageing daughter board；
The ageing motherboard includes motherboard circuit plate, motherboard control device, and the motherboard control device is set to the motherboard electricity
On the plate of road；
The ageing daughter board includes daughter board circuit board, daughter board control device, and the daughter board control device is set to the daughter board electricity
On the plate of road, the daughter board circuit board is electrically connected with the motherboard circuit plate, is arranged on the daughter board circuit board to be measured for connecting
Try the first interface circuit of chip, for connecting to the temperature feeding mechanism of the chip offer ageing temperature environment to be tested
Second interface circuit；
Wherein, the ageing motherboard through the motherboard control device send control information to the corresponding ageing daughter board, it is described
Ageing daughter board controls the corresponding chip to be tested through the daughter board control device and the temperature feeding mechanism carries out ageing
Test, the daughter board control device receive the detection information of the corresponding ageing daughter board and are sent to the motherboard control dress
It sets.
2. ageing system as described in claim 1, which is characterized in that the motherboard control device includes:
First control circuit plate is installed on the motherboard circuit plate and is electrically connected with the motherboard circuit plate；
First controller is set on the first control circuit plate, for sending the control information to corresponding described old
Daughter board is refined, and receives corresponding detection information on the ageing daughter board.
3. ageing system as described in claim 1, which is characterized in that first controller includes:
Primary scene programmable gate array FPGA is connect with the motherboard circuit board communications；
First microprocessor MCU is communicated to connect with the first FPGA and the motherboard circuit plate；
Wherein, the first MCU is for sending the control information to the first FPGA, and the first FPGA is for receiving institute
The control stated corresponding detection information on ageing daughter board and be sent to the first MCU, and sent according to the first MCU
The corresponding ageing daughter board of information control carries out ageing test.
4. ageing system as claimed in claim 3, which is characterized in that the motherboard control device further include:
First indicator light connects the first FPGA, is used to indicate the working condition of the first FPGA；And/or
Second indicator light connects the first MCU, is used to indicate the working condition of the first MCU.
5. ageing system as described in claim 1, which is characterized in that the daughter board control device includes:
Second control circuit plate, be installed on the daughter board circuit board and with the daughter board circuit board electrical connection；
Second controller is set on the second control circuit plate, for being sent stimulus signals to according to the control information
The corresponding chip to be tested sends control signal to the temperature feeding mechanism, and receives the corresponding ageing daughter board
Detection information.
6. the ageing system, which is characterized in that the second controller includes:
Secondary scene programmable gate array FPGA is communicated to connect with the daughter board circuit board；
Second Micro-processor MCV is communicated to connect with the 2nd FPGA and the daughter board circuit board；
Wherein, the 2nd FPGA is described to be measured to control to the corresponding chip to be tested for sending the pumping signal
Try the internal element work of chip, and the corresponding output under the pumping signal according to the internal element of the chip to be tested
Signal determines the corresponding test result of the chip to be tested, and the 2nd MCU is for receiving the institute that the 2nd FPGA is issued
Control signal is stated, the working condition of the temperature feeding mechanism is controlled according to the control signal, receives the daughter board circuit board
Corresponding detection signal is simultaneously uploaded to the FPGA.
7. ageing system as claimed in claim 6, which is characterized in that the daughter board control device further include:
Voltage sample module connects the 2nd MCU, for detecting the operating voltage of the chip to be tested and passing to described
2nd MCU.
8. ageing system as claimed in claim 6, which is characterized in that the daughter board control device further include:
Third indicator light connects the 2nd FPGA, is used to indicate the working condition of the 2nd FPGA；And/or
4th indicator light connects the 2nd MCU, is used to indicate the working condition of the chip to be tested.
9. ageing system as described in claim 1, which is characterized in that the ageing motherboard further include:
Communication interface is set on the motherboard circuit plate and connects the motherboard control device, for controlling the motherboard
Device and external control equipment communicate to connect.
10. ageing system as claimed in claim 5, which is characterized in that the temperature feeding mechanism include with it is described to be tested
The corresponding heating device of chip；The daughter board control device includes: heat control unit, connects the second controller, is used for
Control the working condition of the heating device.
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| CN201910139748.2A CN109884940A (en) | 2019-02-26 | 2019-02-26 | Ageing system |
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| CN201910139748.2A CN109884940A (en) | 2019-02-26 | 2019-02-26 | Ageing system |
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| CN113905227A (en) * | 2021-10-18 | 2022-01-07 | 中国科学院长春光学精密机械与物理研究所 | Video processing chip aging device and method based on daisy chain |
| CN114397872A (en) * | 2021-12-28 | 2022-04-26 | 北京航天新立科技有限公司 | An automatic measurement and control system and method for controller environmental stress screening test |
| CN114397872B (en) * | 2021-12-28 | 2025-04-08 | 北京航天新立科技有限公司 | Automatic measurement and control system and method for controller environmental stress screening test |
| CN115453328A (en) * | 2022-09-29 | 2022-12-09 | 北京物芯科技有限责任公司 | A chip aging system, method, device, equipment and medium |
| CN117214676A (en) * | 2023-11-09 | 2023-12-12 | 成都梓峡信息技术有限公司 | FPGA aging test system |
| CN117214676B (en) * | 2023-11-09 | 2024-01-23 | 成都梓峡信息技术有限公司 | FPGA aging test system |
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