CN119758031A - A chip function testing method, test control module, equipment and device - Google Patents
A chip function testing method, test control module, equipment and device Download PDFInfo
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Abstract
The invention discloses a method, a module, a device and a device for testing chip functions, wherein when a chip to be tested releases a power-on reset signal and ends the power-on reset state, the test control module is subjected to test related configuration through a JTAG interface of the chip to be tested, the chip to be tested and automatic test equipment are controlled to establish a synchronous state, and the chip to be tested is tested and a test result is output. According to the technical scheme, the test control module is added in the chip design stage, so that the automatic test equipment can establish the synchronous state of the external reset and the external clock according to the mode that the automatic test vector directly provides the external reset and the external clock for the chip to be tested, the chip function test can meet the requirement of the synchronous test method of the automatic test equipment, various function tests can be rapidly realized on the automatic test equipment, and the automation degree, the test efficiency and the stability of the function test are effectively improved.
Description
Technical Field
The invention relates to the technical field of testing, in particular to a method, a control module, equipment and a device for testing chip functions.
Background
In the chip Design and production process, design for Test (DFT) has been widely used as a key technology for ensuring product quality and eliminating chips with manufacturing defects. Testability design improves the testability, including controllability and observability, of a chip by inserting specific testability circuits during the chip design phase. The technology runs through each stage in the chip development process, and in the chip production test stage, a testability circuit, automatic test equipment (ATE, automatic Test Equipment) and an Automatic test vector (ATP, automatic TEST PATTERN) are utilized to test the chip, so that the chip with manufacturing defects is removed, and the delivery quality of the chip is ensured.
In the chip production test stage, automatic test equipment and automatic test vectors are generally adopted to complete nonfunctional test, and functional test depends on a system test board and a test program. However, there are a number of disadvantages to the system test board as compared to automated test equipment. The design of the system test board needs to be customized by combining with the chip function, the problem which is unexpected is possibly introduced in the customization process, the problem is processed based on the follow-up requirement, the test efficiency is low, the universality and the stability of the system test board are poor, and the system test board is difficult to adapt to the requirements of alternating current parameter test, direct current parameter test, fault injection test and the like.
Therefore, the chip function test method in the related art has the technical problems of low test efficiency, poor stability and the like.
Disclosure of Invention
The invention mainly aims to provide a method, a module, equipment and a device for testing chip functions, and aims to at least solve the technical problems of low testing efficiency, poor stability and the like of the chip function testing method in the related technology.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
In a first aspect of the present invention, a method for testing a chip function is provided, and the method is applied to an automated testing device, where the method for testing a chip function includes:
controlling the chip to be tested to be in a power-on reset state and an external reset state at the same time in the initial stage of power-on;
When the chip to be tested releases a power-on reset signal and ends the power-on reset state, performing test related configuration on a test control module through a JTAG interface of the chip to be tested, and controlling the chip to be tested and the automatic test equipment to establish a synchronous state, wherein the test control module is integrated in the chip to be tested in advance;
when the external reset signal of the chip to be tested is released and the external reset state is ended, the chip to be tested executes function test preparation operation;
And controlling the chip to be tested to test according to the selected functional test item and outputting a test result, wherein the functional test item comprises a synchronous functional test or an asynchronous functional test.
In a second aspect of the present invention, a test control module is provided, where the test control module is integrated in the chip to be tested, and the test control module is provided with a JTAG interface, a bus slave interface, a general register, a counter, and a configuration register;
The test control module is designed to be in two aspects of reset and clock:
In the reset aspect, a reset signal of the test control module adopts a power-on reset signal, when the chip to be tested is in an external reset state, the automatic test equipment sets a test_mode signal output by the test control module high through a JTAG interface, so that the logic of an internal reset circuit of the chip to be tested is changed and can be directly driven and controlled by external reset through an external reset pin of the chip;
in terms of clock, when the chip to be tested is in an external reset state, the automatic test equipment sets a test_mode signal output by the test control module high through a JTAG interface, so that the logic of an internal clock circuit of the chip to be tested is changed and can be directly driven and controlled by an external clock through an external clock pin, and meanwhile, the external clock provided by the automatic test equipment can be freely transmitted in the clock circuit to start a bus clock of the test control module;
The test control module is used for realizing the test method of the chip function according to the first aspect.
In a third aspect of the present invention, an automated test equipment is provided, the automated test equipment comprising:
The first control module is used for controlling the chip to be tested to be in a power-on reset state and an external reset state at the same time in the initial stage of power-on;
The configuration module is used for carrying out test related configuration on the test control module through a JTAG interface of the chip to be tested and controlling the chip to be tested and the automatic test equipment to establish a synchronous state when the chip to be tested releases a power-on reset signal and ends the power-on reset state;
The second control module is used for executing function test preparation operation on the chip to be tested when the external reset signal of the chip to be tested is released and the external reset state is ended;
And the test module is used for controlling the chip to be tested to test according to the selected functional test item and outputting a test result, wherein the functional test item comprises a synchronous functional test or an asynchronous functional test.
In a fourth aspect of the present invention, there is provided an electronic device comprising a memory, a processor and a bus, the bus being adapted to enable a connection communication between the memory and the processor, the processor being adapted to execute a computer program stored on the memory, the processor implementing the steps in the method for testing a chip function as in the first aspect when the processor executes the computer program.
According to the method, the test control module, the device and the device for testing the chip function, the chip to be tested is controlled to be in the power-on reset state and the external reset state at the same time in the initial stage of power-on, when the chip to be tested releases a power-on reset signal and ends the power-on reset state, the test control module is subjected to test related configuration through the JTAG interface of the chip to be tested, the chip to be tested and the automatic test device are controlled to establish a synchronous state, and when the external reset signal of the chip to be tested releases and ends the external reset state, the chip to be tested executes function test preparation operation, and the chip to be tested is controlled to test and output a test result according to the selected function test item. Compared with the prior art that a system test board is adopted for testing, the technical scheme is based on adding the test control module in the chip design stage, so that the automatic test equipment can directly establish the synchronous state of the external reset and the external clock for the chip to be tested according to the automatic test vector, the chip function test can meet the requirement of the synchronous test method of the automatic test equipment, the unexpected problem is avoided being introduced when the system test board is adopted for testing, and therefore, various function tests can be realized on the automatic test equipment rapidly, and the automation degree, the test efficiency and the test stability of the function test are improved effectively.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of an automated test equipment according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for testing chip functions according to an embodiment of the present application;
FIG. 3 is a schematic diagram of clock, reset and test_mode signals in different stages in a method for testing chip functions according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating an internal structure of a test control module according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an output circuit in a configuration register according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a circuit connection of a FLASH mode configuration register according to an embodiment of the present application;
FIG. 7 is a flow chart of a method for testing chip functions according to an embodiment of the present application;
FIG. 8 is a flow chart of a method for testing chip functions according to an embodiment of the present application;
FIG. 9 is a schematic diagram of an internal structure of a chip under test in the related art;
FIG. 10 is a schematic waveform diagram of clock reset signals in different stages of a chip to be tested in the related art during a chip function test;
FIG. 11 is a schematic waveform diagram of clock reset signals in different stages of a chip to be tested in the related art during a chip function test;
FIG. 12 is a schematic diagram of an internal structure of a chip under test according to an embodiment of the present application;
FIG. 13 is a schematic diagram of module connection in an automated test equipment according to an embodiment of the present application;
fig. 14 is a schematic diagram of structural connection of an electronic device according to an embodiment of the application.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It is noted that related terms such as "first," "second," and the like may be used to describe various components, but these terms are not limiting of the components. These terms are only used to distinguish one element from another element. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present invention. The term "and/or" refers to any one or more combinations of related items and descriptive items.
In the chip design and production process, in order to ensure the product quality and remove chips with manufacturing defects, a testability design method is generally adopted, and the testability of the chips is improved by inserting a specific testability circuit in the chip design stage, and the chips can be tested by using the testability circuit, the automatic test equipment and the automatic test vector in the chip production test stage to remove the chips with the manufacturing defects so as to ensure the delivery quality of the chips.
The design can be divided into two types according to whether the testable design is related to the function of the chip, namely a nonfunctional testable design and a functional testable design. The nonfunctional testability design is to test the chip circuit structure itself, independent of the function of the chip itself. The functional test can detect whether the chip has functional faults in the chip production test, such as communication interface communication abnormality, low power consumption mode abnormality, digital-to-analog conversion result abnormality and the like. Therefore, the test of all faults of the chip can be covered only by combining the nonfunctional test and the functional test, and a complete production test flow is realized.
In the chip production test stage, automatic test equipment and automatic test vectors are generally adopted to complete nonfunctional test, and functional test depends on a system test board and a test program. However, there are a number of disadvantages to the system test board as compared to automated test equipment. The design of the system test board needs to be customized by combining the functions of the chip, the problem that the customization process possibly introduces is unexpected, the universality and the stability of the system test board are poor, and the system test board is difficult to adapt to the requirements of alternating current parameter test, direct current parameter test, error injection test and the like.
Therefore, the chip function test method in the related art has the technical problems of low test efficiency, poor stability and the like.
In order to solve the above technical problems, referring to fig. 1, the present embodiment provides an automated testing system capable of executing a testing method of a chip function.
The automatic test system comprises a computer, automatic test equipment, a printed circuit board, a chip clamp and a test chip. Specifically, the automated test vector has an expected input and an expected output for each clock cycle during the functional test of the chip under test. The automatic test equipment adopts a synchronous test method, namely the automatic test equipment generates expected input signals (such as clock, reset and data) of the chip to be tested cycle by cycle according to the automatic test vector, compares expected output and actual output of the chip to be tested, and completes the test process in a synchronous state. The printed circuit board is connected with the automatic testing equipment and the testing circuit, the chip clamp is used for fixing and facilitating replacement of the chip to be tested, and the chip to be tested can be tested in a complex function (such as USB function) part of the chip to be tested. In the function test, the automatic test equipment requests the output of each clock period of the chip to be tested to be consistent with the expected output through a synchronous test method, and whether the test result passes or not determines the qualification of the chip to be tested. The test is performed according to whether the chip to be tested and the automatic test equipment always keep a synchronous state in the function test process, and the synchronous function test and the asynchronous function test are classified.
Referring to fig. 2 and 3, the method for testing chip functions according to the embodiment of the application includes the following steps:
step S201, the chip to be tested is controlled to be in a power-on reset state and an external reset state at the same time in the initial stage of power-on.
Specifically, when the chip to be tested needs to be functionally tested, a tester can enable the automatic testing equipment to be connected with the chip to be tested through the printed circuit board, and enable the chip to be tested to be powered on, so that the generation of a power-on reset signal is triggered, and the chip to be tested is enabled to enter a power-on reset state, so that the circuit of the chip to be tested is ensured to be in a determined state. Meanwhile, the control unit of the automatic test equipment generates an external reset signal and transmits the external reset signal to an external reset pin of the chip to be tested. Because the two reset signals are independently generated, the chip to be tested can simultaneously receive the effective power-on reset signal and the external reset signal in the power-on initial stage, and the consistency and the synchronism of the chip to be tested in the two reset states are ensured. That is, the automatic test equipment can control the chip to be tested to be in a power-on reset state and an external reset state at the same time in the initial stage of power-on, namely, belongs to the power-on reset stage in fig. 3, and lays a foundation for the configuration and functional test of the subsequent test control module.
Step S202, when the chip to be tested releases the power-on reset signal and ends the power-on reset state, the test control module is configured in a test correlation manner through the JTAG interface of the chip to be tested, and the chip to be tested and the automatic test equipment are controlled to establish a synchronous state.
Specifically, the automatic test equipment can monitor the power-on reset state of the chip to be tested in real time, and when the power-on reset signal is released, the power-on reset state of the chip to be tested is confirmed to be finished. This stage ensures that the internal logic of the chip under test has been initialized, i.e. all registers, counters and state machines have been reset to the default state. Alternatively, the automatic test equipment may also wait for a sufficient time until the chip to be tested automatically releases the power-on reset signal and ends the power-on reset state.
At this time, the automated test equipment can perform test related configuration on the test control module therein through the JTAG interface of the chip to be tested, i.e., the configuration stage of the test control module in fig. 3. In this embodiment, the design based on the JTAG interface complies with the IEEE 1149.X standard, and the automated test equipment may establish a communication connection with the test control module through the JTAG interface standard operation method, and may initiate an access operation to all register resources in the test control module.
It should be noted that, the test control module is a special functional module pre-integrated in the chip to be tested, and is generally embedded into the circuit structure of the chip based on a specific design in the design stage of the chip to be tested. The main functions of the test system are to provide control capability for the function test and debugging process of the chip to be tested, and the main functions are to establish synchronous states of the chip to be tested and automatic test equipment in the function test of the chip to be tested, transfer test information (such as selection of test items, configuration of test parameters, output of test results and the like), and support tasks such as waiting time debugging in asynchronous function test. The test control module typically interacts with the automated test equipment through an external interface (e.g., JTAG interface), accepts control of the automated test equipment, and performs corresponding operations. More specifically, the test_mode signal output by the test control module is set high to control the reset circuit logic and the clock circuit logic of the chip to be tested to change and be directly driven and controlled by the automatic test equipment so as to establish the synchronous state of the automatic test equipment and the chip to be tested, support the functional test of the chip to be tested and control the chip to be tested to enter different states to test and verify the target function. For example, by configuring different test parameters, functional testing and verification are performed in the states of synchronous and asynchronous logic, clock domain interaction, data throughput capability and the like of the chip to be tested.
The method comprises the steps of establishing a synchronous state of a chip to be tested and automatic testing equipment, namely, the automatic testing equipment provides external reset, external clock and input for the chip to be tested according to an automatic testing vector, so that the chip to be tested, the automatic testing equipment and the automatic testing vector are kept in the synchronous state completely.
In addition, the Reset signal of the test control module in the chip to be tested adopts a Power on Reset signal (POR), and other circuits of the chip to be tested can be in an external Reset state through the control of an external Reset pin except for the Power on Reset signal.
Step S203, when the external reset signal of the chip to be tested is released and the external reset state is ended, the chip to be tested performs the function test preparation operation.
Specifically, when the external reset signal of the chip to be tested is released and the external reset state is ended, that is, the external reset state of the chip to be tested is ended.
When the external reset state of the chip to be tested is finished, the chip to be tested executes the function test preparation operation comprising the processes of starting, initializing and selecting the function test items. I.e., in the start-up, initialization and functional test item selection phases of fig. 3, are as follows:
Firstly, after external reset is released, the reset circuit of the system in the chip to be tested firstly releases the reset of the starting module, and the starting module automatically starts to carry out the following 2 operations of 1, loading configuration data from FLASH, initializing some option parameters of the chip, such as chip trimming values (such as on-chip clock source frequency trimming), chip configuration options (such as on-chip LDO output voltage level, whether certain chip functions are enabled or not), and 2, loading a test program from FLASH to the SRAM in the chip to be tested, because the access speed of the FLASH is lower than that of the SRAM in the chip to be tested, and if the processor directly runs the test program from FLASH, the performance is limited by the access speed of the FLASH and is obviously reduced.
And secondly, initializing the process, namely after the starting module finishes working, releasing the reset of the processor by a system reset circuit in the chip to be tested, and automatically starting to execute a test program by the processor, wherein the initial part of the test program comprises the initialization work required by the program operation, such as initializing the initial address of a test program stack, initializing memory data, initializing the functions of the processor (such as multi-level cache enabling of the processor, enabling the functions of a bit zone and the like).
Finally, after the initialization of the test program is completed, the function test item selection process can be started, such as reading the test information stored in the general register of the test control module, and executing the function test item selection according to the test item selection information.
Step S204, according to the selected functional test items, the chip to be tested is controlled to be tested and the test result is output.
Specifically, when the selected functional test item is synchronous functional test in the functional test stage and the test result output stage in fig. 3, the chip to be tested is directly controlled to perform corresponding functional test and output a test result based on the synchronous state between the chip to be tested and the automatic test equipment which are realized in advance. And when the selected function test item is asynchronous function test, controlling and enabling the chip to be tested and the automatic test equipment to be in an asynchronous state so as to control the chip to be tested to perform corresponding function test and output test results. The test results are output in various manners, for example, the test results are judged through the high and low levels of the GPIO, and/or after the related test results are written into a general purpose register in the test control module, the test results are read by the automatic test equipment through a JTAG interface.
Therefore, compared with the test method adopting the system test board (belonging to the peripheral test circuit) to perform the function test in the related art, the test method of the embodiment of the application is based on adding the test control module (belonging to the testability design in the chip) in the chip design stage, and the synchronous state of the chip to be tested and the automatic test equipment can be directly established through the JTAG interface of the chip to be tested in the test process, so that the function test of the chip to be tested can meet the requirement of the synchronous test method of the automatic test equipment, and the automatic test advantages of good universality, high maturity and good reliability of the automatic test equipment are combined, the AC parameter and the DC parameter of the chip to be tested can be measured, the error injection test is easy to perform, and the like, and the unexpected problems possibly introduced by the peripheral test circuit are avoided, thereby realizing various function tests on the automatic test equipment rapidly, and improving the automation degree, the test efficiency and the test stability of the function test effectively. In addition, asynchronous function test can be performed according to actual test requirements.
In an alternative implementation manner of the embodiment, before the chip to be tested is in the power-on reset state and the external reset state at the same time in the initial stage of power-on, the method further comprises the steps of powering on the chip to be tested, enabling the chip to be tested to be in the power-on reset state, initializing a JTAG interface of the chip to be tested when the chip to be tested releases a power-on reset signal and ends the power-on reset state, accessing a FLASH mode configuration register of a test control module through the JTAG interface, controlling the FLASH mode configuration register to output a flash_mode signal in a high state, and burning a test program in the FLASH module through the FLASH interface of the chip to be tested when the FLASH module of the chip to be tested is in a burning mode.
Specifically, before performing a functional test, the automated test equipment accesses a FLASH mode configuration register of the test control module in the chip to be tested through a JTAG interface. In the process, the automatic test equipment performs write operation on the FLASH mode configuration register to enable the FLASH_mode output signal to be set high, so that the FLASH module is configured to enter a burning mode, and in the burning mode, the FLASH module is ready to receive test program data and can write the data into an internal storage unit to prepare the required test program data for subsequent functional test in advance. The "high" or "high state" generally indicates that the signal logic value is "1", that is, when the signal logic value is a preset high value, the flash_mode signal is in a high state, that is, indicates that the FLASH module is in the recording mode.
In an alternative implementation manner of the embodiment, the test control module is configured in a test-related manner through a JTAG interface of the chip to be tested, and specifically includes initializing the JTAG interface of the chip to be tested, accessing a test_mode test data register of the test control module, writing a set value of a test mode into the test_mode test data register, controlling the test_mode test data register to output a test_mode signal in a high state through the configured set value, and simultaneously performing initialization configuration required by testing a general register and a configuration register in the test control module.
Specifically, after the power-on reset of the chip to be tested is finished, firstly, initializing a JTAG interface of the chip to be tested through automatic test equipment, namely, initializing the JTAG interface of the chip to be tested through the automatic test equipment after the power-on reset of the chip to be tested is finished, wherein the initialization comprises synchronization of a clock signal (such as TCK), a data input signal (TDI) and an output signal (TDO) and reading of an IDCODE of the JTAG interface, so that the interface is ensured to be in a communicable state, the automatic test equipment establishes communication with the chip to be tested through the JTAG interface, and the follow-up register access is ensured to be correctly transmitted to a test control module in the chip.
The test data register is configured with a set value to set the test mode signal high, so that the internal reset circuit logic and the clock circuit logic of the chip to be tested are controlled to be changed, and the internal reset circuit logic and the clock circuit logic can be directly driven and controlled by external reset and external clocks. The automatic test equipment provides external reset, external clock and input for the chip to be tested according to the automatic test vector, so that the chip to be tested, the automatic test equipment and the automatic test vector are completely kept in a synchronous state.
And carrying out initialized configuration on the general register and the configuration register in the test control module. For example, the 1 st register in the general registers is initialized to 10, and the 10 th functional test item is selected as the functional test performed this time after the test program reads. The configuration register can control the state of the chip to be tested to test the function test item, for example, can configure the Low dropout regulator (LDO, low-Dropout Regulator) in the chip to be tested to perform the function test in the Low-voltage mode.
In an alternative implementation manner of the embodiment, the chip to be tested executes the function test preparation operation, which specifically includes the function test preparation operation of the chip to be tested starting the chip option parameter initialization configuration and the test program loading, and the test program initialization and the function test item selection flow. The universal register in the test control module provides test information for a test program of the chip to be tested, and the test information comprises test item selection, test parameter configuration, test result output, time sequence setting, interface multiplexing setting and the like.
In an alternative implementation manner of the embodiment, according to the selected functional test item, the chip to be tested is controlled to perform testing and output a test result, and specifically comprises the steps of controlling the chip to be tested to perform testing according to an automatic test vector under the condition that the selected functional test item is synchronous functional test and the automatic test equipment keeps synchronous, and outputting a test result comprising a comparison analysis between an expected output value of the automatic test vector and an actual output value of the chip to be tested, and controlling the chip to be tested to perform testing according to the automatic test vector under the condition that the selected functional test item is asynchronous functional test and the automatic test equipment are asynchronous, and outputting a test result comprising a comparison analysis between an expected output value of the automatic test vector and the actual output value of the chip to be tested and a waiting time required from an asynchronous test starting point to the output of the test result.
Specifically, the embodiment flexibly adapts to test requirements in different scenes by supporting synchronous function test and asynchronous function test. In the synchronous function test, the expected output value of the automatic test vector and the actual output value of the chip are accurately compared by keeping the synchronous state of the chip to be tested and the automatic test equipment, so that high accuracy and stability of the test result are ensured. In the asynchronous function test, the test result is analyzed in an asynchronous state, so that waiting time information from the starting point of the asynchronous test to the output of the test result is further provided, the debugging time required for determining the output waiting time of the test result in the asynchronous function test is reduced, and the development efficiency of the asynchronous function test is improved. The automatic generation of the test result obviously improves the test efficiency, reduces the possibility of human intervention, simultaneously provides detailed references for performance optimization, design improvement and potential problem investigation for rich comparative analysis and delay data, and improves the reliability and comprehensiveness of the whole test work.
Referring to fig. 4, a test control module of the embodiment of the present application is pre-integrated in a chip to be tested, and the test control module is provided with 2 access interfaces, 2 clock domains, 3 types of registers and related configuration signals.
In the test control module, the 2 access interfaces include a JTAG interface and a bus slave interface. The function description for the JTAG interface is as follows, the JTAG interface provides the capability of external access to the internal registers of the test control module, its design complies with IEEE 1149.X standard, and a 5-wire interface is adopted, the interface signals specifically include TMS (Test Mode Select) for test mode selection input, control of state machine in the test access interface Controller (TAP Controller, TEST ACCESS Port Controller), TCK (Test Clock) for test clock input, TDI (Test Data Input) for test data input, TDO (Test Data Output) for test data output, TRST (Test Reset) for test reset input. The adoption of the JTAG interface can be interconnected with other JTAG interfaces (typically JTAG interfaces of a processor) in the chip in a daisy-chain form, and led out of the chip in a single standard JTAG interface without adding an additional pin. And the functional description for the bus slave interface is that it provides the ability for the processor to access the test control module internal registers, which is designed to conform to AMBA bus standards such as AXI, AHB and APB standards, the slave interface being easily integrated into the chip internal bus.
In the test control module, the 2 clock domains include a TCK clock domain and a bus clock domain. The clock driving source of the circuit in the TCK clock domain is a TCK clock input by a JTAG interface, and the clock domain comprises a JTAG module and an interface module, and the functions of the JTAG module are described as follows, the JTAG module realizes a test access interface Controller (TAP Controller), an instruction register (IR, instruction Register), a BYPASS and an IDCODE test data register (TDR, test Data Register) of the IEEE 1149.X standard. And the interface module transmits the access operation of the TCK clock domain to the test control module register through the JTAG interface to the bus clock domain in a cross-clock domain manner and generates a control signal required by the access of the test control module register.
In order to implement the steps of performing test-related configuration on the test control module through the JTAG interface, controlling the test_mode test data register to output the test_mode signal in the high state through the configuration setting value, the configuration of the instruction register and the test_mode test data register in the test control module is shown in the following table 1.
In order to enable access to all registers in the test control module, such as general registers, counters, configuration registers, etc., through the JTAG interface, the configuration of the instruction registers in the test control module and the test data registers accessed by the test control module is shown in table 2 below.
TABLE 1
In table 1, the test_mode Test Data Register (TDR) is selected by configuring a set value to an Instruction Register (IR) of a test access interface Controller (TAP Controller) in the JTAG module, and when the test_mode test data register receives a preset set value (32' hxxxxxxxx), the test_mode signal output by the JTAG module is set high.
TABLE 2
In table 2 above, the test control module accesses the Test Data Register (TDR) by selecting the test access interface Controller (TAP Controller) Instruction Register (IR) configuration settings in the JTAG module. The test DATA register controls read and write operations (1 'b0 is read, 1' b1 is write) through WRn bits, specifies the register address using ADDR [7:0], BWE [3:0] sets byte write enable, DATA [31:0] is used to write or return DATA. In addition, the status bit is used for indicating whether the previous register access operation is completed (1 'b0 is complete and 1' b1 is incomplete), so that efficient read-write operation management of the register is realized.
The bus clock domain in the test control module, the clock drive of the internal circuit is derived from a bus clock, the clock domain comprises a bus interface module, an access arbitration module and a register, the bus interface module, the access arbitration module and the register function are described as follows, the bus interface module generates control signals required by the access of the internal registers of the test control module according to the bus access, when the access of the registers from JTAG and the access of the registers from the bus occur simultaneously, the access arbitration module is required to arbitrate the access conflict, a priority arbitration method is adopted, wherein the priority of the access of the registers from JTAG is always higher than the access of the registers from the bus, and the registers are classified into 3 types, namely general registers, counters and configuration registers.
The class 3 register function in the test control module is described as follows:
Specifically, the general-purpose registers comprise 8 32-bit readable and writable registers, and the transfer of test information, such as the selection of test items, the configuration of test parameters, the output of test results and the like, is realized between the automatic test equipment and the test program through the registers. The specific definition of each general register can be flexibly defined according to the functional test requirement condition.
Specifically, the counter includes 1 48-bit increment counter and associated control registers. When synchronous function test cannot be used in partial chip function test and asynchronous function test is necessary, the counter is used for conveniently calculating the waiting time required between the starting point of the asynchronous test and the output of the test result, so that the debugging and automation test equipment is convenient to inquire the time point of the asynchronous test result. In addition, designing an independent counter within the test control module instead of using a counter that may be present in the chip has the advantage that the counter bit width is freely selectable. The bit width of the existing counter of the chip can be limited by design indexes, and is generally under 32 bits and 32 bits, if the asynchronous function test time is too long, the counter overflow is most likely to be caused, and the counter of the test control module has the bit width of 48 bits, so that the counter overflow problem can be effectively avoided. And, the count clock of the counter is freely selectable. The existing counter of the chip is limited by the design of the system, when asynchronous function test is carried out, the counting clock of the counter can not be provided by the automatic test equipment, but the counter of the test control module is not limited by the design, and the automatic test equipment can be selected to directly provide the counter, so that the actual counting value of the counter can be conveniently and directly converted into the number of waiting periods in the automatic test vector.
Specifically, the configuration registers include trimming value registers, chip function configuration registers, and the like, such as an on-chip clock source frequency trimming register, an on-chip bandgap reference trimming register, a low-power mode configuration register, a start-up mode configuration register, and the like. The output circuit structure shown in fig. 5 is provided between part of the configuration registers and the output configuration signals.
The configuration register is usually initialized during the chip starting stage by using FLASH data or a pin value of the chip so that the chip is in a desired working state, and the register value is defaulted to be an output value of a configuration signal. By adding the configuration copy register and the configuration selection register, convenience is provided for the subsequent testing of the configuration values.
For example, in the trimming value test of a chip to be tested, the simplest method is to test each trimming value of the chip to be tested. The output circuit can quickly perform the adjustment value traversal test to obtain the optimal adjustment value without frequently changing the adjustment value in the FLASH module, and can write all the optimal adjustment values into the FLASH module at one time after all the adjustment value tests are completed. In the test of the start mode of the chip to be tested, the circuit design of the system test board can be simplified through the output circuit structure, namely, the start mode configuration pins of the chip to be tested are simply connected to the switch, and the test control chip on the system test board can change the configuration value of the start mode in the chip to be tested on line through the JTAG interface, so that the system test is facilitated to realize automatic test of various start modes.
In an alternative implementation manner of this embodiment, the configuration register includes a special configuration register, that is, a FLASH mode configuration register, and a configuration signal output by the register is a flash_mode, and through the configuration signal, a FLASH pin inside the chip can be led out to the outside of the chip in a multiplexing manner.
Referring to fig. 6, the FLASH mode configuration register realizes flexible switching of FLASH operation modes through connection of GPIO, FLASH control module, multiplexer (MUX) and on-chip FLASH memory. When the flash_mode signal is high, the FLASH is in a burning mode, a FLASH pin switches a control path to an external pin through a multiplexer, and the FLASH is directly controlled by automatic test equipment to realize operations such as erasing, burning, reading and the like. The design simplifies the FLASH mode switching process, and simultaneously ensures the flexibility and safety of the normal operation and test of the chip.
Referring to fig. 7, in an alternative implementation of the present embodiment, the method for testing the chip function includes three stages of testing procedure.
In the first test program phase, the external reset release is used as a starting point of the chip to be tested and the automatic test equipment in a synchronous state in the phase, and the chip to be tested and the automatic test equipment always operate in the synchronous state in the phase. When the chip to be tested is started, the common part codes in the test program are started to run, the codes in the stage are mainly a starting code, an initializing code and a function test item selecting code, and the selected test information is sourced from a general register in the test control module. And, the present stage code should prohibit modification in the whole test program development after the first functional test item has been developed and after the automated test equipment has been debugged and passed, because the present stage code modification affects the execution process of all functional test items. The test program is usually developed in an incremental form, when the code of the functional test item 1 is developed and is debugged and passed in the automated test equipment, if the code of the stage is modified due to the requirement of the functional test item 2, the modification also affects the developed automated test item 1, so that the functional test item 1 cannot be retested and passed in the automated test equipment, and thus needs to be debugged again. This stage should therefore only retain the code necessary for the functional implementation.
In the second test program stage, the present stage is a chip function test stage. Typically, the functional test items of the chip can be divided into a plurality of functional test items according to various functional modules in the chip, the similar functional modules correspond to one functional test item, some functional test items can be further divided into a plurality of subtest items according to test requirements, for example, the subtest items can be tests of each functional module or tests of different subtasks of the functional module, and the functional tests of the same functional module under different parameter configurations, the selection information and the parameter configuration information of the subtest items can be derived from a general register in a test control module, in addition, part of the functional test items can be divided into a plurality of subtest stages, for example, the subtest items and the subtest stages can correspond to one adjustment value test in the ergodic test of the chip adjustment value to be tested, and the subtest items and the subtest stages are different in the test process, and the subtest items are one-time output test results after the test is finished, and each subtest stage needs to output test results, so that the subtest items and the subtest stages are equivalent in practice if the subtest stage length is 1.
In the function test process, according to whether the chip to be tested and the automatic test equipment always keep synchronous or not, the synchronous function test and the asynchronous function test can be divided into the following steps:
In synchronous functional testing, a synchronous state is always maintained between the chip to be tested and the automated test equipment, because the reset and clock required for functional testing are all directly provided by the automated test equipment, and the chip input to be tested is controlled by the automated test vector and maintains the synchronous state, the output of the chip to be tested and the expected value of the automated test vector can be kept synchronous and aligned on each clock cycle expectation during the test. The test process is generally that an automatic test device provides input to a chip to be tested according to an automatic test vector, and simultaneously compares an expected output value of the automatic test vector with an actual output value of the chip to be tested, and judges whether the functional test passes or not according to a comparison result. Wherein the test is performed at each clock cycle level.
In asynchronous functional testing, a synchronous state cannot be always maintained between a chip to be tested and an automated test equipment, which is generally because clocks required for functional testing are not all directly provided by the automated test equipment, for example, an internal PLL is used for clock doubling during functional testing of a processor performance type, a physical layer provides an independent clock source for a controller during USB testing, and the like, so that synchronization and alignment cannot be maintained on each clock between the output of the chip to be tested and an automated test vector during functional testing. The asynchronous functional test process generally provides an automatic test device with a required input to a chip to be tested according to an automatic test vector, and after the chip to be tested completes a functional test (commonly used for testing functions and/or performances of an internal module of the chip) or completes a test (commonly used for testing functions and/or performances of a complex interface module of the chip) with a tested chip, the test result is output to the automatic test device. Optionally, when synchronous test cannot be used in the partial chip function test and asynchronous function test must be used, the counter inside the test control module is used for conveniently calculating the waiting time required between the starting point of the asynchronous test and the output of the test result, so that the debugging of the time point of the test result query by the automatic test equipment is convenient.
In the third test program stage, the stage is that the automatic test equipment collects the functional test result information of the chip to be tested. The acquisition of the synchronous function test result is convenient, because the automatic test equipment can compare the expected output of the automatic test vector and the actual output of the chip to be tested on a cycle-by-cycle basis in the test process, and automatically record the comparison result, whether the comparison result is completely consistent or not can be directly recorded in the test diary as the function test result, and meanwhile, the test program can write the test result information into the general register in the test control module, if the adjustment value is required to be written into the general register in the ergodic test, and then the automatic test equipment reads out the general register data through the JTAG interface to be recorded in the test diary, thereby facilitating the statistical analysis in the future.
In some asynchronous function tests, the test program can output the test result and then output the test completion mark through the GPIO after the test is completed, and the automatic test equipment can detect the test completion mark in a circulating way and collect the test result after detecting the test completion mark. The foregoing method cannot be adopted in some asynchronous functional tests because the automatic test equipment is required to judge and jump the output completion flag in the cyclic inquiry, and when such operations are performed, the automatic test equipment needs to spend additional time to process, and when the operations including judgment and jump are performed, the speed of the automatic test equipment for executing the automatic test vector may be changed, and further the external clock period provided by the automatic test equipment to the chip to be tested may also be changed, if the asynchronous functional test involves using the PLL inside the chip and the external clock provided by the automatic test equipment with the reference clock source, the PLL is extremely likely to be unlocked, and thus the asynchronous functional test fails, so in such asynchronous functional test, the method of cyclically inquiring the test completion flag cannot be adopted, that is, by using the counter function of the test control module in the actual test, the waiting time may be quickly adjusted, so that the automatic test equipment can correctly detect the test completion flag and read the output of the asynchronous test result of the chip, and the waiting time test method is shown in fig. 8.
The test program takes a starting code, an initializing code, a test function selection code and a code library as common part codes, and functional test items are divided by a functional module, and can be further divided into sub-test items or sub-test stages according to test requirements, and the common part codes are forbidden to be modified after the first functional test item is developed and debugged on automatic test equipment. The test program structure is beneficial to the collaborative development of multiple persons, and each test item is kept relatively independent in the development process, so that the independent development of multiple persons or the integration of the existing function test items are facilitated, and the function between each module in the chip to be tested can be invoked through a common code library in the development process of the function test items, so that the code quantity and time of the development of the test program are reduced, and the development efficiency of the test program is effectively improved.
In an alternative implementation manner of the embodiment, after the chip to be tested is controlled to test according to the automatic test vector, the method further comprises the steps of controlling the count value of the counter in the test control module to be initialized to 0 and activating the counter to start counting at the starting point of the asynchronous function test, controlling the counter to stop counting and storing the actual calculated value of the counter in the FLASH module when the test result of the asynchronous function test is output, reading the actual count value in the FLASH module, calculating the actual count value to obtain a final count value, and taking the final count value as the waiting time required from the starting point of the asynchronous function test to the output of the test result. Wherein the final count value is the actual count value multiplied by the count clock period.
Specifically, this embodiment accurately records the actual waiting time required from the start of the asynchronous test to the output of the test result by the counter. The actual count value is stored in the FLASH module, so that after the automatic test equipment is set high through the flash_mode, the actual count value in the FLASH is read out and recorded in the test diary together with the final count value, and the subsequent statistical analysis is facilitated. Meanwhile, after the asynchronous function test is finished, the actual count values can be directly read from the FLASH by the automatic test equipment through a flash_mode setting method, the waiting time (final count value) required from the starting point of the asynchronous test to the output of the test result can be conveniently obtained through the actual count values and the count clock frequency, and the waiting period number in the automatic test item vector used in the asynchronous function test item is adjusted according to the waiting time.
In an optional implementation manner of this embodiment, after controlling the chip to be tested to perform a test and outputting a test result, the method further includes:
detecting whether the chip to be tested passes the test of the currently selected functional test item according to the test result;
if the selected chip to be tested does not pass the test of the currently selected functional test item, outputting a test result of disqualification of the test of the chip to be tested;
if the chip to be tested passes the test of the currently selected functional test items, detecting whether all the functional test items are tested;
If all the functional test items are tested and pass, outputting a test result of qualified test of the chip to be tested;
and if the function test items which are not tested are present, returning and executing the step of controlling the chip to be tested to be in the power-on reset state and the external reset state at the same time in the power-on initial stage so as to test the next function test item.
Specifically, the operation flow in the embodiment realizes the accurate determination of the functionality and the qualification state of the chip to be tested, and simultaneously designs a reasonable test flow backtracking mechanism to ensure that all test items are covered and the output of the test result is clear and visual. The design is particularly suitable for chip production test, verification test of chip design optimization and the like.
In order to further explain the technical problems and related principles that can be solved by the method for testing a chip function provided by the embodiment of the present application, the following description will be made about the differences between the chip of the related art and the chip to be tested of the embodiment of the present application:
Referring to the related art chip to be tested shown in fig. 9, when the original design of the reset aspect and the clock aspect of the chip to be tested does not meet the requirement of the synchronous test method of the automatic test equipment, the test_mode signal needs to be matched with an additional circuit to meet the requirements of the two aspects. The concrete explanation is as follows:
In the aspect of resetting, the reason that the synchronous test requirement of the automatic test equipment cannot be met is that the system resetting cannot be directly driven and controlled by the automatic test equipment completely.
Because it contains a reset extension module, the system reset active time continues to be extended after the external reset is detected to be effective and released. The chip to be tested is designed for various reasons, for example, no matter how long the effective time of the external reset signal is, the effective time of the reset system after the reset extension treatment is not less than 20ms, the design ensures that all circuits of the chip to be tested can be reset correctly, however, the reset extension module is realized to use a counter to carry out reset delay, the counting clock is carried out by adopting an internal clock source, and the clock source and the automatic test equipment are in an asynchronous state, which can cause the following problems (refer to fig. 10):
Without loss of generality, after the external reset at the time T1 is released, the system reset can be released at the time T2 after a theoretical delay of 3 periods, however, because unavoidable deviation exists between an external clock and an internal clock, the system reset can be actually released at the time T3, and the dislocation can affect all subsequent testing stages. If the automatic test equipment knows that a certain GPIO of the chip to be tested should output a high level at the time T4 according to the automatic test vector, the GPIO actually outputs the high level at the time T5 due to the influence of the system reset release delay, and the automatic test equipment detects that the GPIO at the time T4 does not output the high level, the failure of the function test can be caused.
In the aspect of clocks, the reason that the synchronous test requirement of the automatic test equipment cannot be met is that the system clock is not directly driven and controlled by the automatic test equipment.
Because the system clock adopts the internal clock by default, the possible reason for the design is that the chip to be tested is mainly oriented to the cost sensitive and/or miniaturized market, in some user application scenarios, the application requirements of the chip to be tested can be met by using the internal clock as the system clock, and no external clock is needed, so that the area of the circuit board and the number of circuit components are reduced, but the requirement of synchronous test of the automatic test equipment cannot be met, as shown in fig. 11:
After the system reset is released, the processor starts to execute the test program. In the initialization stage of the test program, the system clock can be switched to an external clock to establish the synchronous state of the automatic test equipment and the chip to be tested, however, between the time of releasing the system reset from T2 and the time of switching the system clock to the external clock T3, the system clock is an internal clock, and the deviation between the external clock and the internal clock can finally lead to that a certain GPIO of the chip to be tested at the time of T4 should output a high level, the GPIO actually outputs a high level at the time of T5, and the automatic test equipment detects that the GPIO at the time of T4 does not output a high level, so that the failure of the functional test can be caused.
In summary, it can be seen that the chip to be tested in the related art cannot meet the requirements of the reset aspect and the clock aspect, and therefore cannot meet the requirements of the synchronous test method of the automatic equipment.
Referring to fig. 12, in the embodiment of the present application, the original reset and clock circuit structure of the chip to be tested is modified by using the test_mode signal to meet the following design objectives:
In the resetting aspect, when the chip to be tested is in an external resetting state, a test_mode signal is set high through a JTAG interface, so that the logic of an internal resetting circuit of the chip to be tested can be changed and is directly driven and controlled by external resetting through an external resetting pin of the chip.
In the clock aspect, when the chip to be tested is in an external reset state, a test_mode signal is set high through a JTAG interface, so that the logic of an internal clock circuit of the chip to be tested can be changed and directly driven by an external clock through an external clock pin of the chip, the external clock can be freely transmitted in a clock circuit, and then the bus clock of the test control module is also in an open state.
Here, in conjunction with fig. 3, after the test_mode signal is set high through the JTAG interface in the configuration stage of the test control module, the system reset and the system clock are switched to the external reset and the external clock, and the synchronization is maintained completely. Furthermore, the external clock, external reset and input are directly provided by the automatic test equipment according to the automatic test vector, so that the whole chip to be tested is completely synchronous with the automatic test equipment and the automatic test vector.
Therefore, the test control module aims at enabling the functional circuit to meet the requirement of the synchronous test method of the automatic test equipment in the chip design stage (using test_mode signals), and can effectively solve the problems that the original reset and clock circuit cannot meet the requirement of the synchronous test method of the automatic test equipment.
Fig. 13 shows an automated test equipment provided by an embodiment of the present invention, the automated test equipment including:
the first control module 1301 is configured to control the chip to be tested to be in a power-on reset state and an external reset state at the same time in an initial stage of power-on;
The configuration module 1302 is configured to perform test related configuration on the test control module through a JTAG interface of the chip to be tested and control the chip to be tested and the automated test equipment to establish a synchronous state when the chip to be tested releases the power-on reset signal and ends the power-on reset state;
The second control module 1303 is configured to release an external reset signal of the chip to be tested and execute a functional test preparation operation when the external reset state is ended;
And the test module 1304 is used for controlling the chip to be tested to test and outputting a test result according to the selected functional test items, wherein the functional test items comprise synchronous functional test or asynchronous functional test.
According to the automatic test equipment, based on the fact that the test control module (belonging to the testability design of the inside of the chip) is added in the chip design stage, the automatic test equipment can directly provide external reset and external clock for the chip to be tested according to the automatic test vector to establish the synchronous state of the test control module and the external clock, so that the chip function test can meet the requirements of the synchronous test method of the automatic test equipment, and the automatic test advantages of good universality, high maturity and good reliability of the automatic test equipment are combined, the alternating current parameters and direct current parameters of the chip to be tested can be measured, error injection test is easy to perform, and the like, so that various function tests can be rapidly realized on the automatic test equipment, and the degree of automation, the test efficiency and the stability of the function test are effectively improved. In addition, asynchronous function test can be performed according to actual test requirements.
Fig. 14 shows an electronic device provided by an embodiment of the present invention, which may be used to implement the method for testing the chip function in any of the foregoing embodiments. The electronic device includes:
Memory 1401, processor 1402, bus 1403, and a computer program stored in memory 1401 and executable on processor 1402, memory 1401 and processor 1402 being connected by bus 1403. When the processor 1402 executes the computer program, the test method of the chip function in the foregoing embodiment is implemented. Wherein the number of processors may be one or more.
The memory 1401 may be a high-speed random access memory or a nonvolatile memory such as a disk memory. The memory 1401 is used for storing executable program codes, and the processor 1402 is coupled to the memory 1401.
Further, the embodiment of the present application also provides a computer readable storage medium, which may be provided in the electronic device in each of the above embodiments, and the computer readable storage medium may be a memory.
The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the test method of the chip function in the foregoing embodiment. Further, the computer-readable medium may be any medium capable of storing a program code, such as a usb (universal serial bus), a removable hard disk, a Read-Only Memory (ROM), a RAM, a magnetic disk, or an optical disk.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module.
It should be noted that, for the sake of simplicity of description, the foregoing method embodiments are all expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present application. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily all required for the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
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