CN115658512A

CN115658512A - Debugging system of general processor

Info

Publication number: CN115658512A
Application number: CN202211333971.9A
Authority: CN
Inventors: 陈进宇; 杨露
Original assignee: Cetc Shentai Information Technology Co ltd
Current assignee: Cetc Shentai Information Technology Co ltd
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2023-01-31

Abstract

The invention relates to a debugging system of a general processor, which comprises a DTM module and a DM module, wherein the DTM module comprises an internal register, a TAP control module and a cdc always-connecting module; the internal registers are divided into an IR register and a DR register, the DTM module is used for reading and writing DMI-ACCESS, IDCODE, DTMCS and BYPASS data registers from the DTM through a JTAG interface according to the value of an IR instruction register, and the DTM module can carry out data information interaction with an upper computer through the JTAG interface and can also carry out data communication with the DM module through a DMI bus protocol. Compare with traditional treater debug system, this debug system can reuse jtag hardware test interface, can provide jtag interface access core state, can debug bare computer processor, and this debug system can expand the trace function to the core assembly line moreover.

Description

Debugging system of general processor

Technical Field

The present invention relates to a debugging system for a processor, and more particularly, to a debugging system for a general-purpose processor having an autonomous instruction set.

Background

It is essential for a processor to provide debug capabilities for software programs running thereon. A general processor debugging system is mainly designed around an interactive debugging function, and realizes that debugger software (GDB, openOCD) can directly obtain control right for a processor through a JTAG interface, so that the debugger can be debugged in an interactive mode.

For a general processor of an independent instruction set in China, the conventional debugging system needs a special debugging bus and a special simulator for the processor, wherein the debugging efficiency of the general processor is low, and the problem of inconvenience in use is brought.

Disclosure of Invention

In order to solve the technical problem, the debugging system of the general processor comprises a DTM module and a DM module, wherein the DTM module comprises an internal register, a TAP control module and a cdc always-connecting module; the internal register is divided into an IR register and a DR register, the DTM module is used for reading and writing DMI-ACCESS, IDCODE, DTMCS and BYPASS data registers from the DTM through a JTAG interface according to the value of the IR instruction register, and the DTM module interacts with the DM module through a data bus according to a DMI interface protocol;

the TAP control module can select a DR register to update a target register according to the instruction content of JTAG IR, and if the IR is DMIACCESS, the state opportunity initiates a DMI protocol request to the DM module according to DMIACCESS field;

the cdc always-connecting module is used for connecting JTAG and DM clocks, and is used for slowly shooting one beat; and the DM module provides debugging control of the platform, can access a memory, a GPR (general purpose register) and a CSR (read Only memory) register by using an abstract command, accesses the memory by using a system bus, and accesses the CSR and the memory by using a Programbuffer instruction.

In an embodiment of the present invention, the length of the IR register in the DTM module is 5 bits, the value of the IR register determines which DR register is to be accessed, and when the TAP controller is reset, the value of IR is default to 5' b00001, that is, the IDCODE register is selected.

In one embodiment of the invention, the TAP control module integrated state machine has two branches, one is an IR branch and the other is a DR branch;

in the Capture-IR state, a specific 5-bit logic sequence is loaded into the instruction register, where the last two bits must be "01"; then entering into a Shift-IR state, and in the Shift-IR state, a specific instruction can be sent to the instruction register by the driving of TCK;

in the Capture-DR state, the DTM captures the value of the data register, and then enters the Shift-DR state from the Capture-DR; in the Shift-DR state, driven by TCK, a new bit of data can be serially input into the data register through TDI on the rising edge of each clock cycle, while the data register can serially output a previously captured bit of data through TDO on the falling edge of each clock cycle.

In an embodiment of the present invention, the interface protocol between the DMI protocol DTM and the DM is an interface protocol, where the DMI is included in the DTM, and the DM module can be accessed according to the DMI protocol DTM.

In one embodiment of the present invention, the DM module comprises a DM _ CSR sub-module, a DM _ SBA sub-module, and a DM _ MEM sub-module; the DM _ CSR submodule is a control module and reads and writes a DM register according to a request command of the DTM; one end of the DM _ CSR is connected with the DMI module and is used for receiving and analyzing the signal sent by the DTM or returning the signal to the DTM, and the other end of the DM _ CSR is connected with the DM _ SBA sub-module and the DM _ MEM sub-module to realize the control of the two modules.

In one embodiment of the invention, the DM _ SBA sub-module implements data interaction with a MASTER interface of the kernel through an AXI bus, and the DM _ MEM sub-module implements data interaction with a SLAVE interface of the kernel through the AXI bus.

Compared with the prior art, the technical scheme of the invention has the following advantages: the debugging system can enable the general processor to carry out online debugging through the JTAG connector, and can finish GDB basic debugging commands, thereby reducing the complexity of a user debugging program and improving the efficiency and the convenience of the debugging program of the general processor to a greater extent; meanwhile, the kernel debugging mode state can be accurately recorded, and a user can also add a user-defined user code into the ProgramBuffer; and can be matched with upper software to directly read the states of the memory and the peripheral equipment through the Bus Access module.

Drawings

In order that the present disclosure may be more readily and clearly understood, reference will now be made in detail to the present disclosure, examples of which are illustrated in the accompanying drawings.

FIG. 1 is an overall frame diagram of the DTM of the present invention;

FIG. 2 is a diagram of the TAP state machine of the present invention;

FIG. 3 is a DMI state machine according to the present invention;

FIG. 4 is a flow chart of the DM instruction execution according to the present invention;

FIG. 5 is a flow chart illustrating the DM instruction execution state transition according to the present invention;

FIG. 6 is the DM exiting debug mode operation of the present invention;

fig. 7 is a state transition diagram for the DM exiting the debug mode according to the present invention.

Detailed Description

As shown in fig. 1, the present embodiment provides a debugging system of a general-purpose processor, including a DTM module and a DM module, wherein the DTM module includes an internal register, a TAP control module and a cdc always interfacing module; the internal register is divided into an IR register and a DR register, the DTM module is used for reading and writing DMI-ACCESS, IDCODE, DTMCS and BYPASS data registers from the DTM through a JTAG interface according to the value of the IR instruction register, and the DTM module interacts with the DM module through a data bus according to a DMI interface protocol.

Therein comprise

DTM module

1) The DTM internal register is divided into an IR register and a DR register, the length of the IR register in the DTM module is 5 bits, the value of the IR register determines which DR register is to be accessed, and when the TAP controller is reset, the value of the IR is default to 5' b00001, namely the IDCODE register is selected. The register (DR register) of the DTM module defines the following DR data register specification table:

Address	Name	Description
			0x00	BYPASS	JTAG recommends this encoding
0x01	IDCODE	JTAG recommends this encoding
			0x10	DTM Control and Status(dtmcs)	For Debugging
0x11	Debug Module Interface Access(dmi)	For Debugging
			0x12	Reserved(BYPASS)	Reserved for future debugging
0x13	Reserved(BYPASS)	Reserved for future debugging
			0x14	Reserved(BYPASS)	Reserved for future debugging
0x15	Reserved(BYPASS)	Reserved for future debugging
			0x16	Reserved(BYPASS)	Reserved for future debugging
0x17	Reserved(BYPASS)	Reserved for future debugging
			0x1f	BYPASS	JTAG requires this encoding

2) The TAP is a TAP state machine controller, and selects the DR register and updates the DR register according to the instruction content of the JTAG IR. The TAP state machine has two branches, one being an Instruction Register (IR) branch and the other being a Data Register (DR) branch.

As in the TAP state machine diagram of fig. 2, 0 or 1 on the arrow indicates the level of the TMS signal. JTAG samples TMS signal and TDI signal at the rising edge of each TCK signal to determine whether the state of the state machine changes, and outputs TDO signal at the falling edge of each TCK signal. It can be seen that no matter which state the TAP is currently in, the TAP must return to the Test-Logic-Reset state as long as TMS remains high for 5 TCK clocks.

The TAP state machine has two main branches, one being the Instruction Register (IR) branch and the other being the Data Register (DR) branch.

In the Capture-IR state, a specific 5-bit logic sequence is loaded into the instruction register (the last two bits must be "01"); then, the Shift-IR state is entered, and in the Shift-IR state, a specific instruction can be sent to the instruction register by driving the TCK. Each instruction will determine an associated data register. Then from Shift-IR- > Exit1-IR- > Update-IR. In the Update-IR state, the instruction just entered into the instruction register will be used to Update the instruction register. And finally, entering a Run-Test-Idle state, enabling the instruction to take effect, and completing the access to the instruction register.

In the Capture-DR state, the DTM captures the values of the data registers. And then entering the Shift-DR state from the Capture-DR. In the Shift-DR state, driven by TCK, a new bit of data can be serially input into the data register through TDI on the rising edge of each clock cycle, while the data register can serially output a previously captured bit of data through TDO on the falling edge of each clock cycle. After the clock period which is the same as the length of the data register, the input of a new signal and the output of captured data can be completed. And then enters into Update-DR state through Exit1-DR state. Op-specified operations begin to be executed by DTM in Update-DR state. And finally, returning to a Run-Test-Idle state, and completing the access to the data register.

3) DMI is an interface protocol between the DTM and the DM, the DMI is contained in the DTM, and the DM module can be accessed according to the DMI protocol DTM.

To ACCESS the DM first, as shown in fig. 3, the value of the IR instruction register must be DMI-ACCESS, and the values of the respective instructions of the IR register are shown in the following table:

instructions	Format
		BYPASS0	5’h0
IDCODE	5’h1
		DTMCSR	5’h10
DMIACCESS	5’h11
		BYPASS1	5’h1f

DM Module

1) DM address space

The address space address allocation of the DM is seen in the following address allocation table:

2) DM register

The memory address mapping register of the DM is seen in the following mapping table:

address	Name (R)
		0x04	Abstract Data 0(data0)
0x0f	Abstract Data 11(data11)
		0x10	Debug Module Control(dmcontrol)
0x11	Debug Module Status(dmstatus)
		0x12	Hart Info(hartinfo)
0x16	Abstract Control and Status(abstracts)
		0x17	Abstract Command(command)
0x18	Abstract Command Autoexec(abstractauto)
		0x20	Program Buffer 0(progbuf0)
0x2f	Program Buffer 15(progbuf15)
		0x38	System Bus Access Control and Status(sbcs)
0x39	System Bus Address 31:0(sbaddress0)
		0x3a	System Bus Address 63:32(sbaddress1)
0x3c	System Bus Data 31:0(sbdata0)
		0x3d	System Bus Data 63:32(sbdata1)

3) DM structure and working principle

The DM debugging module comprises a reset/hash/resume controller module, a Program Buffer module, a Data Buffer module, a Flags Buffer module and a Bus Access module. The reset/hash/resume controller module is used for controlling kernel reset, entering a debugging mode, exiting the debugging mode and the like. The Program Buffer module stores a small section of user-defined code, the Flags Buffer module stores a status bit for marking the working state of the DM, and the Bus Access module is an interface for directly reading and writing the DM with the memory.

The DM has three operating states: halt, resume, expcotion. hash is that the DM enters the debugging mode, resume is that the DM exits the debugging mode, and expcadeion is that the DM enters the exception.

halted

When the upper computer sends a hash request to the DM module, the DM module analyzes the hash instruction to the kernel (an interrupt mode), the kernel PC pointer jumps to 0x800, and the kernel enters a debugging processing program.

resume

After the upper computer sends a resume request to the DM module, the state machine enters a resume state under a proper condition and is set at a resume position 1. The rom loop program executes to go/resume decision, jumps to the resume handler because resume is 1, writes the resume bit, and clears resume (resuming indicates that the resume software handler has not completed) the next beat when resume requests are pulled low.

exception

When DM is abnormal, setting an Exception register as 1, jumping to a debugging entrance, and jumping to an abnormal processing program entrance address by a debugging program according to an abnormal position.

4) Workflow of DM

Fig. 4 shows the operation procedure of executing the command after the DM enters the debug mode from the non-debug mode.

The flow chart of the state transition of the corresponding DM from debug mode to execute instructions is shown in fig. 5 below. The state converter has three states idle, go, cmdexesting. Idle is in Idle state after DM enters debugging mode, go informs kernel to prepare to execute command state after receiving command effective request, and Cmdexecuting is waiting kernel to execute command completion state. After the kernel finishes executing the command, the DM enters the Idle state again and waits for the next command to arrive.

The details of condition 1, condition 2, and condition 3 in fig. 5 are shown in the following table:

and the operation process of the DM exiting the debug mode is shown in fig. 6.

The transition flow of the corresponding DM out of the debug mode is as follows in fig. 7. The state transition machine has two states idle, resume. Idle is the DM in Idle state during debugging, and Resume exits the debug mode state for DM.

The details of

conditions

1 and 2 in FIG. 7 are shown in the following table:

it should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Various other modifications and alterations will occur to those skilled in the art upon reading the foregoing description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims

1. A debugging system of a general processor comprises a DTM module and a DM module, and is characterized in that the DTM module comprises an internal register, a TAP control module and a cdc always-connecting module; the internal register is divided into an IR register and a DR register, the DTM module is used for reading and writing DMI-ACCESS, IDCODE, DTMCS and BYPASS data registers from the DTM through a JTAG interface according to the value of the IR instruction register, and the DTM module interacts with the DM module through a data bus according to a DMI interface protocol;

the cdc always-connecting module is used for connecting JTAG and DM clocks, and is used for slowly shooting one beat; and the DM module provides debugging control of the platform, can access a memory, a GPR (general purpose processor) and a CSR (common memory reference) register by using an abstract command, can access the memory by using a system bus, and can access the CSR and the memory by using a Program buffer instruction.

2. The debugging system of a general-purpose processor according to claim 1, wherein: the length of an IR register in the DTM module is 5 bits, the value of the IR register determines which DR register is to be accessed, and when the TAP controller is reset, the value of the IR is 5' b00001 by default, namely the IDCODE register is selected.

3. The debugging system of claim 1, wherein: the TAP control module integrated state machine has two branches, one is IR branch, and the other is DR branch;

in the Capture-IR state, a specific 5-bit logic sequence is loaded into the instruction register, where the last two bits must be "01"; then entering a Shift-IR state, and in the Shift-IR state, a specific instruction can be sent to the instruction register through the driving of the TCK;

in the Capture-DR state, the DTM captures the value of the data register, and then enters the Shift-DR state from Capture-DR; in the Shift-DR state, driven by TCK, a new bit of data can be serially input into the data register through TDI on the rising edge of each clock cycle, while the data register can serially output a previously captured bit of data through TDO on the falling edge of each clock cycle.

4. The debugging system of claim 1, wherein: and the DMI protocol is contained in the DTM, and the DM module can be accessed according to the DMI protocol DTM.

5. The debugging system of claim 1, wherein: the DM module comprises a DM _ CSR sub-module, a DM _ SBA sub-module and a DM _ MEM sub-module; the DM _ CSR sub-module is a control module and reads and writes a DM register according to a request command of the DTM; one end of the DM _ CSR is connected with the DMI module and is used for receiving and analyzing the signal sent by the DTM or returning the signal to the DTM, and the other end of the DM _ CSR is connected with the DM _ SBA sub-module and the DM _ MEM sub-module to realize the control of the two modules.

6. The debugging system of claim 5, wherein: the DM _ SBA sub module realizes data interaction with a MASTER interface of the kernel through an AXI bus, and the DM _ MEM sub module realizes data interaction with a SLAVE interface of the kernel through the AXI bus.