CN109787603B - Low-conduction flatness analog switch - Google Patents
Low-conduction flatness analog switch Download PDFInfo
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Abstract
The application provides a low-conduction flatness analog switch, which comprises a basic switch module and a current detection module. The basic switch module comprises an NMOS tube N1 which is used for receiving an audio signal and outputting the audio signal in a conducting state. The current detection module is used for scaling the load current of the NMOS tube N1 according to a preset proportion to obtain a compensation current, and inputting the compensation current into the NMOS tube N1. The injection of the compensation current can improve the gate voltage of the NMOS tube N1, further reduce the on-resistance and reduce the on-resistance of the NMOS tube N1 in the process of increasing the load current.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuits, and more particularly to a low-pass analog switch.
Background
Currently, in a mobile phone or some audio circuits, there are analog switches that isolate and conduct audio signals, and these analog switches are usually implemented by PMOS or NMOS. For audio signals, if the on-resistance of the analog switch changes with the change of the audio signal when the audio signal is transmitted, a certain influence is generated on the quality of the output audio signal, so that the on-resistance is an important index of the analog switch. The influence is mainly reflected in the aspect of THD (Total harmonic distortion ), multiple harmonics can occur in the frequency spectrum of the output signal due to the change of the on-resistance of the analog switch, and in general, the larger the on-resistance of the analog switch is, the larger the harmonic component is, which may cause that the quality of the audio signal cannot meet the application requirement of some HIFI (High-Fidelity) sound quality.
Therefore, how to keep the on-resistance of the analog switch unchanged or to make the on-resistance change as small as possible when the input audio signal changes is a challenging and urgent problem to be solved.
Disclosure of Invention
The application provides a low-conduction-flatness analog switch, which aims at keeping the on resistance of the analog switch unchanged or reducing the change as much as possible when an input audio signal changes.
In order to achieve the above object, the present application provides the following technical solutions:
a low on flatness analog switch, comprising:
a basic switch module and a current detection module;
the basic switch module comprises an NMOS tube N1, which is used for receiving an audio signal and outputting the audio signal in a conducting state;
the current detection module is configured to scale the load current of the NMOS transistor N1 according to a preset ratio, obtain a compensation current, and input the compensation current into the NMOS transistor N1.
Optionally, the current detection module includes:
NMOS tube N0, operational amplifier OP3, PMOS tube P5, PMOS tube P6, NMOS tube N4, NMOS tube N5;
the drain electrode of the NMOS tube N0 is connected with the drain electrode of the NMOS tube N1; the grid electrode of the NMOS tube N0 is connected with the grid electrode of the NMOS tube N1; the reverse input end of the operational amplifier OP3 is connected with the source electrode of the NMOS tube N1; the drain electrode of the PMOS tube P5 is connected with the grid electrode of the NMOS tube N1 and is used for inputting the compensation current to the grid electrode of the NMOS tube N1;
the source electrode of the NMOS tube N0 is respectively connected with the positive input end of the operational amplifier OP3 and the drain electrode of the NMOS tube N4, the output end of the operational amplifier OP3 is respectively connected with the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N5, and the source electrode of the NMOS tube N4 and the source electrode of the NMOS tube N5 are respectively grounded; the source electrode of the NMOS tube N5 is respectively connected with the grid electrode of the PMOS tube P6, the drain electrode of the PMOS tube P6 and the grid electrode of the PMOS tube P5, and the source electrode of the PMOS tube P6 is connected with the source electrode of the PMOS tube P5 and is connected with the power supply voltage VDD.
Optionally, the gate lengths of the NMOS transistor N0 and the NMOS transistor N1 are the same, and the width ratio of the NMOS transistor N1 to the NMOS transistor N0 is N.
Optionally, the sizes of the NMOS transistor N4 and the NMOS transistor N5 are the same, and the sizes of the PMOS transistor P5 and the PMOS transistor P6 are the same.
Optionally, the basic switch module further includes:
the first current generation module is used for generating a current IA in direct proportion to the reference signal so as to generate a grid voltage for starting the NMOS tube N1.
Optionally, the first current generation module includes:
the operational amplifier OP2, the PMOS tube P3, the PMOS tube P4, the NMOS tube N3 and the resistor R3;
the source electrode of the PMOS tube P3 is connected with the source electrode of the PMOS tube P4 and is connected with the power supply voltage VDD; the grid of PMOS pipe P3 with PMOS pipe P4's grid links to each other, PMOS pipe P3's grid with PMOS pipe P4's the public end respectively with PMOS pipe P4's drain electrode and NMOS pipe N3's drain electrode links to each other, NMOS pipe N3's grid with operational amplifier OP 2's output links to each other, NMOS pipe N3's source respectively with operational amplifier OP 2's reverse input end and resistance R3's first end links to each other, resistance R3's second ground connection.
Optionally, the basic switch module further includes:
the second current generating module is configured to generate a current IB in direct proportion to the input signal VIN, where the current IB is used for inputting the gate of the NMOS transistor N1.
Optionally, the second current generation module includes:
the operational amplifier OP1, the NMOS tube N2, the PMOS tube P1, the PMOS tube P2 and the resistor R1;
the source electrode of the PMOS tube P2 is connected with the source electrode of the PMOS tube P1 and is connected with the power supply voltage VDD; the grid of PMOS pipe P2 with PMOS pipe P1's grid links to each other, PMOS pipe P2's grid with PMOS pipe P1's the public end respectively with PMOS pipe P1's drain electrode and NMOS pipe N2's drain electrode links to each other, NMOS pipe N2's grid with operational amplifier OP 1's output links to each other, NMOS pipe N2's source respectively with operational amplifier OP 1's reverse input end and resistance R1's first end links to each other, resistance R1's second ground connection.
Optionally, the basic switch module further includes:
a resistor R2;
the grid electrode of the NMOS tube N1 is respectively connected with the first end of the resistor R2, the drain electrode of the PMOS tube P2 and the drain electrode of the PMOS tube P3, and the second end of the resistor R2 is grounded.
Alternatively to this, the method may comprise,
the PMOS tube P1 and the PMOS tube P2 are equal in size, the PMOS tube P3 and the PMOS tube P4 are equal in size, and the resistor R1 and the resistor R2 are equal in resistance.
The low-conduction flatness analog switch comprises a basic switch module and a current detection module. The basic switch module comprises an NMOS tube N1 which is used for receiving an audio signal and outputting the audio signal in a conducting state. The current detection module is used for scaling the load current of the NMOS tube N1 according to a preset proportion to obtain a compensation current, and inputting the compensation current into the NMOS tube N1. The injection of the compensation current can improve the gate voltage of the NMOS tube N1, further reduce the on-resistance and reduce the on-resistance of the NMOS tube N1 in the process of increasing the load current.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of an overall circuit of a low-turn-on flatness analog switch according to an embodiment of the present disclosure;
FIG. 2 is a schematic circuit diagram of a basic switch module disclosed in an embodiment of the present application;
FIG. 3 is an overall circuit diagram of a low-turn-on flatness analog switch according to an embodiment of the present disclosure;
fig. 4 is a diagram of simulation results of the low-conduction-flatness analog switch provided in the present application and a conventional analog switch.
Detailed Description
The application provides a low conduction flatness analog switch, is applied to the scene of the application demand that requires high assurance tone quality, under the condition of certain load resistance, analog switch's input signal VIN range changes, then the corresponding change of electric current in the switch tube also takes place, and then leads to the voltage drop of switch tube source drain to change, and then has changed the actual on-resistance of switch tube.
The purpose of the present application is: when the input audio signal changes, how to keep the on-resistance of the analog switch unchanged or change as small as possible.
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
As shown in fig. 1, an embodiment of the present application provides a low-conduction flatness analog switch, including: a basic switch module 11 and a current detection module 12, wherein the basic switch module 11 has a specific structure as shown in fig. 2, and the basic switch module 11 includes: a first current generation module 21, a second current generation module 22, and a conduction module 23, wherein:
the first current generation module 21 includes: operational amplifier OP2, PMOS pipe P3, PMOS pipe P4, NMOS pipe N3, resistance R3. The source of the PMOS transistor P3 is connected to the source of the PMOS transistor P4 and to the power supply voltage VDD. The grid of the PMOS tube P3 is connected with the grid of the PMOS tube P4, the common end of the grid of the PMOS tube P3 and the grid of the PMOS tube P4 is respectively connected with the drain of the PMOS tube P4 and the drain of the NMOS tube N3, the grid of the NMOS tube N3 is connected with the output end of the operational amplifier OP2, the source of the NMOS tube N3 is respectively connected with the reverse input end of the operational amplifier OP2 and the first end of the resistor R3, and the second end of the resistor R3 is grounded.
The first current generation module 21 is used for generating a current IA proportional to the reference signal VREF so as to generate a basic gate voltage V for turning on the NMOS transistor N1 refgate 。
The second current generation module 22 includes an operational amplifier OP1, an NMOS transistor N2, a PMOS transistor P1, a PMOS transistor P2, and a resistor R1. The source of the PMOS transistor P2 is connected to the source of the PMOS transistor P1 and to the power supply voltage VDD. The grid of the PMOS tube P2 is connected with the grid of the PMOS tube P1, the common end of the grid of the PMOS tube P2 and the grid of the PMOS tube P1 is respectively connected with the drain of the PMOS tube P1 and the drain of the NMOS tube N2, the grid of the NMOS tube N2 is connected with the output end of the operational amplifier OP1, the source of the NMOS tube N2 is respectively connected with the reverse input end of the operational amplifier OP1 and the first end of the resistor R1, and the second end of the resistor R1 is grounded.
The second current generation module 22 is used for generating a current IB proportional to the input signal VIN to generate a gate voltage V of the compensation NMOS transistor N1 in 。
The conduction module 23 includes an NMOS transistor N1 and a resistor R2. The gate of the NMOS transistor N1 is connected to the first end of the resistor R2, the drain of the PMOS transistor P2, and the drain of the PMOS transistor P3, respectively, and the second end of the resistor R2 is grounded.
The conduction module 23 is used for inputting the current IA and the current IB to the resistor R2 to enable the gate-source voltage V of the NMOS transistor N1 gs As the input signal VIN changes.
As shown in fig. 2, the drain of the NMOS transistor N1 and the forward input end of the operational amplifier OP1 are the signal input end of the basic switch module 11, and are used for receiving the input signal VIN, the source of the NMOS transistor N1 is the signal output end of the basic switch module 11, and is used for outputting the output signal VOUT meeting the high-fidelity sound quality, the forward input end of the operational amplifier OP2 is the reference signal input end of the basic switch module 11, and is used for receiving the reference signal VREF, the gate of the NMOS transistor N1 is the current output end of the basic switch module 11, and is connected to the current detection end of the current detection module 12, and the gate of the NMOS transistor N1 is the current input end of the basic switch module 11, and is connected to the current feedback end of the current detection module 12.
It should be noted that the basic switch module 11 is used in NMThe grid electrode of the OS tube N1 generates a grid electrode voltage V gate The gate voltage V gate With the variation of the input signal VIN, a constant gate-source voltage V is generated in the NMOS transistor N1 gs 。
In the embodiment of the application, the PMOS tube P1 and the PMOS tube P2 are equal in size, the PMOS tube P3 and the PMOS tube P4 are equal in size, the resistors R1 and R2 are equal in resistance, and then the grid voltage V gate The magnitude of the variation with the input signal VIN is the same. Specifically, the reference signal VREF is used to generate a basic gate voltage V refgate When the input signal VIN is zero, the reference signal VREF generates a basic gate voltage V refgate When the input signals VIN are different, the gate voltage V of the NMOS transistor N1 gate Basic gate voltage V generated at reference signal VREF refgate On the basis of which the gate voltage V generated by the input signal VIN is superimposed in This causes the gate-source voltage Vgs of the NMOS transistor N1 to vary as the input signal VIN varies.
The PMOS transistors P1, P2, P3, P4, R1 and R2 are preferred embodiments, and may be different in other embodiments.
As shown in fig. 3, the specific structure of the current detection module 12 is that the current detection module 12 includes: NMOS tube N0, operational amplifier OP3, PMOS tube P5, PMOS tube P6, NMOS tube N4, NMOS tube N5, wherein the drain electrode of NMOS tube N0 is connected with the drain electrode of NMOS tube N1 in basic switch module 11. The grid electrode of the NMOS tube N0 is used as a current detection end to be connected with the grid electrode of the NMOS tube N1, the source electrode of the NMOS tube N0 is respectively connected with the positive input end of the operational amplifier OP3 and the drain electrode of the NMOS tube N4, the output end of the operational amplifier OP3 is respectively connected with the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N5, the negative input end of the operational amplifier OP3 is connected with the source electrode of the NMOS tube N1, and the source electrodes of the NMOS tube N4 and the NMOS tube N5 are respectively grounded. The source electrode of the NMOS tube N5 is respectively connected with the grid electrode of the PMOS tube P6, the drain electrode of the PMOS tube P6 and the grid electrode of the PMOS tube P5, and the source electrode of the PMOS tube P6 is connected with the source electrode of the PMOS tube P5 and the power supply voltage VDD. The drain electrode of the PMOS tube P5 is used as a current feedback end and connected with the grid electrode of the NMOS tube N1.
The current detection module 12 is configured to collect the load current IL in the NMOS tube N1 through the current detection end, scale the load current IL according to a preset proportion, and input the obtained current as a compensation current to the gate of the NMOS tube N1 through the current feedback end, and provide a compensation voltage for the gate of the NMOS tube N1, thereby reducing the on-resistance variation within the same current variation range. The load current IL is a current flowing from the input terminal to the output terminal through the NMOS transistor N1.
It should be noted that, in the embodiment of the present application, the NMOS tube N0 and the NMOS tube N1 are matched NMOS tubes, that is, the gate lengths of the NMOS tube N0 and the NMOS tube N1 are set to be the same, the width ratio of the NMOS tube N1 to the NMOS tube N0 is N, the sizes of the NMOS tube N4 and the NMOS tube N5 are the same, and the sizes of the PMOS tube P5 and the PMOS tube P6 are the same. The operational amplifier OP3, the NMOS tube N4 and the NMOS tube N5 act to enable the voltage of the source electrode of the NMOS tube N0 to be the same as that of the source electrode of the NMOS tube N1, so that the current in the NMOS tube N1 is ensured to be N times that in the NMOS tube N0, finally the PMOS tube P5 injects a current IC into the resistor R2, and the injection of the current IC improves the grid voltage V of the NMOS tube N1 gate And further, the on-resistance is reduced, and the on-resistance of the NMOS tube N1 is reduced in the process of increasing the load current.
In the embodiment of the present application, the on-resistance of the NMOS transistor N1 is set to be about 2.3 ohms, the load resistance RL is 30 ohms, and when the input signal VIN changes between 0.2V and 1V, as shown in fig. 4, fig. 4 is a graph of simulation results of the low-on-flatness simulation switch provided in the present application and the conventional simulation switch, in fig. 4, the abscissa is the input signal VIN, and the ordinate is the on-resistance R ON R for on-resistance of conventional analog switch ON_ORIG The variation value is about 83 milliohms, and the R for the on-resistance of the low-on-flatness analog switch provided by the application ON-NEW As can be seen from FIG. 4, the on-resistance flatness of the low-on-flatness analog switch provided by the present application is greatly reduced compared with that of the conventional analog switch, and therefore, the on-resistance of the low-on-flatness analog switch provided by the present application is greatly reduced compared with that of the conventional analog switch in the same current variation rangeThe anti-change is greatly reduced, and when the input audio signal changes, the on-resistance of the analog switch is kept unchanged or changed as little as possible, so that the application with extremely high requirements on signal transmission, such as audio, can be better dealt with.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A low-turn-on flatness analog switch, comprising:
a basic switch module and a current detection module;
the basic switch module comprises an NMOS tube N1, which is used for receiving an audio signal and outputting the audio signal in a conducting state;
the current detection module is used for scaling the load current of the NMOS tube N1 according to a preset proportion to obtain a compensation current, and inputting the compensation current into the NMOS tube N1;
wherein, the current detection module comprises:
NMOS tube N0, operational amplifier OP3, PMOS tube P5, PMOS tube P6, NMOS tube N4, NMOS tube N5;
the drain electrode of the NMOS tube N0 is connected with the drain electrode of the NMOS tube N1; the grid electrode of the NMOS tube N0 is connected with the grid electrode of the NMOS tube N1; the reverse input end of the operational amplifier OP3 is connected with the source electrode of the NMOS tube N1; the drain electrode of the PMOS tube P5 is connected with the grid electrode of the NMOS tube N1 and is used for inputting the compensation current to the grid electrode of the NMOS tube N1;
the source electrode of the NMOS tube N0 is respectively connected with the positive input end of the operational amplifier OP3 and the drain electrode of the NMOS tube N4, the output end of the operational amplifier OP3 is respectively connected with the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N5, and the source electrode of the NMOS tube N4 and the source electrode of the NMOS tube N5 are respectively grounded; the source electrode of the NMOS tube N5 is respectively connected with the grid electrode of the PMOS tube P6, the drain electrode of the PMOS tube P6 and the grid electrode of the PMOS tube P5, and the source electrode of the PMOS tube P6 is connected with the source electrode of the PMOS tube P5 and is connected with the power supply voltage VDD.
2. The low-turn-on flatness analog switch of claim 1, wherein,
the gate lengths of the NMOS tube N0 and the NMOS tube N1 are the same, and the width ratio of the NMOS tube N1 to the NMOS tube N0 is N.
3. The low-turn-on flatness analog switch of claim 1, wherein,
the NMOS tube N4 and the NMOS tube N5 have the same size, and the PMOS tube P5 and the PMOS tube P6 have the same size.
4. The low-turn-on flatness analog switch of claim 1, wherein the basic switch module further comprises:
the first current generation module is used for generating a current IA in direct proportion to the reference signal so as to generate a grid voltage for starting the NMOS tube N1.
5. The low-turn-on flatness analog switch of claim 4, wherein the first current generating module comprises:
the operational amplifier OP2, the PMOS tube P3, the PMOS tube P4, the NMOS tube N3 and the resistor R3;
the source electrode of the PMOS tube P3 is connected with the source electrode of the PMOS tube P4 and is connected with the power supply voltage VDD; the grid of PMOS pipe P3 with PMOS pipe P4's grid links to each other, PMOS pipe P3's grid with PMOS pipe P4's the public end respectively with PMOS pipe P4's drain electrode and NMOS pipe N3's drain electrode links to each other, NMOS pipe N3's grid with operational amplifier OP 2's output links to each other, NMOS pipe N3's source respectively with operational amplifier OP 2's reverse input end and resistance R3's first end links to each other, resistance R3's second ground connection.
6. The low-turn-on flatness analog switch of claim 5, wherein the basic switch module further comprises:
the second current generating module is configured to generate a current IB in direct proportion to the input signal VIN, where the current IB is used for inputting the gate of the NMOS transistor N1.
7. The low-turn-on flatness analog switch of claim 6, wherein the second current generating module comprises:
the operational amplifier OP1, the NMOS tube N2, the PMOS tube P1, the PMOS tube P2 and the resistor R1;
the source electrode of the PMOS tube P2 is connected with the source electrode of the PMOS tube P1 and is connected with the power supply voltage VDD; the grid of PMOS pipe P2 with PMOS pipe P1's grid links to each other, PMOS pipe P2's grid with PMOS pipe P1's the public end respectively with PMOS pipe P1's drain electrode and NMOS pipe N2's drain electrode links to each other, NMOS pipe N2's grid with operational amplifier OP 1's output links to each other, NMOS pipe N2's source respectively with operational amplifier OP 1's reverse input end and resistance R1's first end links to each other, resistance R1's second ground connection.
8. The low-turn-on flatness analog switch of claim 7, wherein the basic switch module further comprises:
a resistor R2;
the grid electrode of the NMOS tube N1 is respectively connected with the first end of the resistor R2, the drain electrode of the PMOS tube P2 and the drain electrode of the PMOS tube P3, and the second end of the resistor R2 is grounded.
9. The low-turn-on flatness analog switch of claim 8, wherein,
the PMOS tube P1 and the PMOS tube P2 are equal in size, the PMOS tube P3 and the PMOS tube P4 are equal in size, and the resistor R1 and the resistor R2 are equal in resistance.
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| CN201910164082.6A CN109787603B (en) | 2019-03-05 | 2019-03-05 | Low-conduction flatness analog switch |
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| CN104883172A (en) * | 2015-05-26 | 2015-09-02 | 周玲 | Analog switch circuit structure |
| CN107786190A (en) * | 2017-11-09 | 2018-03-09 | 中电科技集团重庆声光电有限公司 | A kind of low on-resistance flatness analog switch with leakage current technology for eliminating |
| CN108512536A (en) * | 2018-07-10 | 2018-09-07 | 上海艾为电子技术股份有限公司 | A kind of analog switch with constant conduction resistance |
| CN109245752A (en) * | 2018-10-22 | 2019-01-18 | 上海艾为电子技术股份有限公司 | A kind of adjustment circuit and analog switch |
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2019
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883172A (en) * | 2015-05-26 | 2015-09-02 | 周玲 | Analog switch circuit structure |
| CN107786190A (en) * | 2017-11-09 | 2018-03-09 | 中电科技集团重庆声光电有限公司 | A kind of low on-resistance flatness analog switch with leakage current technology for eliminating |
| CN108512536A (en) * | 2018-07-10 | 2018-09-07 | 上海艾为电子技术股份有限公司 | A kind of analog switch with constant conduction resistance |
| CN109245752A (en) * | 2018-10-22 | 2019-01-18 | 上海艾为电子技术股份有限公司 | A kind of adjustment circuit and analog switch |
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