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CN109495078B - Reference voltage generating circuit and switching power supply - Google Patents

Reference voltage generating circuit and switching power supply Download PDF

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Publication number
CN109495078B
CN109495078B CN201910031836.0A CN201910031836A CN109495078B CN 109495078 B CN109495078 B CN 109495078B CN 201910031836 A CN201910031836 A CN 201910031836A CN 109495078 B CN109495078 B CN 109495078B
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China
Prior art keywords
pmos transistor
conversion circuit
output
circuit
input end
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CN201910031836.0A
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Chinese (zh)
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CN109495078A (en
Inventor
张海军
张启帆
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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Priority to CN201910031836.0A priority Critical patent/CN109495078B/en
Publication of CN109495078A publication Critical patent/CN109495078A/en
Priority to PCT/CN2020/071078 priority patent/WO2020147637A1/en
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Publication of CN109495078B publication Critical patent/CN109495078B/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/432—Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/471—Indexing scheme relating to amplifiers the voltage being sensed
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Amplifiers (AREA)

Abstract

The application provides a reference voltage generating circuit and a switching power supply, comprising: the circuit comprises a first conversion circuit, a second conversion circuit, a bias conversion circuit and a summing resistor; according to the application, the sampling circuit samples the potentials of the two output poles of the first operational amplifier of the AB type audio power amplifier or the potentials of the two output poles of the AB type audio power amplifier, and the reference voltage changes along with the potential changes of the two output poles of the first operational amplifier of the AB type audio power amplifier or the potentials of the two output poles of the AB type audio power amplifier through the summing resistor, the input conversion circuit and the bias conversion circuit, so that the output voltage of the switching power supply changes along with the potential changes of the two output poles of the first operational amplifier of the AB type audio power amplifier or the potentials of the two output poles of the AB type audio power amplifier, thereby reducing the conduction loss on a power tube of a power level and improving the efficiency of a system.

Description

Reference voltage generating circuit and switching power supply
Technical Field
The present application relates to the field of switching power supplies, and in particular, to a reference voltage generating circuit and a switching power supply.
Background
In recent years, with the rapid development of portable electronic products, the requirements of the portable electronic products for the sound quality of speakers thereof are also gradually increasing. The class AB audio power amplifier is widely applied to portable electronic products due to the advantages of good linearity, good sound quality, simple design structure and the like.
Because the switching power supply has the advantages of high working efficiency, small heat generation and the like, the power supply of the output stage of the AB type audio power amplifier is usually provided by the switching power supply.
However, when the output signal of the class AB audio power amplifier is changed, such as reduced, the voltage drop on the PMOS power tube of the output electrode is increased and the consumed power is increased because the output voltage value provided by the switching power supply is unchanged; when the output signal of the AB type audio power amplifier is increased, the voltage division on the NMOS power tube of the output electrode is increased, and the consumed power is increased, so that larger power waste is caused on the power level of the AB type audio power amplifier, and the efficiency of the AB type audio power amplifier is lower.
Disclosure of Invention
Therefore, the embodiment of the application provides a reference voltage generating circuit and a switching power supply to solve the problems of larger power consumption and low efficiency of an AB-class audio power amplifier.
In order to achieve the above object, the embodiment of the present application provides the following technical solutions:
the first aspect of the application discloses a reference voltage generating circuit, which is characterized in that the reference voltage generating circuit is used for providing reference voltage for a switching power supply of an output stage of an AB-type audio power amplifier; the reference voltage generation circuit includes: the device comprises a sampling circuit, an input conversion circuit, a bias conversion circuit and a summation module; wherein:
the first input end and the second input end of the sampling circuit are respectively used as the first input end and the second input end of the reference voltage generating circuit, respectively receive potential sampling values of an output stage VOP1 and an output stage VON1 of a first operational amplifier in the AB type audio power amplifier, or respectively receive potential sampling values of the output stage VOP and the output stage VON of the AB type audio power amplifier;
the input end of the bias conversion circuit is used as a third input end of the reference voltage generation circuit and is connected with a fixed bias voltage;
the first output end of the sampling circuit is connected with the first input end of the input conversion circuit; the second output end of the sampling circuit is connected with the second input end of the input conversion circuit;
the output end of the input conversion circuit, the output end of the bias conversion circuit and the input end of the summation module are all connected, and the output end of the summation module is used as the output end of the reference voltage generation circuit.
Optionally, the input conversion circuit includes: a first conversion circuit and a second conversion circuit; wherein:
the input end of the first conversion circuit is used as the first input end of the input conversion circuit, and the potential sampling value of the output stage VOP1 or the output stage VOP is received;
the input end of the second conversion circuit is used as a second input end of the input conversion circuit, and receives the output stage VON1 or the potential sampling value of the output stage VON;
the output end of the first conversion circuit is connected with the output end of the second conversion circuit, and the connection point is used as the output end of the input conversion circuit.
Optionally, the first conversion circuit includes: a first comparator, a first NMOS transistor, a first resistor, a first PMOS transistor, and a second PMOS transistor; wherein:
the non-inverting input end of the first comparator is used as the input end of the first conversion circuit; the inverting input end of the first comparator is connected with the source electrode of the first NMOS transistor, and the connecting point is connected with one end of the first resistor; the other end of the first resistor is grounded;
the output end of the first comparator is connected with the grid electrode of the first NMOS transistor;
the grid electrode of the first PMOS transistor is connected with the drain electrode of the first PMOS transistor, and the connection point of the grid electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor;
the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with a power supply;
the grid electrode of the second PMOS transistor is connected with the grid electrode of the first PMOS transistor; the drain of the second PMOS transistor serves as the output of the first switching circuit.
Optionally, the second conversion circuit includes: a second comparator, a second NMOS transistor, a second resistor, a third PMOS transistor, and a fourth PMOS transistor; wherein:
the non-inverting input end of the second comparator is used as the input end of the second conversion circuit; the inverting input end of the second comparator is connected with the source electrode of the second NMOS transistor, and the connection point is connected with one end of the second resistor; the other end of the second resistor is grounded;
the output end of the second comparator is connected with the grid electrode of the second NMOS transistor;
the grid electrode of the third PMOS transistor is connected with the drain electrode of the third PMOS transistor, and the connection point of the third PMOS transistor is connected with the drain electrode of the second NMOS transistor;
the source electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected with a power supply;
the grid electrode of the fourth PMOS transistor is connected with the grid electrode of the third PMOS transistor; the drain of the fourth PMOS transistor serves as the output terminal of the second conversion circuit.
Optionally, the bias conversion circuit includes: a third comparator, a third NMOS transistor, a third resistor, a fifth PMOS transistor, and a sixth PMOS transistor; wherein:
the non-inverting input end of the third comparator is used as the input end of the bias conversion circuit; the inverting input end of the third comparator is connected with the source electrode of the third NMOS transistor, and the connecting point is connected with one end of the third resistor; the other end of the third resistor is grounded;
the output end of the third comparator is connected with the grid electrode of the third NOMS transistor;
the grid electrode of the fifth PMOS transistor is connected with the drain electrode of the fifth PMOS transistor, and the connection point of the fifth PMOS transistor is connected with the drain electrode of the third NOMS transistor;
the source electrode of the fifth PMOS transistor and the source electrode of the sixth PMOS transistor are connected with a power supply;
the grid electrode of the sixth PMOS transistor is connected with the grid electrode of the fifth PMOS transistor; the drain of the sixth PMOS transistor serves as the output of the bias switching circuit.
Optionally, the summing module includes a summing resistor, wherein: one end of the summing resistor is used as an input end of the summing module and an output end of the summing module, and the other end of the summing resistor is grounded.
A second aspect of the application discloses a switching power supply for providing a supply voltage to an output stage of a class AB audio power amplifier, comprising: a main circuit, and a reference voltage generating circuit as claimed in any one of claims 1 to 6; wherein:
the reference voltage supply end of the main circuit is connected with the output end of the reference voltage generation circuit; the input end of the main circuit is used as the input end of the switching power supply; the output end of the main circuit is used as the output end of the switching power supply;
the main circuit is any one of BUCK topology, BOOST topology and BUCK_BOOST topology.
Optionally, the BOOST topology includes:
the non-inverting input end is used as an error amplifier of the control end of the BOOST topology, and the inverting input end of the error amplifier receives a feedback voltage signal;
a pulse width modulation comparator with a positive input end connected with the output end of the error amplifier; the negative input end of the pulse width modulation comparator receives a slope compensation voltage signal;
the input end of the switching tube driving unit is connected with the output end of the pulse width modulation comparator, the first output end of the switching tube driving unit is connected with the control end of the first power tube, and the second output end of the switching tube driving unit is connected with the control end of the second power tube;
the second end of the first power tube and the second end of the second power tube are connected with one end of the inductor;
the other end of the inductor is used as an input end of the BOOST topology;
the first end of the first power tube is used as an output end of the BOOST topology; the first end of the second power tube is grounded.
Optionally, the first power tube is a PMOS power tube; the second power tube is an NMOS power tube.
Optionally, the first ends of the first power tube and the second power tube are sources, the second ends of the first power tube and the second power tube are drains, and the control ends of the first power tube and the second power tube are gates.
Compared with the prior art, the sampling circuit samples the potentials of the two output poles of the first operational amplifier of the AB-type audio power amplifier or the potentials of the two output poles of the AB-type audio power amplifier; the input conversion circuit is used for converting and summing the potentials acquired by the two input ends of the acquisition circuit to obtain an input current signal, and the bias conversion circuit is used for converting the fixed bias voltage to obtain a bias current signal; then the summation module sums the input current signal and the bias current signal and converts the summed signal into a reference voltage signal; the reference voltage signal can be changed along with the potential change of the two output poles of the first operational amplifier of the AB type audio power amplifier or the two output poles of the AB type audio power amplifier, and the output voltage of the switching power supply is further changed along with the potential change of the two output poles of the first operational amplifier of the AB type audio power amplifier or the two output poles of the AB type audio power amplifier, so that the conduction loss on a power tube of a power level is reduced, and the efficiency of a system is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a reference voltage generating circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of an input conversion circuit 200 in a reference voltage generating circuit according to another embodiment of the present application;
fig. 3 is a schematic diagram of a first conversion circuit 210 in a reference voltage generating circuit according to another embodiment of the present application;
fig. 4 is a schematic diagram of a second conversion circuit 220 in a reference voltage generating circuit according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a bias conversion circuit 300 in a reference voltage generation circuit according to another embodiment of the present application;
fig. 6 is a schematic diagram of a switching power supply according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In order to solve the problems of larger power consumption and low efficiency of the class AB audio power amplifier, an embodiment of the present application provides a reference voltage generating circuit, as shown in fig. 1, the specific structure includes: sampling circuit 100, input conversion circuit 200, bias conversion circuit 300, and summing module 400; wherein:
the first input terminal and the second input terminal of the sampling circuit 100 are respectively used as the first input terminal and the second input terminal of the reference voltage generating circuit, and respectively receive the sampling value of the electric potential of the output stage VOP1 and the output stage VON1 in the first operational amplifier in the class AB audio power amplifier, or respectively receive the sampling value of the electric potential of the output stage VOP and the output stage VON of the class AB audio power amplifier.
The input end of the bias conversion circuit 300 is used as the third input end of the reference voltage generation circuit, and is connected with a fixed bias voltage.
A first output terminal of the sampling circuit 100 is connected to a first input terminal of the input conversion circuit 200; a second output of the sampling circuit 100 is connected to a second input of the input conversion circuit 200.
The output end of the input conversion circuit 200, the output end of the bias conversion circuit 300 and the input end of the summation module 400 are all connected, and the output end of the summation module 400 serves as the output end of the reference voltage generation circuit.
Optionally, the summing module 400 comprises a summing resistor Rt, wherein: one end of the summing resistor Rt serves as both an input terminal of the summing module 400 and an output terminal of the summing module 400, and the other end of the summing resistor Rt is grounded.
It should be noted that, the present embodiment is only illustrated by the summing resistor, and in practical application, other devices may be implemented, such as an adder, which is not limited herein, so long as other implementations that can achieve the same purpose as the summing resistor Rt are within the scope of the present application.
The specific working principle is as follows:
the first input terminal and the second input terminal of the sampling circuit 100 respectively receive the sampled values of the electric potentials of the output stage VOP1 and the output stage VON1 of the first operational amplifier in the class AB audio power amplifier, or respectively sample the sampled values of the electric potentials of the output stage VOP and the output stage VON of the class AB audio power amplifier.
The input conversion circuit 200 converts and sums the sampling values of the potentials received by the two input ends of the sampling circuit 100 to obtain an input current signal V3; the bias conversion circuit 300 converts the fixed bias voltage DV received at its input to a bias current signal V4.
Since the input conversion circuit 200 and the bias conversion circuit 300 are in parallel relation, the current flowing through the summing resistor Rt is the sum of the currents flowing through the input conversion circuit 200 and the bias conversion circuit 300, i.e. the summing resistor Rt adds together the input current signal V3 and the bias current signal V4.
And because the summing resistor Rt has current flowing through it to generate voltage division, that IS, the summing resistor Rt converts the current signal into a voltage signal, and one end of the summing resistor IS the output end of the reference voltage generating circuit, and the other end IS grounded, the potential of the reference voltage signal vref_is output by the reference voltage generating circuit IS the voltage division of the summing resistor Rt.
Compared with the prior art, the sampling circuit samples the potentials of the two output poles of the first operational amplifier of the AB type audio power amplifier or the two output poles of the AB type audio power amplifier, and the reference voltage changes along with the potential changes of the two output poles of the first operational amplifier of the AB type audio power amplifier or the two output poles of the AB type audio power amplifier through the summing resistor, the input conversion circuit and the bias conversion circuit, so that the output voltage of the switching power supply changes along with the potential changes of the two output poles of the first operational amplifier of the AB type audio power amplifier or the two output poles of the AB type audio power amplifier, thereby reducing the conduction loss on a power tube of a power level and improving the efficiency of a system.
Alternatively, as shown in fig. 2, in another embodiment of the present application, an implementation of one of the input conversion circuits 200 includes: a first conversion circuit 210 and a second conversion circuit 220; wherein:
an input terminal of the first conversion circuit 210 is used as a first input terminal of the input conversion circuit 200, and receives the output electrode VOP1 or a sampling value of the potential of the output electrode VOP; an input terminal of the second conversion circuit 220 is used as a second input terminal of the input conversion circuit 200, and receives a sampling value of the potential of the output electrode VON1 or the output electrode VIN.
An output terminal of the first conversion circuit 210 is connected to an output terminal of the second conversion circuit 220, and a connection point is used as an output terminal of the input conversion circuit 200.
The specific working principle is as follows:
the first conversion circuit 210 converts the sampling value of the potential received by the first input end of the input conversion circuit 200 to obtain a first current signal V1; the second conversion circuit 220 converts the sampled value of the potential received at the second input terminal of the input conversion circuit 200 to obtain a second current signal V2.
Further, since the first conversion circuit 210 and the second conversion circuit 220 are connected in parallel, the input conversion circuit 200 sums the first current signal V1 and the second current signal V2 and outputs the input current signal V3.
It should be noted that, in this embodiment, only one specific implementation manner of the first conversion circuit 210 and the second conversion circuit 220 is taken as an example for illustration, and other embodiments are the same as the working principle of this embodiment, and reference may be made to the working principle of this embodiment, which is not repeated here
The other structures and principles are the same as those of the above embodiments, and will not be described in detail here.
Alternatively, as shown in fig. 3, in another embodiment of the present application, an implementation of the first conversion circuit 210 includes: a first comparator 211, a first NMOS transistor M1, a first resistor R1, a first PMOS transistor P1, and a second PMOS transistor P2; wherein:
the non-inverting input terminal of the first comparator 211 serves as the input terminal of the first conversion circuit 210; an inverting input terminal of the first comparator 211 is connected to a source of the first NMOS transistor M1, and a connection point is connected to one end of the first resistor R1; the other end of the first resistor R1 is grounded.
The output terminal of the first comparator 211 is connected to the gate of the first NMOS transistor M1.
The grid electrode of the first PMOS transistor P1 is connected with the drain electrode of the first PMOS transistor P1, and the connection point is connected with the drain electrode of the first NMOS transistor M1; the source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are both connected to the power supply terminal.
The grid electrode of the second PMOS transistor P2 is connected with the grid electrode of the first PMOS transistor; the drain of the second PMOS transistor serves as the output of the first conversion circuit 210.
The specific working principle is as follows:
if the first input terminal of the sampling circuit 100 receives the potential sampling value of the output electrode VOP1, that is, the potential of the non-inverting input terminal of the first comparator 211 is the potential sampling value of the output electrode VOP1, when the potential of the output electrode VOP1 is high, since the inverting input terminal of the first comparator 211 is grounded through the first resistor R1, that is, the potential of the inverting input terminal of the first comparator 211 is 0, the potential of the non-inverting input terminal of the first comparator 211, that is, the potential sampling value of the output electrode VOP1, is greater than the potential of the inverting input terminal of the first comparator 211, so the output terminal of the first comparator 211 outputs the first control signal of high level.
When the grid electrode of the first NMOS transistor M1 receives a high-level first control signal, the first NMOS transistor is turned on; since the gate of the first PMOS transistor P1 is connected to the drain thereof, that is, after the first NMOS transistor M1 is turned on, the electric potential between the gate of the first PMOS transistor P1 and the drain thereof is 0, that is, a low level, the first PMOS transistor P1 is turned on, that is, the first resistor R1, the first NMOS transistor M1, and the first PMOS transistor P1 have a current flowing therethrough.
Since the second PMOS transistor P2 and the first PMOS transistor P1 are connected to form a mirror circuit, when a current flows in the first PMOS transistor P1, a current flows in the second PMOS transistor P2, i.e. the first current signal V1.
It should be noted that the ratio of the current in the second PMOS transistor P2 to the current in the first PMOS transistor P1 is equal to the ratio of the dimensions of the second PMOS transistor P2 to the first PMOS transistor P1, and the ratio therebetween may be determined according to the actual requirement, which is not limited herein.
Further, after the first conversion circuit 210 is turned on, the potential of the inverting input terminal of the first comparator 211 is a divided voltage of the first resistor R1, so that the first conversion circuit 210 can be kept in the on state when the output electrode VOP1 is at the high level, so that it is necessary to ensure that the divided voltage of the first resistor R1 is smaller than the potential of the output electrode VOP1 after the first conversion circuit 210 is turned on.
When the potential of the output electrode VOP1 is at the low level, the first conversion circuit 210 is not turned on.
If the non-inverting input terminal of the first comparator 211 samples the potential of the output electrode VOP, the working principle is basically the same as that described above, and only the voltage division of the first resistor R1 is required to be ensured to be smaller than the potential of the output stage VOP after the first conversion circuit 210 is turned on, which is not described in detail herein.
It should be noted that, the embodiment only provides a specific implementation manner of the first conversion circuit 210, and in practical application, the implementation manner may be implemented by a circuit structure or a chip formed by other discrete devices, so long as other implementation manners capable of implementing the above working principle are all within the protection scope of the present application.
The other structures and principles are the same as those of the above embodiments, and will not be described in detail here.
Alternatively, as shown in fig. 4, in another embodiment of the present application, an implementation of the second conversion circuit 220 includes: a second comparator 221, a second NMOS transistor M2, a second resistor R2, a third PMOS transistor P3, and a fourth PMOS transistor P4; wherein:
the non-inverting input of the second comparator 221 serves as the input of the second conversion circuit 220; an inverting input terminal of the second comparator 221 is connected to a source of the second NMOS transistor M2, and a connection point is connected to one end of the second resistor R2; the other end of the second resistor R2 is grounded.
The output of the second comparator 221 is connected to the gate of the second NMOS transistor M2.
The gate of the third PMOS transistor P3 is connected to the drain thereof, and the connection point is connected to the drain of the second NOMS transistor M2.
The source electrode of the third PMOS transistor P3 and the source electrode of the fourth PMOS transistor P4 are connected with a power supply; the gate of the fourth PMOS transistor P4 is connected to the gate of the third PMOS transistor P3; the drain of the fourth PMOS transistor P4 serves as the output terminal of the second conversion circuit 220.
The operation principle of the second conversion circuit 220 is substantially the same as that of the first conversion circuit 210, and will not be described herein.
The other structures and principles are the same as those of the above embodiments, and will not be described in detail here.
Alternatively, as shown in fig. 5, in another embodiment of the present application, an implementation of the bias conversion circuit 300 includes: a third comparator 310, a third NMOS transistor M3, a third resistor R3, a fifth PMOS transistor P5, and a sixth PMOS transistor P6; wherein:
the non-inverting input of the third comparator 310 serves as the input of the offset conversion circuit 300; an inverting input terminal of the third comparator 310 is connected to a source of the third NMOS transistor M3, and a connection point is connected to one end of the third resistor R3; the other end of the third resistor R3 is grounded.
The output of the third comparator 310 is connected to the gate of the third NMOS transistor M3.
The gate of the fifth PMOS transistor P5 is connected to the drain thereof, and the connection point is connected to the drain of the third NMOS transistor M3.
The source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are both connected to a power supply.
The gate of the sixth PMOS transistor P6 is connected to the gate of the fifth PMOS transistor P5; the drain of the sixth PMOS transistor serves as the output of the bias conversion circuit 300.
The operating principle of the bias conversion circuit 300 is substantially the same as that of the first conversion circuit 210, and will not be described here.
The other structures and principles are the same as those of the above embodiments, and will not be described in detail here.
The application also provides a switching power supply, as shown in fig. 6, which specifically comprises the following components: a main circuit 520 and a reference voltage generating circuit 510 as disclosed in any of the above embodiments, wherein:
the reference voltage control terminal of the main circuit 520 is connected to the output terminal of the reference voltage generating circuit 510; an input of the main circuit 520 is used as an input of the switching power supply; the output of the 520 main circuit serves as the output of the switching power supply.
The main circuit is any one of BUCK topology, BOOST topology and BUCK_BOOST topology.
Alternatively, this embodiment only takes an implementation of the main circuit 520 as an example, namely, a BOOST topology, and other implementations of the main circuit 520 are not specifically described herein, but other implementations of the main circuit 520 are also within the scope of the present application. The specific structure of the BOOST topology, as shown in fig. 6, includes: an error amplifier 521, a pulse width modulation comparator 522, and a switching tube driving unit 523; wherein:
the non-inverting input of error amplifier 521 serves as the reference voltage supply for the BOOST topology; the inverting input of the error amplifier receives the feedback voltage signal.
One end of the fourth resistor R4 is connected with one end of the fifth resistor R5, and the connection point outputs a feedback voltage signal; the other end of the fifth resistor R5 is grounded.
The positive input end of the pulse width modulation comparator 522, the output end of the error amplifier 521, the output end of the clamping module 524 and the output end of the loop compensation capacitor 525 are all connected; the negative input of the pulse width modulation comparator 522 receives the slope compensation voltage signal.
The sampling module 526 is connected to the current production module 527, and the connection point outputs a slope compensation voltage signal.
An input terminal of the switching tube driving unit 523 is connected to an output terminal of the pulse width modulation comparator 522; the first output end HSG of the switch tube driving unit 523 is connected with the control end of the first power tube Mp; the second output terminal LSG of the switching tube driving unit 523 is connected to the control terminal of the second power tube Mn.
The second end of the first power tube Mp, the second end of the second power tube Mn and one end of the inductor L are connected, and the other end of the inductor is used as an input end of the BOOST topology; the first end of the first power tube Mp is used as an output end of the BOOST topology; the first end of the second power tube Mn is grounded.
It should be noted that, the first power tube Mp is a PMOS power tube; the second power tube Mn is an NMOS power tube; and the first ends of the first power tube Mp and the second power tube Mn are sources, the second ends of the first power tube Mp and the second power tube Mn are drains, and the control ends of the first power tube Mp and the second power tube Mn are grids.
The other end of the fourth resistor R4, one end of the capacitor C and one end of the sixth resistor R6 are connected, and the connection point is connected with the first end of the first power tube; the other end of the capacitor C is grounded, and the other end of the sixth resistor R6 is grounded.
The specific working principle is as follows:
when the potential of the reference voltage signal vref_is outputted by the reference voltage generating circuit 510 IS greater than the reference voltage VFB, the error amplifier 521 amplifies the difference between the potential of the reference voltage signal and the reference voltage VFB and outputs the error amplification signal COMP, and the clamping module 524 does not clamp the potential of the error amplification signal COMP because the potential of the reference voltage signal vref_is IS greater than the reference voltage VFB.
Therefore, the potential of the error amplification signal COMP is greater than the slope compensation voltage VSLOPE, so the potential of the driving signal output by the pulse width modulation comparator 522 is at a high level; the input end of the switching tube driving unit 523 receives a high-level driving signal, drives the first power tube Mp to be turned on, and turns off the second power tube Mn.
When the potential of the reference voltage signal vref_is output by the reference voltage generating circuit 510 IS smaller than the reference voltage VFB, the error amplifier 521 amplifies the difference between the reference voltage VFB and the potential of the reference voltage signal and outputs the error amplification signal COMP, and the clamp module 524 clamps the potential of the error amplification signal COMP to a low level since the potential of the reference voltage signal vref_is IS smaller than the reference voltage VFB.
Therefore, the potential of the error amplifier COMP is smaller than the slope compensation voltage VSLOPE, so the potential of the driving signal output by the pulse width modulation comparator 522 is low; the input end of the switching tube driving unit 523 receives the low-level driving signal, closes the first power tube Mp, and turns on the second power tube Mn.
It should be noted that, the present embodiment distinguishes the driving signals only with a high level and a low level, so that the different driving signals control the switching tube driving unit 523 to perform different operations, which is not limited; in practical application, other schemes capable of realizing the working principle are within the protection scope of the application.
It should be further noted that the ratio of the reference voltage VFB to the output voltage VOUT of the BOOST topology, that is, the ratio of the reference voltage VFB to the output voltage VOUT of the switching power supply, is equal to the sum of the resistance of the fifth resistor R5 and the resistance of the fourth resistor R4 and the fifth resistor R5, that is, vfb=vout×r5/(r4+r5), that is, the reference voltage may represent the output voltage VOUT of the switching power supply to some extent.
Further, it is deduced that after the above-mentioned operation, the output voltage VOUT of the switching power supply is closer to the reference voltage, so, when the potential of the reference voltage signal output by the reference voltage generating circuit 510 changes, the output voltage VOUT of the switching power supply also changes, and is closer to the changed reference voltage, that is, the output voltage VOUT of the switching power supply changes along with the potential change of the reference voltage signal output by the reference voltage generating circuit 510.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A reference voltage generation circuit for providing a reference voltage for a switching power supply of a class AB audio power amplifier output stage; the reference voltage generation circuit includes: the device comprises a sampling circuit, an input conversion circuit, a bias conversion circuit and a summation module; wherein:
the first input end and the second input end of the sampling circuit are respectively used as the first input end and the second input end of the reference voltage generating circuit, respectively receive potential sampling values of an output stage VOP1 and an output stage VON1 of a first operational amplifier in the AB type audio power amplifier, or respectively receive potential sampling values of the output stage VOP and the output stage VON of the AB type audio power amplifier;
the input end of the bias conversion circuit is used as a third input end of the reference voltage generation circuit and is connected with a fixed bias voltage;
the first output end of the sampling circuit is connected with the first input end of the input conversion circuit; the second output end of the sampling circuit is connected with the second input end of the input conversion circuit;
the output end of the input conversion circuit, the output end of the bias conversion circuit and the input end of the summation module are all connected, and the output end of the summation module is used as the output end of the reference voltage generation circuit.
2. The reference voltage generating circuit according to claim 1, wherein the input converting circuit comprises: a first conversion circuit and a second conversion circuit; wherein:
the input end of the first conversion circuit is used as the first input end of the input conversion circuit, and the potential sampling value of the output stage VOP1 or the output stage VOP is received;
the input end of the second conversion circuit is used as a second input end of the input conversion circuit, and receives the output stage VON1 or the potential sampling value of the output stage VON;
the output end of the first conversion circuit is connected with the output end of the second conversion circuit, and the connection point is used as the output end of the input conversion circuit.
3. The reference voltage generating circuit according to claim 2, wherein the first conversion circuit includes: a first comparator, a first NMOS transistor, a first resistor, a first PMOS transistor, and a second PMOS transistor; wherein:
the non-inverting input end of the first comparator is used as the input end of the first conversion circuit; the inverting input end of the first comparator is connected with the source electrode of the first NMOS transistor, and the connecting point is connected with one end of the first resistor; the other end of the first resistor is grounded;
the output end of the first comparator is connected with the grid electrode of the first NMOS transistor;
the grid electrode of the first PMOS transistor is connected with the drain electrode of the first PMOS transistor, and the connection point of the grid electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor;
the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with a power supply;
the grid electrode of the second PMOS transistor is connected with the grid electrode of the first PMOS transistor; the drain of the second PMOS transistor serves as the output of the first switching circuit.
4. The reference voltage generating circuit according to claim 2, wherein the second conversion circuit includes: a second comparator, a second NMOS transistor, a second resistor, a third PMOS transistor, and a fourth PMOS transistor; wherein:
the non-inverting input end of the second comparator is used as the input end of the second conversion circuit; the inverting input end of the second comparator is connected with the source electrode of the second NMOS transistor, and the connection point is connected with one end of the second resistor; the other end of the second resistor is grounded;
the output end of the second comparator is connected with the grid electrode of the second NMOS transistor;
the grid electrode of the third PMOS transistor is connected with the drain electrode of the third PMOS transistor, and the connection point of the third PMOS transistor is connected with the drain electrode of the second NMOS transistor;
the source electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected with a power supply;
the grid electrode of the fourth PMOS transistor is connected with the grid electrode of the third PMOS transistor; the drain of the fourth PMOS transistor serves as the output terminal of the second conversion circuit.
5. The reference voltage generating circuit according to claim 1, wherein the bias conversion circuit comprises: a third comparator, a third NMOS transistor, a third resistor, a fifth PMOS transistor, and a sixth PMOS transistor; wherein:
the non-inverting input end of the third comparator is used as the input end of the bias conversion circuit; the inverting input end of the third comparator is connected with the source electrode of the third NMOS transistor, and the connecting point is connected with one end of the third resistor; the other end of the third resistor is grounded;
the output end of the third comparator is connected with the grid electrode of the third NOMS transistor;
the grid electrode of the fifth PMOS transistor is connected with the drain electrode of the fifth PMOS transistor, and the connection point of the fifth PMOS transistor is connected with the drain electrode of the third NOMS transistor;
the source electrode of the fifth PMOS transistor and the source electrode of the sixth PMOS transistor are connected with a power supply;
the grid electrode of the sixth PMOS transistor is connected with the grid electrode of the fifth PMOS transistor; the drain of the sixth PMOS transistor serves as the output of the bias switching circuit.
6. The reference voltage generating circuit of any one of claims 1-5, wherein the summing module comprises a summing resistor, wherein: one end of the summing resistor is used as an input end of the summing module and an output end of the summing module, and the other end of the summing resistor is grounded.
7. A switching power supply for providing a supply voltage to an output stage of a class AB audio power amplifier, comprising: a main circuit, and a reference voltage generating circuit as claimed in any one of claims 1 to 6; wherein:
the reference voltage supply end of the main circuit is connected with the output end of the reference voltage generation circuit; the input end of the main circuit is used as the input end of the switching power supply; the output end of the main circuit is used as the output end of the switching power supply;
the main circuit is any one of BUCK topology, BOOST topology and BUCK_BOOST topology.
8. The switching power supply of claim 7 wherein said BOOST topology comprises:
the non-inverting input end is used as an error amplifier of the control end of the BOOST topology, and the inverting input end of the error amplifier receives a feedback voltage signal;
a pulse width modulation comparator with a positive input end connected with the output end of the error amplifier; the negative input end of the pulse width modulation comparator receives a slope compensation voltage signal;
the input end of the switching tube driving unit is connected with the output end of the pulse width modulation comparator, the first output end of the switching tube driving unit is connected with the control end of the first power tube, and the second output end of the switching tube driving unit is connected with the control end of the second power tube;
the second end of the first power tube and the second end of the second power tube are connected with one end of the inductor;
the other end of the inductor is used as an input end of the BOOST topology;
the first end of the first power tube is used as an output end of the BOOST topology; the first end of the second power tube is grounded.
9. The switching power supply of claim 8 wherein said first power tube is a PMOS power tube; the second power tube is an NMOS power tube.
10. The switching power supply of claim 9, wherein the first ends of the first and second power tubes are sources, the second ends of the first and second power tubes are drains, and the control ends of the first and second power tubes are gates.
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