CN109713033A - LDMOS device and its manufacturing method - Google Patents
LDMOS device and its manufacturing method Download PDFInfo
- Publication number
- CN109713033A CN109713033A CN201811632282.1A CN201811632282A CN109713033A CN 109713033 A CN109713033 A CN 109713033A CN 201811632282 A CN201811632282 A CN 201811632282A CN 109713033 A CN109713033 A CN 109713033A
- Authority
- CN
- China
- Prior art keywords
- silicon dioxide
- drift region
- dioxide layer
- type
- ldmos device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 116
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 57
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims description 30
- VJJVVKGSBWRFNP-UHFFFAOYSA-N [O].[Si](=O)=O Chemical compound [O].[Si](=O)=O VJJVVKGSBWRFNP-UHFFFAOYSA-N 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 3
- 230000014759 maintenance of location Effects 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of LDMOS devices comprising forms first kind trap on a silicon substrate；Surface drift region, drain terminal and the source of Second Type are formed in the transverse direction of first kind trap；Surface drift region is in drain terminal between source, and surface drift region is adjacent with drain terminal, with source interval；Silicon dioxide layer is formed with above surface drift region, surface drift region is formed with silicon dioxide layer with the interval top between source；The silicon dioxide layer of the surface of surface drift region is covered with ONO film layer；ONO film layer and N-type surface drift region are the same as being formed with polysilicon gate in the silicon dioxide layer above the interval between source.The invention also discloses the manufacturing methods of the LDMOS device.The invention can avoid technological fluctuation bring component failure or integrity problems, can accomplish that technique is controllable and has smaller chip area under the premise of meeting high voltage and low on-resistance.
Description
Technical field
The present invention relates to semiconductor technology, in particular to a kind of LDMOS device and its manufacturing method.
Background technique
Lateral double diffusion metal oxide semiconductor (LDMOS) is a kind of MOS device being lightly doped, and is had with CMOS technology
Extraordinary compatibility.Traditional cmos device is usually source and drain symmetrical structure, and LDMOS uses source and drain unsymmetric structure with full
Foot is compared with high voltage and the demand of relatively low conducting resistance.
As shown in Figure 1,300 region of source electrode of LDMOS is equipped with body area 202,300 regions of drain electrode are equipped with drift region 201.Its
In, body area 202 is similar with the well region in traditional CMOS transistor, is mainly used for controlling the threshold voltage of LDMOS；Drift region
201 are mainly used for controlling the pressure-resistant performance of LDMOS, for the pressure resistance for improving LDMOS, the ion implantation dosage of drift region 201 than
The well region implantation dosage of CMOS transistor is much smaller.From device architecture, drift region 201 and body area 202 are usually opposite types
Ion implanting.
In traditional cmos process, usually additionally increases by two light shields and be respectively formed drift region 201 and body area 202, to realize
Higher voltage endurance and lower conducting resistance.
In tradition application, the cost for increasing by two light shields is prohibitively expensive, therefore, occurs more for 201 He of drift region
The research in body area 202 is injected using the trap of CMOS transistor and adjusts ion implanting to reach cmos device preferable with LDMOS device
Balance；As shown in Fig. 2, the body area in 300 region of source electrode of LDMOS is replaced using the trap 205 of CMOS transistor, while drift region
It is replaced using the trap 203 of CMOS transistor, in necessary situation, increases deep trap 204 and obtain most suitable drift region.For source well
205 can also do corresponding adjustment with the spacing of drift region trap 203.
On the other hand, flash memory (Flash Memory) is being moved with the characteristics of its non-volatile (Non-Volatile)
It is widely used in the consumer electronics products such as mobile phone, digital camera and portable system.Embedded Flash storage
Device is even more because its low-cost and high-performance is more and more approved.Wherein, SONOS (Silicon-Oxide-Nitride-
Oxide-Silicon, silicon/silicon dioxide/silicon nitride/silicon dioxide/silicon) type flash memory with its simple process, operation electricity
Force down, the advantages that data reliability is high and is readily integrated into standard CMOS process and be regarded as common floating gate (Floating
Gate) the substitute products of type flash memory.
Typical SONOS structure is to stop oxygen by silicon substrate (S)-tunnel oxide (O)-charge storage layer silicon nitride (N)-
Change layer (O)-polysilicon gate (S) composition.This structure is compiled using the tunnelling of electronics, and the injection in hole is counted
According to erasing.In SONOS, charge is stored in ONO (Oxide-Nitride-Oxide, silicon dioxide/silicon nitride/bis-
Silica) in trapping centre in dielectric layer, thus referred to as electric charge capture device.
Embedded Flash product needs charge pump to provide high voltage and realizes turning for charge during programmed and erased
It moves, the pressure resistance of charge pump usually requires to provide LDMOS device as control；Embedded product uses conventional CMOS device simultaneously
Do the functional logic circuit of core control portions.For conventional LDMOS in the design of embedded product charge pump, it is larger that there are areas
The problems such as conducting resistance is big；Therefore special applications demand is combined, DEMOS (improvement version LDMOS) shown in Fig. 3 is suggested, compares
In traditional LDMOS, source and drain terminal are formed in cmos device trap 206, eliminates drain terminal close to polysilicon 400 in structure
Shallow channel isolation area 101 increases surface drift region 301, reduces conducting resistance.But there are two drawbacks, one for this device
No longer it is autoregistration injection for drain electrode 300, is affected by technological fluctuation；Secondly being 301 region of surface drift region as pressure resistance
Buffer area, it is necessary to reach certain length to reduce the voltage for reaching 400 lower section of grid, breakdown is avoided to fail.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of LDMOS device and its manufacturing methods, are avoided that technological fluctuation
Bring component failure or integrity problem can accomplish that technique is controllable under the premise of meeting high voltage and low on-resistance
And there is smaller chip area.
In order to solve the above technical problems, LDMOS device provided by the invention comprising be formed on silicon substrate 100
One type trap 206；
Surface drift region 301, drain terminal and the source 300 of Second Type are formed in the transverse direction of the first kind trap 206；
Surface drift region 301 is in drain terminal between source 300, and surface drift region 301 is adjacent with drain terminal, between source 300
Every；
Silicon dioxide layer is formed with above surface drift region 301, surface drift region 301 is the same as rectangular on the interval between source
At there is silicon dioxide layer；
The silicon dioxide layer of the surface of surface drift region 301 is covered with ONO film layer 402；
The ONO film layer 402 and N-type surface drift region 301 are the same as shape in the silicon dioxide layer above the interval between source
At there is polysilicon gate.
Preferably, the depth of surface drift region 301 is less than the depth of drain terminal and source 300.
Preferably, being formed with shallow channel isolation area 101 on the outside of drain terminal and source 300.
Preferably, the first kind is p-type, Second Type is N-type.
Preferably, the first kind is N-type, Second Type is p-type.
Preferably, the silicon substrate 100 is P type substrate.
In order to solve the above technical problems, the manufacturing method of the LDMOS device provided by the invention, comprising the following steps:
One, forms bed course silicon dioxide layer 403 on silicon substrate 100；
On silicon substrate 100 described in two, shallow channel isolation area 101 is formed；
Three, the silicon substrate 100 of two neighboring shallow channel isolation area 101 right part, through bed course silicon dioxide layer
403, surface drift region 301 is formed by photoetching and ion implanting, the shallow channel isolation area 101 of surface drift region 301 is shallow；
Entire silicon substrate top formation first kind trap 206 of four, between two neighboring shallow channel isolation area 101, first
The depth of type trap 206 is not less than the depth of shallow channel isolation area 101；
Five, form ONO film layer 402 in bed course silicon dioxide layer 403；
ONO film layer 402 and bed course two of six, on the silicon substrate 100, except 301 surface of removal surface drift region
Silicon oxide layer 403, only the ONO film layer 402 and bed course silicon dioxide layer 403 right above retention surface drift region 301；
Seven, form grid oxygen silicon dioxide layer 401 on silicon substrate 100；
Eight, form polysilicon layer in grid oxygen silicon dioxide layer 401 and ONO film layer 402；
Grid oxygen silicon dioxide layer 401 and polycrystalline on the silicon substrate 100 of the adjacent left side shallow channel isolation area 101 of nine, removal
Silicon layer, and bed course silicon dioxide layer 403 and polysilicon layer on the right side of adjacent on the silicon substrate 100 of shallow channel isolation area 101 are removed,
Form polysilicon gate；
Ten, carry out Second Type heavy doping ion injection at left and right sides of polysilicon gate, form drain terminal and source 300；
11, carry out subsequent process steps.
Preferably, forming shallow channel isolation area 101 by etching fill process in step 2.
Preferably, through bed course silicon dioxide layer 403, forming first kind trap 206 by ion implanting in step 4.
Preferably, forming ONO film layer 402 using furnace process in step 5.
Preferably, the ONO film in step 6, except being removed right above surface drift region 301 by lithography and etching technique
Layer 402 and bed course silicon dioxide layer 403.
Preferably, in step 6, using the ONO except 301 surface of dry method combination wet etching removal surface drift region
Film layer 402 and bed course silicon dioxide layer 403.
Preferably, forming grid oxygen silicon dioxide layer 401 on silicon substrate 100 by cleaning and furnace process in step 7.
Preferably, being formed simultaneously CMOS grid oxygen silicon dioxide layer in step 7.
Preferably, the consistency of thickness of the grid oxygen silicon dioxide layer 401 formed in step 7 and bed course silicon dioxide layer 403.
Preferably, forming polysilicon gate by lithography and etching in step 9.
Preferably, by self-registered technology, Second Type heavy doping is carried out at left and right sides of polysilicon gate in step 10
Ion implanting forms drain terminal and source 300.
Preferably, carrying out the injection of Second Type heavy doping ion at left and right sides of polysilicon gate in step 10 and moving back
Fire process forms drain terminal and source 300.
LDMOS device and its manufacturing method of the invention can be used source and drain autoregistration injection, avoid technological fluctuation bring
Component failure or integrity problem；Meanwhile the ONO that the grid of the LDMOS device and drain terminal pressure resistance pass through introducing embedded flash memory
Structure and obtain enough voltage endurance capabilities, ONO film layer 402 collectively constitutes high voltage region in conjunction with silicon dioxide layer；Surface drift
Area 301 can reduce as far as possible, be conducive to the diminution of device area；In addition pass through silica above surface drift region 301
Layer and ONO structure and grid form field plate effect, can reduce surface field and promote voltage endurance capability, which can be full
Under the premise of sufficient high voltage and low on-resistance, accomplish that technique is controllable and has smaller chip area.
Detailed description of the invention
In order to illustrate more clearly of technical solution of the present invention, the required attached drawing of the present invention is made below simple
It introduces, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ordinary skill people
For member, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is LDMOS device cross-sectional view in the prior art；
Fig. 2 is the LDMOS device sectional view for reducing light shield in the prior art and using；
Fig. 3 is the improvement version LDMOS device sectional view for reducing conducting resistance in the prior art；
Fig. 4 is one embodiment sectional view of LDMOS device of the invention；
Fig. 5 is that one embodiment of LDMOS device manufacturing method of the invention forms bed course silicon dioxide layer and shallow trench isolation
Area's sectional view；
Fig. 6 is that one embodiment of LDMOS device manufacturing method of the invention forms surface drift region sectional view；
Fig. 7 is that one embodiment of LDMOS device manufacturing method of the invention forms first kind trap and ONO film layer sectional view；
Fig. 8 is that one embodiment of LDMOS device manufacturing method of the invention removes part ONO film layer and bed course silicon dioxide layer
Sectional view；
Fig. 9 is that one embodiment of LDMOS device manufacturing method of the invention forms grid oxygen silicon dioxide layer sectional view；
Figure 10 is that one embodiment of LDMOS device manufacturing method of the invention forms polysilicon layer sectional view；
Figure 11 is that one embodiment of LDMOS device manufacturing method of the invention forms polysilicon gate sectional view.
Description of symbols:
100 silicon substrates；101 shallow channel isolation areas；201 drain-drift regions；202 source bodies；203/204 drain well is (same
Cmos device trap)；205 source wells (with cmos device trap)；206CMOS device well；300 source drain implants；The drift of 301 surfaces
Area；400 polysilicon gates；401 grid oxygen silicon dioxide layers；402ONO film layer；403 bed course silicon dioxide layers.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff all other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
Embodiment one
As shown in figure 4, LDMOS device includes the first kind trap 206 being formed on silicon substrate 100；
Surface drift region 301, drain terminal and the source 300 of Second Type are formed in the transverse direction of the first kind trap 206；
Surface drift region 301 is in drain terminal between source 300, and surface drift region 301 is adjacent with drain terminal, between source 300
Every；
Silicon dioxide layer is formed with above surface drift region 301, surface drift region 301 is the same as rectangular on the interval between source
At there is silicon dioxide layer；
The silicon dioxide layer of the surface of surface drift region 301 is covered with ONO film layer 402；
The ONO film layer 402 and N-type surface drift region 301 are the same as shape in the silicon dioxide layer above the interval between source
At there is polysilicon gate 400.
Preferably, the depth of surface drift region 301 is less than the depth of drain terminal and source 300.
Preferably, being formed with shallow channel isolation area 101 on the outside of drain terminal and source 300.
Preferably, silicon substrate 100 is P type substrate.
Preferably, the first kind is p-type, Second Type is N-type.
Preferably, the first kind is N-type, Second Type is p-type.
The LDMOS device of embodiment one, can be used source and drain autoregistration injection, avoid technological fluctuation bring component failure or
Integrity problem；Meanwhile the grid of the LDMOS device is obtained with drain terminal pressure resistance by introducing the ONO structure of embedded flash memory
Enough voltage endurance capabilities, ONO film layer 402 collectively constitute high voltage region in conjunction with silicon dioxide layer；Surface drift region 301 can use up
Possible diminution is conducive to the diminution of device area；In addition pass through silicon dioxide layer and ONO structure above surface drift region 301
Field plate effect is formed with grid, surface field can be reduced and promote voltage endurance capability, which can meet high voltage and low
Under the premise of conducting resistance, accomplish that technique is controllable and has smaller chip area.
Embodiment two
The manufacturing method of the LDMOS device of embodiment one, comprising the following steps:
One, forms bed course silicon dioxide layer 403 on silicon substrate 100；
On silicon substrate 100 described in two, shallow channel isolation area 101 is formed, as shown in Figure 5；
Three, the silicon substrate 100 of two neighboring shallow channel isolation area 101 right part, through bed course silicon dioxide layer
403, surface drift region 301 is formed by photoetching and ion implanting, the shallow channel isolation area 101 of surface drift region 301 is shallow,
As shown in Figure 6；
Entire silicon substrate top formation first kind trap 206 of four, between two neighboring shallow channel isolation area 101, first
The depth of type trap 206 is not less than the depth of shallow channel isolation area 101；
Five, form ONO (silicon dioxide/silicon nitride/silica) film layer 402 in bed course silicon dioxide layer 403, such as scheme
Shown in 7；
ONO film layer 402 and bed course two of six, on the silicon substrate 100, except 301 surface of removal surface drift region
Silicon oxide layer 403, the only ONO film layer 402 and bed course silicon dioxide layer 403 right above retention surface drift region 301, such as Fig. 8 institute
Show；
Seven, form grid oxygen silicon dioxide layer 401 on silicon substrate 100, as shown in Figure 9；
Eight, form polysilicon layer in grid oxygen silicon dioxide layer 401 and ONO film layer 402, as shown in Figure 10；
Grid oxygen silicon dioxide layer 401 and polycrystalline on the silicon substrate 100 of the adjacent left side shallow channel isolation area 101 of nine, removal
Silicon layer, and bed course silicon dioxide layer 403 and polysilicon layer on the right side of adjacent on the silicon substrate 100 of shallow channel isolation area 101 are removed,
Polysilicon gate is formed, as shown in figure 11；
Ten, carry out Second Type heavy doping ion injection at left and right sides of polysilicon gate, form drain terminal and source 300,
As shown in Figure 4；
11, carry out subsequent process steps.
Preferably, forming shallow channel isolation area 101 by etching fill process in step 2.
Preferably, through bed course silicon dioxide layer 403, forming first kind trap 206 by ion implanting in step 4.
Preferably, forming ONO film layer 402 using furnace process in step 5.
Preferably, the ONO film in step 6, except being removed right above surface drift region 301 by lithography and etching technique
Layer 402 and bed course silicon dioxide layer 403.
Preferably, in step 6, using the ONO except 301 surface of dry method combination wet etching removal surface drift region
Film layer 402 and bed course silicon dioxide layer 403.
Preferably, by cleaning and furnace process, forming grid oxygen silicon dioxide layer on silicon substrate 100 in step 7
401。
Preferably, being formed simultaneously CMOS grid oxygen silicon dioxide layer in step 7.
Preferably, the consistency of thickness of the grid oxygen silicon dioxide layer 401 formed in step 7 and bed course silicon dioxide layer 403.
Preferably, forming polysilicon gate by lithography and etching in step 9.
Preferably, by self-registered technology, Second Type heavy doping is carried out at left and right sides of polysilicon gate in step 10
Ion implanting forms drain terminal and source 300.
Preferably, carrying out the injection of Second Type heavy doping ion at left and right sides of polysilicon gate in step 10 and moving back
Fire process forms drain terminal and source 300.
Preferably, the first kind is p-type, Second Type is N-type.
Preferably, the first kind is N-type, Second Type is p-type.
Preferably, the silicon substrate 100 is P type substrate.
The manufacturing method of the NLDMOS device of embodiment two, technology controlling and process is good, and the element layout structure of manufacture is small.
The above is only preferred embodiment of the present application, it is not used to limit the application.Come for those skilled in the art
It says, various changes and changes are possible in this application.Within the spirit and principles of this application, made any modification, equivalent
Replacement, improvement etc., should be included within the scope of protection of this application.
Claims (21)
1. a kind of LDMOS device, which is characterized in that it includes the first kind trap (206) being formed on silicon substrate (100)；
Surface drift region (301), drain terminal and the source of Second Type are formed in the transverse direction of the first kind trap (206)
(300)；
Surface drift region (301) is between the same source of drain terminal (300), and surface drift region (301) are adjacent with drain terminal, same to source
(300) it is spaced；
It is formed with silicon dioxide layer above surface drift region (301), surface drift region (301) are the same as rectangular on the interval between source
At there is silicon dioxide layer；
The silicon dioxide layer of the surface of surface drift region (301) is covered with ONO film layer (402)；
The ONO film layer (402) and N-type surface drift region (301) are the same as shape in the silicon dioxide layer above the interval between source
At there is polysilicon gate.
2. LDMOS device according to claim 1, which is characterized in that
The depth of surface drift region (301) is less than the depth of drain terminal and source (300).
3. LDMOS device according to claim 1, which is characterized in that
Shallow channel isolation area (101) are formed on the outside of drain terminal and source (300).
4. LDMOS device according to claim 1, which is characterized in that
The first kind is p-type, and Second Type is N-type.
5. LDMOS device according to claim 1, which is characterized in that
The first kind is N-type, and Second Type is p-type.
6. LDMOS device according to claim 1, which is characterized in that
The silicon substrate (100) is P type substrate.
7. the manufacturing method of LDMOS device according to claim 3, which comprises the following steps:
One, forms bed course silicon dioxide layer (403) on silicon substrate (100)；
On silicon substrate described in two, (100), formed shallow channel isolation area (101)；
Three, the silicon substrate (100) of two neighboring shallow channel isolation area (101) right part, through bed course silicon dioxide layer
(403), surface drift region (301) are formed by photoetching and ion implanting, surface drift region (301) more described shallow channel isolation area
(101) shallow；
First kind trap (206) are formed at entire silicon substrate top of four, between two neighboring shallow channel isolation area (101), and first
The depth of type trap (206) is not less than the depth of shallow channel isolation area (101)；
Five, form ONO film layer (402) on bed course silicon dioxide layer (403)；
ONO film layer (402) and bed course of six, on the silicon substrate (100), except removal surface drift region (301) surface
Silicon dioxide layer (403), only the ONO film layer (402) and bed course silicon dioxide layer right above retention surface drift region (301)
(403)；
Seven, form grid oxygen silicon dioxide layer (401) on silicon substrate (100)；
Eight, form polysilicon layer in grid oxygen silicon dioxide layer (401) and ONO film layer (402)；
Grid oxygen silicon dioxide layer (401) on the silicon substrate (100) of the adjacent left side shallow channel isolation area (101) of nine, removal and more
Crystal silicon layer, and remove the bed course silicon dioxide layer (403) on the silicon substrate (100) of adjacent right side shallow channel isolation area (101) and
Polysilicon layer forms polysilicon gate；
Ten, carry out Second Type heavy doping ion injection at left and right sides of polysilicon gate, form drain terminal and source (300)；
11, carry out subsequent process steps.
8. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 2, shallow channel isolation area (101) are formed by etching fill process.
9. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 4, through bed course silicon dioxide layer (403), first kind trap (206) are formed by ion implanting.
10. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 5, ONO film layer (402) are formed using furnace process.
11. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 6, by lithography and etching technique removal surface drift region (301) right above except ONO film layer (402) and
Bed course silicon dioxide layer (403).
12. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 6, using the ONO film layer (402) except dry method combination wet etching removal surface drift region (301) surface
And bed course silicon dioxide layer (403).
13. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 7, grid oxygen silicon dioxide layer (401) are formed on silicon substrate (100) by cleaning and furnace process.
14. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 7, it is formed simultaneously CMOS grid oxygen silicon dioxide layer.
15. LDMOS device manufacturing method according to claim 7, which is characterized in that
The consistency of thickness of the grid oxygen silicon dioxide layer (401) and bed course silicon dioxide layer (403) that are formed in step 7.
16. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 9, polysilicon gate is formed by lithography and etching.
17. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 10, by self-registered technology, the injection of Second Type heavy doping ion, shape are carried out at left and right sides of polysilicon gate
At drain terminal and source (300).
18. LDMOS device manufacturing method according to claim 7, which is characterized in that
In step 10, the injection of Second Type heavy doping ion and annealing process are carried out at left and right sides of polysilicon gate, are formed
Drain terminal and source (300).
19. LDMOS device manufacturing method according to claim 7, which is characterized in that
The first kind is p-type, and Second Type is N-type.
20. LDMOS device manufacturing method according to claim 7, which is characterized in that
The first kind is N-type, and Second Type is p-type.
21. LDMOS device manufacturing method according to claim 7, which is characterized in that
The silicon substrate (100) is P type substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811632282.1A CN109713033A (en) | 2018-12-29 | 2018-12-29 | LDMOS device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811632282.1A CN109713033A (en) | 2018-12-29 | 2018-12-29 | LDMOS device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109713033A true CN109713033A (en) | 2019-05-03 |
Family
ID=66258194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811632282.1A Pending CN109713033A (en) | 2018-12-29 | 2018-12-29 | LDMOS device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109713033A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060113592A1 (en) * | 2004-05-03 | 2006-06-01 | Sameer Pendharkar | Robust DEMOS transistors and method for making the same |
| US20080042198A1 (en) * | 2006-08-17 | 2008-02-21 | Chul-Jin Yoon | Demos structure |
| CN103187443A (en) * | 2011-12-30 | 2013-07-03 | 无锡华润上华半导体有限公司 | Lateral double-diffusion metal oxide semiconductor field effect transistor |
| CN107180873A (en) * | 2016-03-14 | 2017-09-19 | 马克西姆综合产品公司 | Ldmos transistor and associated system and method including RESURF layers and step grid |
| CN107275333A (en) * | 2017-06-30 | 2017-10-20 | 上海华虹宏力半导体制造有限公司 | DMOS devices and manufacture method in SONOS non-volatility memorizer techniques |
-
2018
- 2018-12-29 CN CN201811632282.1A patent/CN109713033A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060113592A1 (en) * | 2004-05-03 | 2006-06-01 | Sameer Pendharkar | Robust DEMOS transistors and method for making the same |
| US20080042198A1 (en) * | 2006-08-17 | 2008-02-21 | Chul-Jin Yoon | Demos structure |
| CN103187443A (en) * | 2011-12-30 | 2013-07-03 | 无锡华润上华半导体有限公司 | Lateral double-diffusion metal oxide semiconductor field effect transistor |
| CN107180873A (en) * | 2016-03-14 | 2017-09-19 | 马克西姆综合产品公司 | Ldmos transistor and associated system and method including RESURF layers and step grid |
| CN107275333A (en) * | 2017-06-30 | 2017-10-20 | 上海华虹宏力半导体制造有限公司 | DMOS devices and manufacture method in SONOS non-volatility memorizer techniques |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI462277B (en) | Non-volatile semiconductor memory devices, non-volatile memory serials and non-volatile memory arrays | |
| CN103035650B (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US11532637B2 (en) | Embedded flash memory cell including a tunnel dielectric layer having different thicknesses over a memory region | |
| US9418993B2 (en) | Device and method for a LDMOS design for a FinFET integrated circuit | |
| CN102270663B (en) | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device | |
| KR20120066627A (en) | Super junction trench power mosfet devices fabrication | |
| KR20120094466A (en) | Super junction trench power mosfet devices | |
| KR20030020644A (en) | Flash memory element and manufacturing method | |
| CN1868069A (en) | Recess channel flash architecture for reduced short channel effect | |
| KR20040093404A (en) | A semiconductor device and a method of manufacturing the same | |
| US9412878B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN103632942B (en) | The method of integrated SONOS device and LDMOS device in CMOS technology | |
| CN107527917B (en) | 1.5T depletion type SONOS non-volatile memory and manufacturing method thereof | |
| CN1653621A (en) | Floating Gate Memory Cell with Increased Coupling Ratio | |
| CN1258231C (en) | Dual bit multi-level ballistic MONOS memory, and manufacturing method, programming, and operation process for memory | |
| KR100588051B1 (en) | EPERPOM and EPERPOM manufacturing method | |
| JPH11220044A (en) | Low-voltage eeprom/nvram transistor and manufacture thereof | |
| US6025229A (en) | Method of fabricating split-gate source side injection flash memory array | |
| CN101826527A (en) | Semiconductor device, method of fabricating the same and flash memory device | |
| TWI643253B (en) | Method of fabricating power mosfet | |
| TWI513007B (en) | Memory device and methods for fabricating and operating the same | |
| US7449384B2 (en) | Method of manufacturing flash memory device | |
| CN109713033A (en) | LDMOS device and its manufacturing method | |
| KR101110177B1 (en) | EEPROM Cell and the method for manufacturing EEPROM Cell | |
| US7408219B2 (en) | Nonvolatile semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190503 |