JPH11220044A - Low-voltage eeprom/nvram transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the electron injection efficiency strikingly, by providing the step-difference channel/drain structure, wherein a vertical channel/drain part is added under a floating gate, in the horizontal channel structure. SOLUTION: A transistor 400a has a P-type silicon substrate 401, N+ source diffusion 404, the horizontal channel part of 410, drain diffusion 406, a floating gate 440 which covers both a horizontal channel and a step-difference channel, and a control gate 445. The floating gate is dielectrically separated by a dielectric layer 42, which is the dioxide thermally grown from the surface of a seiconductor substrate. The control gate 445 is capacitively coupled (capacitive coupling) to the control gate 440 through a dielectric film 430. The dielectric film can be any of the thermally grown silicon dioxide or the combination layer of the silicon dioxide and silicon nitride.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and relates to a device structure for improving electron injection efficiency, lowering voltage, shortening writing time, and performing nonvolatile random access memory operation, and a method of manufacturing the same.

[0002]

2. Description of the Prior Art The mechanism of emission of hot electrons through a gate insulating film to a gate is as follows.
A. Phillip (A. Phillips et al.
1975 IEDM Technical Diges
t, P. 39). Since then, the phenomenon has been described by Tac Nin (T. Ning et al. Applied P
physics 1997 Vol 48, P.M. 286) and many more. Prior to confirmation of hot electron emissions, electrically programmable memories (EPROMs) used a memory structure very similar to channel hot electron EPROMs. But it is Flowman. From Bench cow ski (From-Bentchkowsky: P-ch
Annell 1971 ISSCC P.S. 80'a F
uly decoded 2048 bit Ele
ctricany-ProgrammableMOS-
ROM ") and" FAMOS-a New Semico
nector Change Stage De
v1ce ″, (Solid StateElectro
nics, 1974, vol 17, P.N. As shown in 517), the memory cell was programmed using a high electric field avalanche mechanism (avalanche breakdown mechanism).
For the programming of MOSFET EPROM cells, see
Barnes (J. Barnes et al, 1976)
IEDM P.A. 177, "Operation and
Characterization of N-ch
Ann EPROM cell ") and P. Salsbury 1977 ISSCC
P. 186, "High Performance M
OSEPROM using a stack-gat
e cell "). J. Burns is 2
Two basic types of double polysilicon CHEEPR
OM transistors are shown. The stack gate transistor 100a of FIG. 1A and the split gate transistor 100b of FIG. 1B. Both have N + source junction 104, N + drain junction 106,
It has a P-substrate 101, a channel gate insulating film 120, a floating gate (floating gate) 140, a polyoxide 130, and a control gate 145.

[0003] Transistor 100b has a split channel, which is electrically conductive and has a floating gate.
A portion 110 controlled by 40 and a portion 118 connected to it by a control gate 145 are connected. FIG.
900 in B is a passivation layer. For both types of transistors 100a and 100b, programming is performed near the silicon surface and near the drain junction by hot electron injection.

[0004] A numerical model that correctly predicts hot electron emission to a floating gate is described in Cheming Hu, IEDM 197.
9, p. 223 "Lucky-Electron Mo
del of ChannelHotElectron
Emission "). FIG.
General double polysilicon stack gate EPROM
FIG. 2 is a cross-sectional view of the transistor 200, used to explain a lucky model. Transistor is N
MOS transistor with source 204, drain 20
6, a substrate 201, a floating gate 240, and a control gate 245. When the voltage Vcg is applied to the control gate 245, Ccg−fg / (Ccg−fg + Cfg) due to capacitive coupling (capacitive coupling).
The voltage of the floating gate increases according to the capacitance ratio (= caprin ratio (coupling ratio)) of −si). Here, Ccg-fg is the capacitance (capacitance) between the control gate and the floating gate,
fg-si is the capacitance between the floating gate, the channel, and the source / drain. Once the floating gate voltage exceeds the threshold voltage, electrons begin to flow from the source to the drain. 1 from silicon surface
Electrons in the channel close to the surface within 0 nm are accelerated in the horizontal direction by the potential between the drain and source. The electrons gain energy and momentum from the horizontal electric field and reach maximum energy near the drain end 206. Only a fraction of the electrons gain energy above the barrier height of the tunnel insulating film (220). When the energy of the electrons exceeds the height of the barrier of the insulating film, the momentum of the electrons changes upward due to the scattering of acoustic phonons without energy loss, and the electrons are injected into the insulating film 220 when going toward the floating gate. , Floating gate polysilicon 240 may be reached. It has been observed that the likelihood of channel to polysilicon injection is at a level between IE-6 and IE-9. The channel hot electron emission to the floating gate, no matter how small the channel length or junction depth, is, if Vd-Vs is 2.5
It is proposed in this model that there is little if V or less.

[0005]

2. Description of the Related Art The injection rate of channel electrons into a floating gate is too small, which causes problems in various aspects. The problems of channel hot electron injection for EPROM and EEPROM memory operation are:

The possibility that the electrons are turned upward due to phonon scattering is that most of the hot electrons must be produced by drain voltage acceleration. Must be much higher (eg 5
V or more).

[0007] The control voltage must be high (9-1 for the coupling ratio of 0.6 to 0.5).
0V). This is because the help of an electric field is required for the injected electrons to reach the floating gate polysilicon (the floating gate voltage must exceed the drain voltage). When the floating gate voltage is lower than the drain voltage, the electrons injected into the insulating film are pushed back to the channel.

The program time for storing electrons in the floating gate is long. The readout time is on the order of microseconds since the electron injection efficiency is IE-6 or less, compared to the readout time on the order of nanoseconds.

[0009] Since the injection current is too small, it is difficult to control the electron accumulation level in one program cycle because the injection current control depends on both the drain voltage and the control gate voltage.

The need for a high voltage device to decode the control gates in the memory array. The higher the control gate voltage, the thicker the gate insulating film and the longer the channel length. This penalizes the degree of integration and becomes a barrier to scaling technology.

[0011] Because of the high drain voltage, hot electrons with higher energy than necessary are used to damage the oxide crystal lattice and form traps, so that the insulating film is quickly worn out and has poor durability.

Since high voltage is required at the drain and control gate for low injection efficiency, power consumption and drain current are high.

In an electrically erasable programmable read only memory (EEPROM), electrons stored in the floating gate are removed by applying an appropriate voltage to the transistor terminals. E
There are two erasing methods for removing electrons from the floating gate of an EPROM. One is to use double polysilicon EEPROM cells to transfer electrons from the floating gate to the silicon below (ie, source,
(Drain diffusion or substrate) removal method. Another one
One is to use a triple polysilicon EEPROM cell to remove electrons from the floating gate to another third gate.

The method of the double polysilicon cell is described in Samachusa (G. Samechusa et al. 1987).
IEEE Journal of Solid Circ
uits, Vol. SC-22, No. 5, p. 67
6, "0/2 Flash EEPROM using
double polysilicontechno
This double polysilicon cell deformation is described by H. Kumeet a.
l. "Flash-Erase EEPROM cell
l with an Asymmetric Sour
ce and Drain Structure, "T
technical Digest of the IE
EE International Electron
Device Meeting, December
1987, p. 560) and Kinet (VN Kyne)
tt et al. "An In-system Re
programmable 256K CMOS Fl
ashMemory ", Digest of Tech
nickal papers, IEEE Interna
Tional Solid-State Circuit
ts Conference, February 198
8, p. 132).

A typical double polysilicon stack gate EEPROM cell by Kume removes electrons from the floating gate to the silicon below as shown in FIG. 3A. Erasing in the double polysilicon EEPROM transistor 300a is accomplished through the tunnel oxide 320 when the tunnel oxide electric field between the floating gate 340 and the source diffusion junction 304 exceeds the FN tunneling critical electric field of 10 MV / cm. With a normal erase voltage, the tunnel oxide is 10 nm, the diffusion junction is 12 V, the control gate is φV, and the drain voltage is floating. Since this method requires a high voltage at the source junction, the junction is prone to avalanche breakdown. To protect against this breakdown, the source junction is deeper than the drain junction. (The drain junction must be shallow, to create a high electric field at the drain end for hot channel electrons.) This stacked gate cell is the EEPROM cell 10 of FIG. 1A.
0a, but has an asymmetric deep source junction.

It is recorded that the double-poly split gate transistor 100b cannot be used for an application in which the number of times of rewriting of asymmetrical diffusion is large because only one junction is provided.

A triple polysilicon transistor solves this problem. This is because electrons are removed through the third polysilicon instead of the junction. Also, triple polysilicon EEPROM cells solve the deep junction problem for scale-down memory technology. Triple polysilicon devices are described in J. Kupec et al. 1980 IED.
M TechnicalDigest, P.M. 602 "T
ripple Level Polysilicon E
EPROM with Single Transmission
tor per Bit ″).
uoka, H .; Iizuka US PatNo. 4,
531,203 Issued July 23,19
85). A variation of the same cell is Kuo (CK Kuo and SC Tsa).
nUS Pat. No. 4,561,004 issu
ed Dec 24, 1985) and Wu (AT Wu)
et al, 1986 IEDM Technical.
Digest, P .; 584 "Q Novel High
-Speed, 5-V Programming EPR
OM structure with source-
side injection ") and Harari (E. Ha
RariUS Pat, No. 5,198,380is
sued Mar 30, 1993).

All of these triple polysilicon memory cells use one of the polysilicon levels as the erase gate. The erase gate is near the floating gate and is insulated by a thin tunnel die electric. When the proper voltage is applied to all elements of the transistor, charge is removed from the floating gate to the erase gate. FIG. 3B shows an EEPROM transistor 300b that uses a third polysilicon for erasing by Cupec in various triple polysilicon EEPROM cells.

In the transistor 300b, the electrons stored in the floating gate 340 are removed from the side wall of the floating gate to the third polysilicon 350. A common example of voltage applied to each node during erase is 12-15V on triple erase polysilicon for 20nm ONO 325, on control polysilicon second polysilicon 345 and diffusion junction 3
OV is applied to 04 and 306. Since the voltage on the drain during programming is as low as about 5V, triple polysilicon EEPROM transistors do not suffer from avalanche breakdown or junction leakage at the junction. However, triple polysilicon transistors also have problems. The problem is as follows:

Extra polysilicon devotion for erasing is required, and an extra step is necessary for forming triple polysilicon because a dielectric layer (insulating layer) is required for tunnel erasing. This not only complicates the process but also affects the degree of integration of the memory cells.

An extra circuit is required to generate a high voltage for erasing. The block size for erasure must be relatively large in order to minimize the adverse effect of the extra circuit on the degree of integration. Erasing large block sizes reduces the overall life of the memory array because it increases unnecessary program and erase cycles.

[0022]

SUMMARY OF THE INVENTION The present invention relates to an electrically programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM). This broadens the application of the nonvolatile memory.

An electrically programmable read only memory (EEPROM) uses a floating gate conductive gate (not connected) in a field effect transistor structure and uses it as a semiconductor between source and drain regions. Place insulated over the channel on the substrate. The control gate is also provided insulated on the floating gate. The state of the memory is determined by the amount of charge held on the floating gate, which controls the threshold of the transistor. Next, the mechanism of charge accumulation in channel hot electrons (CHE) will be described.

When a voltage is applied to the control gate on the floating gate, the potential of the floating gate increases due to the capacitive coupling from the control gate to the floating gate. Once the floating gate voltage exceeds the threshold voltage, electrons begin to flow from source to drain. The horizontal electric field accelerates the horizontal movement of the electrons in the channel due to the potential difference between the drain and the source. Electrons gain energy and momentum from the field and reach maximum energy at the drain end. When the electron energy exceeds the height of the insulating barrier, the electrons are injected into the insulating film and can reach the floating gate polysilicon if the momentum of the electrons is in the direction of the floating gate. However, this possibility is very small and requires low efficiency and long program time.
Once the electrons are injected and stored in the floating gate, the threshold voltage of the memory increases.

The state of the memory transistor is read by applying voltages on the source, drain and control gate, which is similar to the operation of a normal MOSFET transistor. The amount of current flowing between the source and the drain is affected by the threshold voltage. That is, it depends on the amount of accumulated electrons. The more electrons stored in the floating gate, the higher the threshold voltage and the lower the current. The memory state depends on the current level. The programming time for injecting electrons into the floating gate is very slow compared to the read time for the same memory transistor, since a small amount of channel electrons, typically one millionth, is injected into the floating gate. Therefore, a high drain and control gate voltage to improve the programming time even a little
Used in EPROMs and Flash EEPROMs. The need for this high voltage is a major obstacle to scaling down memory arrays.

It is a primary object of the present invention to provide a new memory cell design and structure to significantly improve electron injection efficiency.

It is another object of the present invention to provide a new memory cell design and structure that allows for reliable programming and erasing from the same drain junction.

Another object of the present invention is to reduce the drain and control gate voltages required for electron injection,
In addition to enabling scaling and high integration of memory cells in the future, it is also necessary to improve the reliability of the memory cells and improve the durability (the number of times of writing and erasing).

Another object of the present invention is to enable target-level electron accumulation with a fast programming time, thereby more effectively combining multi-level / multi-bit applications of single memory transistors in combination with the controllability of electron injection. It is gaining.

It is another object of the present invention to provide a new program reading structure and operation technique for the EPROM function in a single polysilicon cell.

Another object of the present invention is to provide an operation technique for tunneling erasure from a floating gate to a control gate instead of a triple polysilicon EEPROM according to the prior art, instead of a double polysilicon EEPROM cell. Provide a new structure that is possible with

Another object of the present invention is to provide a feature of the function of a nonvolatile RAM of a split gate cell having a new structure, and that when a word line (control gate) is selected, 'φ' (program) is changed. 1, (erase) is to be provided.

It is another object of the present invention to provide a simpler and more controllable manufacturing process for EPROM, flash EEPROM and non-volatile memory applications.

[0034]

SUMMARY OF THE INVENTION The various features achieved by the present invention may be used alone or in any combination. The key features are briefly summarized below:

The problem with prior art channel hot electron injection type EPROMs and EEPROMs has been to provide a stepped channel / drain structure in which a vertical channel / drain portion is added below a floating gate to a horizontal channel structure. Can be solved by This significantly improves the efficiency of electron injection from the channel to the floating gate. This is because the electrons accelerated in the horizontal channel directly enter the vertical portion of the floating gate in the traveling direction. On the contrary, the prior art relied on the indirect method of scattering electrons by photons and turning up 90 degrees to the floating gate. The features of vertical injection by steps are high injection efficiency, shorten programming time, facilitate multi-level storage, improve controllability, enable operation at low voltage, and achieve reliability and simplification of all processes I do.

By using the first feature of the present invention of the step channel / drain structure only by adjusting the drain overlap region slightly longer than the length of the horizontal channel, a low voltage of 5V can be used instead of the prior art double polysilicon. A programmable single polysilicon EPROM cell is achieved. Because of its structure and simplification of production process and low voltage operation, it can be used for applications such as integrating EPROM on its chip using logic or DRAM process, and aluminum wire, poly for redundancy personalization on DRAM chip. Silicon fuse can be replaced.

A new feature can be achieved in a double polysilicon EEPROM transistor with a step channel / drain that the erase and program operations can be performed reliably using the same junction. Increase the length of the N-drain and increase the depth of the junction to withstand the high voltage required to cause FN tunneling from the floating gate to the diffusion without significantly affecting the injection efficiency. And lighten or adjust the dose. In the prior art EEPROM, a reliable erase operation from tunneling to diffusion can be performed only at a deep source side junction, but not at a shallow drain junction used for programming. In a conventional split gate cell, the floating gate has only one junction, so erasing and programming cannot be performed on the same side. However, using this new feature in both split-gate and stacked-gate structures allows the use of the same junction and EEPROM transistors. Double polysilicon EEPRO with step channel / drain
Another new feature of the erase operation by tunneling from the floating gate to the control gate in the M transistor is made possible by adjusting the length of the overlapping floating gate on the N-drain diffusion.

In the prior art, removing electrons by tunneling from the floating gate to another polysilicon required a triple polysilicon structure in the EEPROM transistor. Features of this new double polysilicon EEPROM transistor include shallow drain junctions (from floating gate to diffusion), simplifying process complexity (double polysilicon vs. triple polysilicon), as well as word line (control line) levels An object of the present invention is to enable erasure of a small block size and provide a long life and the like by reducing unnecessary program / erase cycles. A nonvolatile RA using a split-gate double-polysilicon transistor having a step channel / drain structure, which could not be achieved by the conventional EEPROM.
M operation is enabled by a combination of low voltage programming and the operation characteristics of poly-to-poly tunnel erasure. The definition of the random access memory is "0" (program) and "1" for transistors in different locations (different bits) at the same time for the selected control gate.
(Erase) can be written. With an optimized design and imposing a voltage on the drain and source, a split gate double polysilicon transistor with a step channel / drain structure can achieve this RAM function. The double polysilicon split gate transistor with the injection step channel is non-volatile and operates like a RAM, so that it can be used for much wider applications. Further, since programming and erasing can be performed for each bit, the programming / erasing time is shortened and the durability to programming / erasing is extended.

A triple polysilicon EEPROM transistor with horizontal and vertical channels (but no N-drain region) is provided. This is a double polysilicon EEPR with step channel / drain
This is a variation of the OM transistor, and uses the same concept that high injection efficiency is obtained because the straight traveling direction of electrons is perpendicular to the floating gate.

A primary object of the present invention is to demonstrate that a stepped channel device structure can be produced. First, a simple method for forming a step channel having an N-drain self-aligned to the step will be described. The floating polysilicon gate covers the step channel by a non-self-aligned process. The basic steps of forming a stack and split gate transistor in an ERPROM / EEPROM using this simple method of creating steps are shown.

Another method of forming a split gate transistor is provided. Among them, the length of the channel and the step under the floating gate can be accurately formed, and the error can be almost ignored by making full use of the spacer technology.

Description of the operation of the present invention

EEPROM N-Channel Transistor with Step Injection Channel at Drain End FIGS. 4A and 4
B is a sectional view of the step-injection channel transistor according to the first aspect of the present invention. Transistor 400 of FIG. 4A
a is a P-type silicon substrate 401 (which may be a p-type epitaxial layer on a semiconductor substrate to which P + is added);
It has a horizontal channel portion of the N + source diffusions 404 and 410, a drain diffusion 406, a floating gate 440 and a control gate 445 which cover both the horizontal channel and the step channel uniformly. The floating gate is dielectrically separated from the surface of the semiconductor substrate by a dielectric layer 420 which is a thermally generated dioxide. The control gate 445 is a floating gate 440
The capacitor is capacitively coupled (capacitively coupled) through a dielectric film 430, and the dielectric film may be either heat-generated silicon dioxide or a combination layer of silicon dioxide and silicon nitride.
The p type 401 is generally about 1E16cm ^-3 to 5E
Added between 17 cm ^-3 . Dielectric film 420 is typically 5 to 10 nanometers thick and floating gate 440 is typically a thick N
The thickness of the + additive film may be 100 nm or 300 nm.
Control gate 445 may be a low resistance interconnect material, such as polysilicon silicide with a thick N + doped film, or other refractory material or metal. Passivation is indicated by layer 900 and can be made of any of the known silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. N + source diffusion 404 is made by arsenic, phosphorus, antimony, or ion implantation. Before the step is formed, a shallow boron halo (pocket) is implanted to increase the electric field at the corner 415 to increase the injection efficiency and the N-channel drain 402 is easy to use. The same ion impurity material is used. Immediately before the oxide layer is formed, it is injected in a self-aligned manner.

As shown in FIG. 4C, the angle of the step measured from the horizontal plane of the original surface of the semiconductor substrate is not so critical, and is 20 n
The high injection condition is satisfied as long as m or more. If this angle is too small, the length of the step channel portion becomes too long, and the degree of integration is deteriorated. Therefore, the step angle is preferably 30 degrees or more. The depth of the step 413 is at least 20 nm or more. The purpose of the step 413 is to use the floating gate 440.
To efficiently inject hot electrons into the

When an appropriate voltage is applied to the control gate 445, the potential of the floating gate increases due to capacitive coupling, and an electron layer is formed in the channel portion 410. The electrons are then accelerated by the horizontal drain field when the drain diffusion 406 is subjected to a positive voltage, as seen in a MOSFET transistor. Electrons flow in the inversion layer (typically about 10 nm) of the horizontal channel section 410 on the silicon surface. If N-drain is the corner of channel 415
At a moderate addition concentration (normally less than IE18 per cm ^-3 ), the highest electric field
Around 415 can be made along 3 and the electrons reach their maximum speed there, and this is the injection point because the electron travel is still nearly horizontal. Conventional CHE
In the EPROM, the electrons accelerated in the channel rely on an indirect method in which electrons having an energy of 3 eV or more are injected into the floating gate even if the electrons accelerated upward by 90 degrees toward the floating gate after phonon scattering. In the step structure of the injection of electrons into the floating gate, the floating gate potential of each of the electrons whose channel energy is higher than the barrier height (3 eV in the case of silicon dioxide) is 41
When the potential is higher than 5, the floating gate is injected straight without the need for phonon scattering. The floating gate potential due to capacitive coupling from the control gate lowers the height of the tunnel oxide barrier by the Schottky effect, while increasing the horizontal electric field and accelerating the channel electrons. Thus, the configuration of the step structure of the present invention significantly improves the efficiency of electron injection from the channel to the floating gate.

When the floating gate voltage drops due to electron accumulation and drops below the threshold voltage, the channel electrons disappear and no current flows. In read mode, it is preferable to switch between the drain and the source in order to prevent injection of electrons into the floating gate due to a voltage surge due to power noise; that is, the step side is the source and the other end is the drain.

The conditions for obtaining a high injection efficiency at a low voltage using a step drain / channel EPROM transistor in a channel hot electron program are summarized below: Structural conditions: (1) The depth of the step is 20 nm or more and from the horizontal channel plane. Is preferably 30 degrees or more. (2) The drain junction end is preferably located at the corner of the channel, but a high injection efficiency can be achieved even with a p-type step channel.

Optional conditions for selection: (1) The potential (compared to the source junction) at the injection point of the step channel angle is 2.5 to 3.0 V or more. (2) The potential of the floating gate must be at least larger than the potential at the injection point angle.

The EPRO of the present invention is compared with a conventional EPROM.
The M structure is obtained by a drain voltage of about 3V which is much lower than the required 5V at the low injection efficiency of the conventional EPROM cell, and is characterized by a high injection efficiency of hot electrons into the floating gate. Thus, the control gate voltage required for the EPROM cell according to the prior art can also be relatively significantly reduced. High implantation at low voltage can solve many of the problems described in the "Description of the Prior Art" section.

The drain voltage of the present invention can be achieved because hot electron emission is already achieved with high injection efficiency.
It can be reduced to the theoretical limit of 2.5-3.0 V, which is almost half of the voltage required for the EPROM according to the prior art.

The control voltage of the present invention can be relatively reduced with the reduction of the drain voltage.

Because of the high injection efficiency of the present invention, the program time for storing the target level injection electrons in the floating gate is reduced. The program time saved in the gate is reduced.

This is simplified because the programming time for the multi-level storage on the floating gate to achieve the target level determined by the control gate voltage is short.

Since the electric field for writing hot electrons in the conventional EEPROM cell does not need to be high, the reliability and durability of the memory cell are improved according to the present invention.

Since the height of the voltage for the control gate is reduced, the thickness of the support circuit oxide and the channel length are greatly reduced.

High injection efficiency and low voltage operation significantly reduce power consumption during programming, making it very attractive for portable operation.

[0056]

【Example】

Embodiment: Single-Polysilicon Step-Channel Drain EPROM Transistor and Its Operation A single-polysilicon n-channel EPROM cell which achieves lower voltage programmability than the prior art using a step-injection channel / drain, which is the object of the present invention, is possible. I made it.

Low voltage operation below 5V is attractive because it does not require a thick insulating film for high voltage devices and a drain engineering process. 5A, 5B and 5C are cross-sectional views of a single polysilicon channel EPROM transistor according to a second feature of the present invention. This transistor is a modified version of the transistor 400a. The second polysilicon is removed, and the size of the gate overlapping the drain Ln region is adjusted. Transistor 500
a is a p-type substrate 501, an N + source diffusion 504, a horizontal channel portion 510, a step 513 (a boron halo may be inserted), an N drain diffusion 502, an N + drain 506, and a floating (horizontal and step channels are uniformly covered). It comprises a gate 540. The floating gate 540 is dielectrically separated from the surface of the semiconductor substrate by a dielectric insulating film 520 formed by heat generation. The passivation layer 900 is the same as that described in the first feature. For improved (enhanced) devices, usually p-type 501 is IE16cm
^-3 to 5E17 cm ^-3 .
The dielectric film 520 is typically 5-10 nm thick and the floating gate 540 is typically a thick N + film of polysilicon, with a thickness between 100 nm and 400 nm. The N + source diffusion 504 is made by ion implantation of arsenic, phosphorus, and antimony. The N-channel drain 502 is made of the same implantation material, but is self-aligned to the step channel end 513 immediately before forming the step before the oxide layer 520 is formed. The concentration of 502 below the floating gate is IE17 or higher.
It is slightly lower than the concentration of 5E20cm ^-3 or more diffusion junction 504 and 506 between 5E19 cm ^-3. The angle of the step is preferably 30 degrees or more measured from the horizontal plane. The depth of the step 513 is 30 nm or more.

The purpose of the step 513 is to use the step channel 515.
In this case, hot electrons are more efficiently injected into the floating gate 604 at the corners.

The conditions for injecting electrons into the floating gate are the same as those described in the first feature section "EPROM N-Channel Transistor with Step Channel at Drain" described above: (1) Injection point 515 Is 2.5V-3.
Be higher than 0V. (2) Floating gate potential 2.5V ~
3.0 V must be higher than the voltage at the injection point.

The first condition (1) can be easily achieved by applying a drain voltage of 3 V or more. The floating gate potential of the second condition (2) is 2.5
What must be above V-3.0V can be obtained in two ways.

In the first method, the length of Ln (502) is made slightly longer than the length (510) of the horizontal channel portion. This increases the coupling capacitance from the drain to the floating gate. In this case, when 5 V is applied to the drain 506, the floating gate voltage becomes 2.
It becomes 5-3.0V. Potential at injection point is about 3V
The junction end 502 so that it stays at the injection point 51
It is also good to offset from 5 to the corner of the step bottom. The second method is to use a floating gate 5 as shown in FIG. 5A.
To make the gate of the capacitor 541 electrically connected to each other with the same polysilicon as 40 and the coupling capacitance 500b outside the EPROM transistor. The coupling capacitance part is 0.6a
It is designed to be slightly larger than the EPROM transistor gate area in order to obtain a coupling ratio. Thus, when 5V is applied to the diffusion of capacitor junction 556, the floating gate potential is coupled through the capacitor to about 3V. Once the conditions (1) and (2) are satisfied, the channel hot electrons are efficiently and directly (without needing phonon scattering).
Injected into the floating gate.

In the second method, the outer capacitor performs the same function as the control gate of a double polysilicon EEPROM memory cell. In the first method, the transistor plays the role of storage, but has no function of selection. Therefore, in order to use this device as an EEPROM memory cell, a conventional n-channel FET device 500c can be used as a single EPR as shown in FIG. 5A.
It is added in series to the OM transistor 500a. The gate of this conventional FET transistor 500c provides a selection function (control gate) for accessing information of the storage transistor 500a. In this method, the storage EPROM transistor is normally 'on'. (5E16 ^/ cm 3 ~5E17 ^/ c
A depletion device using arsenic or phosphorus in channel region 510 at a concentration between m ³ ) After storing the injected electrons, the threshold voltage is increased to obtain an 'off' state.

The main object of the present invention is to use a step injection channel / drain to form a single polysilicon n-channel E
PROM cells provide low voltage programming as low as 5V. The advantages obtained from this single-poly EPROM are that (i) the necessity of double-polysilicon is eliminated, (ii) no high-voltage device is required, and (iii) the elimination of double-polysilicon and high-voltage devices by simplifying the process EPROM convertibility with logic or DRAM can be achieved. (Iv) A wide area application for integrating EPROM on a logic chip can be created, and the fuse of DRAM chip can be replaced and used for redundancy personalization.

[0064]

[Embodiment: Electric erase by tunneling from floating gate to diffusion in double polysilicon EEPROM with step channel drain]
In double polysilicon EEPROMs, erasing is by electron tunneling from the floating gate to the diffusion, and a third feature of the present invention is that erasing and programming with the same step drain-diffusion is possible.

The transistor 400a of FIG.
Double Polysilicon EEPROM Transistor 30
0a, wherein the drain junction is replaced by a step channel / drain and the depth of the source junction 404 is reduced. The source junction depth can be reduced because erasing is done on the side walls of the step channel / drain rather than on the source side. This step junction already has a lightly added n-junction, one to the breakdown.
0-12V is designed to withstand. Transistor 400b (FIG. 4B) is the split gate of an EEPROM and performs tunneling to diffusion. This is something that could not be done with the conventional invention. In the prior art, tunnel erasure to diffusion has been impossible because erasure and programming must be done at the same junction, which are of opposite nature. In both cases, the transistors 400a and 400b have a P-type semiconductor substrate 401,
N + source diffusion 404, horizontal 410 channel region whose conductivity is controlled by floating gate 440, control gate 445, step 413, N
-A drain diffusion 404, an N + drain diffusion, a floating gate 440 covering both the horizontal channel and the step channel, and a control gate 445.

The split gate 400 b has an extra channel region 418 and its conductivity is controlled by a gate 445 in series with a portion of the channel 410. The floating gate is dielectrically separated from the semiconductor substrate surface by a dielectric film 420.
Is a dioxide grown by heat treatment. The control gate 445 is capacitively coupled to the floating gate 440 through an insulating film 430, and the insulating film may be either thermally grown silicon dioxide or a combination of silicon dioxide and silicon nitride. P type 401 is added between the common 1E16 cm ^-3 of 5E17 cm ^-3, a die electric layer 420 is usually 5 to 10 nm thick, a floating gate 440 is a polysilicon film that is N + added thickness thereof is 100nm ~
A distance between 300 nm is good. The control gate 445 is made of a thick N + -added polysilicon film, a low-resistance wiring material such as silicide, or a refractory metal material. N + diffusions 404 and 406 are made by arsenic, phosphorus or antimony ion implantation. N-drain 40
2 is formed by self-aligning the same ion implantation into the step channel end 413 immediately after the step formation or before the oxide layer 420 is formed. At this point, it is also possible to increase the electric field by adding a p-type halo to enhance the injection. N junction 402 is typically 1E17 to 1E for 10V erase
An addition (doping) of between 18 cm ^-3 is made, the depth of which is chosen between 250 and 300 nm, a little deeper than the source junction 150 to 200 nm.

The programming requirements and explanation are described in Section I. a "EEP with step channel at drain end
Exactly the same as a ROM n-channel transistor. The angle of this step is generally 30 degrees or more as measured from the horizontal plane.

The depth of the step 413 is at least 30 nm.
The purpose of step 413 is to more efficiently inject hot electrons into floating gate 440 at the corner of step channel 415.

The erasing operation is basically performed by the transistor 30
0a and the same as the most commonly used transistor in the industry. Assuming that the tunnel oxide 410 is 9 nm, the ONO 430 is 20 nm, and the coupling ratio is 0.55, about 10 V is applied to the drain junction and the transistor 400a or 400
In either case, when the control gate is set to φV, the electric field of the oxide 422 exceeds the critical value of FN tunneling (about 10 MV / cm). Electrons captured by the floating gate are 300a
In this case, the source side is looked at by the FN tunnel, but here, it is removed by FN tunneling at a step channel / drain formed on the drain side. In this method, since a high voltage is required at the drain junction, the drain junction is liable to avalanche breakdown. N-junction 402 is lightly doped and deeper than source junction 404 to eliminate breakdown during erase. By optimizing the design in this way, the invention of the programming and erasing operation using the step channel / drain junction can be achieved. The split gate structure is the same as the stacked gate structure, and the double polysilicon EEPRO of the present invention is used.
It can be made with M transistors.

[0070]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Electrical Erasing by Tunneling from Floating Gate to Control Gate in Double-Polysilicon EEPROM with Step Channel In the description of the prior art, the removal of tunneling of electrons from a floating gate to another polysilicon is performed in triple. A polysilicon structure was required. When a voltage is applied to the control gate in a two-layer polysilicon stack, split gate transistor cell,
The design was such that more than half the control gate voltage was induced on the floating gate.
Therefore, the thickness of the tunnel oxide is much thinner than the dielectric NO between the upper poly layers, so that the electric field applied to the tunnel oxide is many times larger than the electric field applied to the upper portion. This means that the tunnel started with the tunnel oxide first upward, and programming (injection) occurred instead of erasing, and poly erasing could not be performed. Then, third polysilicon was added for erasing, and erasing was performed by tunneling between the floating gate and the third erasing gate. However, in the step channel / drain transistor of the present invention, the tunnel erasure from the floating gate to the control gate can be safely achieved by double polysilicon by selecting an appropriate NO thickness and LG length.

Another new feature of the floating gate to control gate erase operation in a double polysilicon EEPROM transistor with a step channel / drain is the fourth feature of the present invention. Double polysilicon EEPROM transistors 600a and 6
At 00b, the requirements for electrical erase and programming are:
(I) Tunnel gate oxide 620 is 5 to 10 nm
Things between. (Ii) Dielectric 630, such as ONO or nitride oxide, should be as thick or thicker than tunnel oxide. Normal 8-1
5 nm. (Iii) The length of the channel region 610 and the overlap spread (overlap spread) Ln 602 are substantially equal to or greater than each other.

A typical critical electric field for tunneling from polysilicon to polysilicon through thermal oxide on polysilicon or oxide / nitride deposited by CVD is about 6-7 MV / cm.
(E. Harari and F.O.
According to Masuka), the electric field of the oxide of the heat-treated substrate is 10 MV / cm, which is lower than this. ) So the electric field of the die electric 630 must be higher than 6 MV / cm to eliminate the tunnel from the floating gate to the control gate. On the other hand, taking into account the disturbance of the charge injected by the channel hot electrons, the electric field between the poly layers is 3 MV / c.
m or less. Transistor 60
Double polysilicon EEPRO at 0a and 600b
The design and operation of M are illustrated using a simple model.
FIG. 7A shows a simplified capacitance model of transistors 600a and 600b. Capacitor Ccg-fg is the capacitance between control gate 645 and floating gate 640. Cfg
-Ln is the floating gate 640 and the n-diffusion region 6
02. Cfg-ch is the capacitance between floating gate 640 and channel region 610. (More precisely, Cfg-ch
Should also be included from the source to floating gate overlap capacitance. 3.) Here, for simplicity, the three capacitances are assumed to be of the same size, but this choice is a realistic assumption. When voltage is applied to any terminal node, 1/3
Are applied to the floating gate node by capacitive coupling, and each voltage is added. (Superimpose.)

The program conditions for injecting electrons into the floating gate are described in the first section above. (1) The floating gate voltage is> 3 V. (2) The injection point potential is> 2.5 to 3.0 V. Based on the assumption that all capacitances are the same (flat channel length = Ln), when 5 V is charged to the control gate and the drain node, the floating gate voltage becomes 3.3 V due to the capacitive coupling and satisfies the program condition. For example, tunnel gate oxide 8n
Taking m and ONO 11 nm as an example, the potential of ONO 11 nm is 1.7 V = 5 V-3.3 V, and the electric field is 1.55 MV / cm (= 1.7 V / 11 nm).
Assuming that the control gate is 5 V, the floating voltage is 1.7 even if the source / drain is grounded.
V and the electric field of the ONO is 3 MV / cm (= 3.3 V / 1
1 nm). Thus, during programming, the electric field of the ONO is kept below the design target of 3 MV / cm. In the erase operation, the control gate voltage is further increased, while the source and drain are kept at φv. When the control gate voltage is increased to 10 V, the floating gate voltage becomes 3.3 V due to the capacitive coupling, and the potential difference applied to the ONO is 6.7 V = 1.
0V-3.3V. ONO electric field is 6 MV / cm
(= 6.7 V / 11 nm), which satisfies the target condition for electron tunneling from the floating gate polysilicon to the control gate polysilicon.
In this manner, the poly-to-poly tunneling erasure can be reduced by one.
At 0V and programming with channel hot electron injection at 5V is achieved. The condition of the erase voltage is the triple (three-layer) polysilicon EEPR of the prior art.
It is almost the same as the voltage level required for the OM cell.

The transistors 600c, 600d and 60
Reference numeral 0e denotes a double polysplit gate transistor shown in FIG. 6C having a stepped channel of the transistor 600c, which is slightly modified from 600b. All of these transistor variations use the same electron injection mechanism as transistor 600b described above. The same transistor element label numbers as those used in the description of the structure and function of the transistor 600b are used for 600c, 600d, and 600e.

The floating gate of the transistor 600c is formed on the side wall of the split gate as shown in FIG. 6C. At 600c, a coupling capacitor is obtained through the sidewall between the split gate and the floating gate. Erasing is done by tunneling through the side walls. Transistor 600d
Are embedded in a silicon substrate. The transistor 600e is the transistor 600
Although it has a floating gate embedded with d, the function of N + drain 606 is coupled to region 602 with a higher sheet resistance penalty. A highly integrated memory array can be manufactured by arranging the transistors 600e.

Summarizing the advantages obtained with an electrically erasable programmable read only memory transistor with a step channel / drain using poly-erase: 1) The double silicon EEPROM cell with step channel / drain of the present invention is a poly-silicon EEPROM. Enables erasure to silicon. Three-layer polysilicon EE with separate program control gate and erase gate
Unlike PROM, it allows CHE programming and erasing using the same control gate. This split gate transistor can achieve the advantage of using a shallow junction for the memory cell because the drain and source operate at low voltage. In addition, the polysilicon layer is changed from three layers to two.
The layers simplify the process.

2) Since each control gate (= word line) can be used for the erasing operation and the programming operation, it is possible to erase a small unit at the word line level instead of erasing a large block size seen in a three-layer polysilicon EEPROM. . Therefore, local memory data in small units can be erased instead of unnecessary large blocks. Since the program / erase cycle is not used more than necessary, the life of the EEPROM is extended.

[0078]

EXAMPLE: Non-Volatile Random Access Memory Operation in a Double-Polysilicon Split-Gate Structure In a flash EEPROM operation according to the prior art, programming and erasing were performed sequentially. This is because the program and erase operation conditions were not compatible. The program operation was to first erase the entire memory chip or a portion of the memory chip and reprogram that portion. Selected control gate (word line)
This is because "φ" and "1" could not be simultaneously written into arbitrarily different (bit) transistors.
For this reason, the EEPROM was able to write "φ" and "1" in order, but was not called RAM but was called ROM.

By combining the poly-to-poly erasure function and low-voltage programming in the double-layer polysilicon split-gate transistor of the step channel 600b, any transistor location can be programmed as long as it has an electrically connected control gate. And erasure can be performed at the same time. Thus EEPR
The features of the random access memory lacking in the OM can be achieved by using a split gate transistor having a step channel with proper design and operation.

The concept of the operation and design of the random access memory using the split gate transistor 600b, which is the fourth feature, is the fifth feature of the present invention.

The principles of the program and erase operations are the same as described above. Electrical erasure can be accomplished by tunneling electrons from the floating gate to the control gate, and programming can be accomplished by forward injection into the step channel. Repeat the description of the same model and its transistor to make the description clear. In the double-layer polysilicon EEPROM transistor 600b, the condition of the nonvolatile operation is that (i) the thickness of the tunnel gate oxide 620 is between 5 and 10 nm. (I
i) Insulating layer 6 such as ONO or nitride oxide
Numeral 30 is slightly thicker or equal to the thickness of the tunnel oxide, usually between 8 and 15 nm. (Iii) Length of channel region 610 and overlap diffusion Ln6
02 is the same length or more.

Thermal oxide on polysilicon or C
A typical critical electric field for tunneling from polysilicon to polysilicon through oxide / nitride deposited with VD is about 6-7 MV / cm. (E. Harari an
d F. According to Masuka), the electric field of the oxide of the heat-treated substrate is 10 MV / cm, which is lower than this. 3.) The electric field of the die electric 630 must therefore be higher than 6 MV / cm for tunnel erasure from the floating gate to the control gate. On the other hand, considering the disturbance of the charge injected by the channel hot electrons, the electric field between the poly layers becomes 3M.
It must be kept below V / cm. The design and operation of a double polysilicon EEPROM in the transistor 600b is illustrated using a simple model. FIG.
A shows a simplified capacitance model of the transistor 600b. The capacitor Ccg-fg is connected to the control gate 645 and the floating gate 64
It is a capacitance between zero. Cfg-Ln is the capacitance between floating gate 640 and n-diffusion region 602. Cfg-ch is the capacitance between floating gate 640 and channel region 610. By using this concept and choosing the appropriate voltage and capacitor parameters in a more accurate model, we can optimize more finely, but for the sake of simplicity we assume that the three capacitances are the same size. I do. (This choice is a realistic assumption.) When a voltage is applied to any terminal node, one-third of that voltage is induced by capacitive coupling at the floating gate node, and each voltage is added. (Superimpose.) The program conditions for electron injection into the floating gate are as follows: (i) Floating gate voltage> 3 V (ii) Injection point potential is> 2.5-3.0 V at 615 injection points It is. The channel length and the size of Ln are adjusted to satisfy the following design requirements.

When the tunnel gate oxide is 8 nm and O
FIG. 7B shows an example in which NO is 11 nm and the write operation voltage condition is satisfied. FIG. 7B shows a table of the floating gate potential and ONO satisfying the write “φ”, “1”, and “no change (unselected)”. The electric field was represented. The reference is the lowest voltage of zero volts used here.
The control gate voltage is 10 V when 5 V is not selected.
It is when V is selected. Drain and source voltage are written "φ" (high Vt is obtained by electron injection)
, Vs = 5V and Vd = 10V, and write
Vs = φV and Vd = φV for 1 ″ (low Vt due to tunnel erasure through ONO), and Vd = 5V with Vs = 5V when “no change”. Floating when 10V is applied to control gate and drain node The gate voltage is 8.3 V (resulting in Vds = 3.3 V, Vgs = 5 V) by capacitive coupling, which satisfies the program condition, and the potential applied to the 11 nm ONO is 1.7 V = 10 V-8.3 V, The electric field is 1.55 MV / cm (1.7 V / 11 nm), the control gate is 10 V, and the source / drain is 5 V.
, The floating voltage (floating voltage) is 6.7V
And the electric field of the ONO is 3 MV / cm (= 3.3 V / 11 n
m). Thus, the electric field of the ONO during programming is kept below 3 MV / cm, and the target condition can be satisfied.

In the erase operation, the control voltage is maintained at 10 V, but the source and drain are reduced to φV. The floating gate voltage becomes 3.3 V by capacitive coupling, and the ONO voltage becomes 6.7 V = 10 V−
It becomes 3.3V. The ONO electric field is 6 MV / cm (= 6.
7V / 11 nm), which fills the target for electron tunneling from the floating gate polysilicon to the control gate polysilicon, and the electrons stored on the floating gate are removed by the control gate. ONO electric field is always 3MV
/ Cm or less. When the control gate is not selected and Vfg = 5V, Vd = 10V, and Vs = 5V are not selected, the floating gate is 6.7V, that is, Vgs =
1.7V, which is close to the voltage at which the drain and source are turned on. This malfunction when not selected is caused by the split gate 6
20 can be prevented by installing them in series with the floating gate.

Writing "φ" or "1" in accessing the control gate can be performed at any time by selecting appropriate voltages for the drain (bit) and source when the control gate is selected to be 10V. At the same time, among the memory cells electrically connected to the selected control gate, "φ"
Writing “1” with “1” is the operation of the random access memory itself. Thus, the prior art EEPROM
However, the split gate double polysilicon transistor of the present invention enables a nonvolatile RAM to be achieved.

The advantages obtained by the operation of the double polysilicon split gate transistor having the step channel / drain are as follows. 1) Programming and erasing can be performed in bit units as needed. Conventional triple polysilicon EEPR
Unnecessary erase cycles at the time of data rewriting in the OM are omitted. Since writing can be performed in bit units, resistance to program / erase cycles is improved.

2) The double polysilicon split cell with step channel / drain of the present invention and proper operation and design provide a non-volatile RAM. The present invention can be used in a wide variety of applications to provide non-volatile but behavior like a RAM.

[0088]

Embodiment: Triple Polysilicon EEPROM with Vertical Floating Gate Channel Another feature of the present invention is a variation of EPROM transistors 800a and 800b with a step injection channel and relates to the sixth feature. FIGS. 8A and 8B are cross-sectional views of a triple polysilicon EEPROM transistor with any vertical floating gate channel and horizontal channel connected in series. Transistors 800a and 800b are made of P-type silicon substrate 801, N + source diffusion 804; horizontal channel region 818 (conductivity is controlled by the third polysilicon of the selected word gate). The vertical channel 810 is controlled by a floating gate 840 and a control gate 845.

The floating gate 840 covers the vertical channel and the drain diffusion 806 at the bottom of the vertical trench. The floating gate is dielectrically separated by thermally grown silicon dioxide 820. The control gate 845 is dielectrically coupled (capacitively coupled) to the floating gate 840 through a dielectric film 830, and the dielectric film may be either thermally grown silicon dioxide or a thin film of silicon dioxide and silicon nitride. .
P type 801 is usually 1E16cm ^-3 to 5E17c
channel gate oxide horizontal is doped among the m ^-3 is slightly thicker at between 8 and 15 nm, 300n from the floating gate 840 is normally N + in be a doped polysilicon film thickness of 100nm
Good between m. The control gate 845 is a polysilicon film doped with N +. Select gate 850
May be polysilicon or a low resistance silicide or refractory material. The N + source diffusion 804 is formed by ion implantation of arsenic, phosphorus, and antimony. N +
The drain 806 is formed of the same ion implanted material, but is self-aligned to the vertical channel end 810, which occurs immediately after the step formation and immediately before the deposition of the floating gate polysilicon 840. Junction 80 when N + junction 806 is used for erasure
6 is doped with phosphorus to increase the junction depth so that the junction breakdown is higher. Floating gate 840 and select gate 850
The drain junction depth may be a normal arsenic doped junction when erasing is performed by tunneling between. Here, channel electrons are provided from N + junction 804, but if electrons are provided to the select gate channel, N +
A channel electron inversion layer (inverted layer) may be used instead of the junction.

When a voltage above a certain level is applied to the control gate 845, the potential of the floating gate capacitively coupled from the control gate becomes higher than the threshold voltage of the vertical channel region 810. If the select gate 850 also has a threshold. When the voltage is higher than the voltage, the electrons are connected to the source junction 8
From 04, it starts flowing to the drain junction 806.
Electrons are accelerated by a horizontal electric field as seen in MOSFET transistors.

The potential of the control gate 845 is sufficiently high so that the potential of the floating gate becomes higher than the sum of the drain and the threshold voltage, and the horizontal gate resistance is slightly higher than the threshold voltage when the select gate 850 is slightly higher than the threshold voltage. As long as it is high, the channel potential at 815 will approach the voltage applied to drain 806. This produces the highest electric field at the intersection 815 of the horizontal and vertical channels, the highest speed of the electrons and the movement of the electrons is still horizontal, so the corner of 815 is the injection point. When the energy level of the electrons accelerated in the channel becomes higher than the height of the barrier, the high-energy electrons are injected straight through the oxide into the floating gate. In contrast, the prior art was injected into the floating gate by an indirect process of turning 90 degrees upward due to phonon scattering of electrons. In this way, the efficiency of electron injection from the channel to the floating gate is improved by orders of magnitude using the vertical channel structure.

[0092]

Example: EEPRO with step channel drain
The main object of the present invention is to show a new structure of the EEPROM device structure, to show the device operation of the new structure EPROM, EEPROM and NVRAM transistor, and to show another method of making the structure. It is. There are many ways to create a step channel at the drain end, but some of them will be explained. The first method is a simple method that does not use a self-aligned line in which a channel step is covered with floating gate polysilicon. The second method is
This is a method of minimizing misalignment during a mask process by a method other than the first self-alignment.

[0093]

Embodiment: Simple Step Channel Drain Forming Method FIGS. 9A and 9B show a method of forming a step channel / drain structure which is the seventh feature of the present invention by a first method. LO
Immediately after the COS device isolation or shallow trench isolation 454, step building begins as shown in FIG. 9A. The area of this device is still thin silicon oxide and CV
It is covered with a D-deposited nitride dielectric (dielectric film) 425. The photoresist 462 of FIG. 9B is used to define the set step region. Using the photoresist layer 462 as a mask, the dielectric layer 452 is etched by a wet etch such as dry RIE or KOH. Then the silicon substrate is carefully etched to a depth of at least 30 nm. The angle of the step should be kept at least 30 degrees, measured from the horizontal silicon surface, to achieve high implantation efficiency,
This is for injecting electrons horizontally into the floating gate. This angle can be controlled by setting etch conditions in RIE. The n-region 402 is then implanted at the channel drain end 415 with arsenic, phosphorus or antimony by self-alignment. The implantation amount of the n− region is smaller than 5E19 cm ⁻³ in order to control the thickness of the channel oxide on the step 413 and maintain good gate oxide quality. The structure of the n-junction can be achieved by a simple process called self-alignment in the step channel / drain region. After the removal of the photoresist 462 and the dielectric layer 452, the tunnel oxide 420 is thermally grown. After forming the step channel / drain, the normal EEPROM process is continued.

[0094]

EXAMPLE: Method of Manufacturing Stacked Gate Transistor Using Simple Step Forming Method A method of forming the transistor 400a in FIG. 4A and the transistor 600a in FIG. 6A will now be provided. The difference between the two transistors is simply the N-drain junction. The N-drain junction of transistor 400a is deeper than that of 600a because of the high voltage for tunnel erasure from the floating gate to the N-drain. This is obtained by implanting highly diffused impurities such as phosphorus,
cm2-5E14 / cm2 phosphorus at 100 KeV ~
It is implanted at an energy of 180 KeV. On the other hand, the N-drain transistor 600a is formed by implanting phosphorus ions at an energy of 30 to 100 KeV. Arsenic can also be used for N-drain in transistor 600a. At that time, the depth of the N drain junction of the transistor 600a becomes shallower than the source junction of arsenic. Floating gate polysilicon 440 is deposited on thermally grown tunnel oxide 420, and a thin oxide is grown on the polysilicon layer. Then a photoresist mask 464 is applied,
The floating gate is separated from the neighboring cells as shown in FIG. 9C.

A composite (synthetic) dielectric layer 430, such as ONO or nitrided oxide, is made of a deposit, on which a second control gate polysilicon 445 is made. After forming a dielectric layer 455 on the control gate polysilicon, carefully etch the control gate and floating gate by reactive ion etching using the photoresist mask 466 in FIG. 9D, and then step source / drain junction regions Ion implantation. Ordinary F
ET process for sidewall spacer formation, diffusion annealing,
Passivation, drilling of contact holes, metal processes for wiring, etc. follow. Thus, a final device structure of the stacked transistor 400a shown in FIG. 6 and the transistor 600a shown in FIG. 6A is obtained.

[0096]

EXAMPLE: Method of manufacturing split gate transistor using a simple step forming method After forming a step channel, split gate transistors 400b and 600b having a step channel / drain are manufactured by a common split gate process. Is no different. During formation of the step channel, the requirements for the N-drain junction are different for the two transistors. The N-drain of transistor 400b is designed for high voltage to eliminate tunneling from the floating gate to the N-drain, so that the N-drain junction of transistor 400b is deeper than that of 600b and has a high diffusion of phosphorus. 5E13 / cm ³ ~
5E14 / cm ³ of phosphorus at 100 KeV to 180 K
Implant with energy between eV. On the other hand, transistor 0
The N-drain of Ob is formed by the small energy of the phosphorus ion implantation of 30 KeV to 100 KeV. Arsenic for the N-drain may be used for the transistor 600b. Thus, the depth of the N-drain junction of transistor 600b is as shallow as the arsenic source junction.

In FIG. 10B, the photoresist mask 4 is formed.
65 is used for N + junction formation and implant N + ions using the arsenic, phosphorus or antimony species. Then, the floating gate between adjacent cells is separated on the field oxide as shown in FIG. 9C. After removing the thin oxide on the channel 418, the split gate channel gate oxide and poly oxide are thermally grown. Then, a composite dielectric layer such as ONO or nitride oxide is deposited, followed by a second control gate polysilicon 445 shown in FIG. 10C. The N + ion implantation dose of 404 has been chosen to be quite high, such as 5E20 to 5E21 cm ^-3 , which compares the oxide 424 with the gate oxide 428 on the split channel gate 418 in FIG. It is for growing thickly on top.

Dielectric composite layer 430 (synthetic dielectric layer)
After the formation of the control channel polysilicon 428 and the split channel region 428, the control gate and the floating gate are simultaneously etched by careful reactive ion etching using a photoresist mask. This is followed by the usual FET processes such as sidewall spacer creation, diffusion annealing, passivation, contact hole drilling and wiring metallization. Thus, the split gate transistor (of FIG. 4A) 4
00b and the final device structure of transistor 600b of FIG. 6A.

According to each method, transistors 400a, 400b, 600a and 600b having a high injection step channel structure having a self-aligned diffusion region can be obtained by simple steps. Once the step channel / drain is formed, the conventional stack gate transistor or split gate transistor process continues.

[0100]

EXAMPLE: Manufacturing of a stepped split gate transistor having a large side gate Example: Method of manufacturing a stepped split gate transistor having a large side gate This is a method for accurately controlling the length of the overlapped Ln. Two fabrication methods will now be described; the first is to create a relatively large horizontal channel below the floating gate, and the second is a short horizontal channel. 11A-11
G denotes a split gate transistor 60 having a stepped channel / drain structure related to the above-described features of the present invention.
0c shows a variation of the manufacturing method. After LOCOS device isolation or shallow trench isolation, the word line gate 645 (which functions as the split gate channel 618 in the transistor 600b) is shown in FIG. 11A, where the height of the polysilicon 645 is about 250 nm. Between 400 and 400 nm, the polysilicon is covered with a 100 to 200 nm dielectric layer 655. After the polysilicon is defined, a thin oxide (10
(５６20 nm) 656 is thermally grown on the poly sidewall, after which a thin nitride 657 is created by CVD deposition (FIG. 11B). The photoresist 661 is used to set a contact area. The nitride film 657 is isotropically etched by RIE using a photoresist mask, and ions such as arsenic are implanted to form an N + source junction. After removing the photoresist, the sidewall oxide (50-80 nm) 65 of FIG.
8, a thermal oxide film several times thicker than that of 656 of the polysilicon gate 645 on the opposite side is selectively thermally grown in the contact hole region.

The oxide at the bottom of the contact hole is etched by vertical RIE, during which the nitride 656 on the floating gate side prevents oxidation of the lower part and also serves as an etch stop when etching the oxide film on the junction N + 604. 180 to 20 for polysilicon 670
There is a thickness of 0 nm, and when deposited, FIG.
D is shown by the dotted line.

A vertical dry etch is performed to form sidewall spacers 672 that define the horizontal channel length 610 on the floating gate. When 0.3 μm lithography is used, the gate width and space 645 are 0.3
μm and the contact hole after the thick sidewall oxidation 658 is on the order of 0.25 μm. Therefore, contact hole 671 is still completely filled with polysilicon 670 even after polysilicon sidewall etch when polysilicon 670 is thicker than 150 nm. The buried polysilicon is used to form a self-aligned contact. After etching the polysilicon spacer, the N-drain 62 is removed.
Phosphorus for 0 is implanted at 50.100 KeV in an amount of 1E14-7E15 per cm ² . The thin nitride layer 657 is then etched vertically using the polyspacer 672 as an etch mask. The cross section here is as shown in FIG. 11D. One of the unique features of this process is to provide a self-aligned borderless contact that fills the contact hole while creating a horizontal channel in one polysilicon devotion. The photoresist 662 of FIG. 11E is used to protect the polysilicon in the contact holes during the removal of the self-aligned sidewall polysilicon. A thin nitride 657 is etched using the sidewall polysilicon as a mask. Next, using the thin nitride 657 as a mask, the thermal oxide 656 is etched, and then the substrate is dry-etched to form a vertical step of about 50 nm. Next, thermal oxide is formed,
Thereafter, the nitride 657 is selectively and isotropically removed by chemical dry etching. The sectional view at this point is 11E. After removing the photoresist 662, the oxide 6 is removed.
Reference numeral 56 denotes wet etching with a thin HF solution. The thermal oxide (50-100 nm) is again applied to the channel region 620.
On the sidewalls of polysilicon 630 (the oxide on the sidewall poly is slightly thicker than on a single crystal silicon substrate). The oxide layer is nitrided in an N ₂ O environment and then oxidized repeatedly to minimize pinholes.

Thin CV instead of nightization
A nitride layer of D (about 6 nm) may be deposited. Then the floating gate polysilicon is converted to CV
Conformally deposit by D and etch vertically by RIE as shown in FIG. 11F. The thickness of the polysilicon determines the dimensions of the sidewall, which determines the length of the floating gate. Since the thickness of the CVD can be very precisely controlled (within 5%), the dimensions of the horizontal channel length and the Ln length are very precisely set. By using these two side wall processes, it is possible to exactly meet the design goal. Night Lighting and Poly Sidewall Oxide 6
The purpose of the nitride layer on 30 is to improve the retention time and to reduce the leakage current between the word gate 645 and the floating gate 640. Silicon nitride may be replaced with silicon-rich silicon oxide to reduce tunnel erasing voltage. Separation of cells adjacent to floating gate of sidewall poly,
The contact poly is simultaneously separated by reactive ion etching as shown by 640S and 671S in FIG. This is followed by thermal oxidation of the polysilicon floating gate, CVD oxide deposition, and nitride composite layer 629. The purpose of the composite layer 629 is to protect the floating gate polysilicon 640 from contamination and moisture. Here is the normal process: deposition of passivation layer such as phosphosilicate glass (PSG), flattening by CMP, drilling of contact holes, filling of contact holes with tungsten, aluminum or copper, and wiring Metallization. FIG. 11G shows a cross-sectional view after this step is completed. FIG. 11H shows the memory cell viewed from above.
With this simple process, the structure of the step channel / n-drain region can be achieved in a self-aligned manner.

In this manner, the channel length, the horizontal channel, and the length of the step N-drain under the floating gate of the split gate can be accurately and finely formed by using the sidewall technique. The polysilicon used to set the horizontal channel below the floating gate is also used to fill the self-aligned contact holes.

[0105]

Embodiment: Manufacturing method of a stepped split gate transistor having a small side gate FIG. 12A to FIG. 12C show a manufacturing method of a variation of a split gate transistor 600c having a stepped channel / drain structure. Here, the horizontal channel length under the floating gate is 100 nm or less and the conventional horizontal channel length (15
(0 nm or more). The process for these two transistors is very similar.

After device isolation by LOCOS isolation or shallow trench isolation, the word line gate 645 (the split gate channel 618 of the transistor 600b).
11A) is set as shown in FIG. 11A, but the height of the polysilicon 645 is about 250 n.
m is between 400 nm and 400 nm.
It is covered with a 0 to 200 nm dielectric layer 655. Then, a thin oxide film (10-20 nm) 656 is thermally grown on the polysilicon sidewall, and a thin silicon nitride 657 is formed.
Is deposited by CVD as shown in FIG. 11B. Here, the thickness of the nitride determines the length of the horizontal channel (100 nm or less). Photoresist 661
Is used to protect the contact area. The nitride film 657 is isotropically etched by RIE using a photoresist mask, ions of arsenic or the like are implanted, and
+ Form a source junction.

After removing the photoresist, the sidewall oxide (50-80 nm), 658 in FIG. 11C, is selectively thermally grown in a contact region several times thicker than the 656 of the polysilicon gate 645 on the opposite side. The oxide at the bottom of the contact hole is vertically etched by RIE. During this time, the nitride 657 prevents oxidation of other regions and also serves as an etch stop during the etching of the oxide on junction N + 604. Then, as shown by the dotted line in FIG.
0 is deposited. A directional dry etch is performed to form the sidewall spacers 672. When using 0.3μm lithography, gate width and space 645 become 0.3μ
m. The contact hole after the thick sidewall oxidation 658 is then about 0.25 μm. Therefore, the contact hole 671 is made of 150 n of polysilicon 670.
If m or more, it is still completely buried after the poly sidewall etching. This buried polysilicon is used to form a self-aligned contact. Photoresist 662 is provided to protect the polysilicon in the contact holes when removing the sidewall polysilicon. Then, the nitride 657 is vertically etched, and FIG.
The nitride spacer indicated by the dotted line in FIG.
Used to set the thermal oxide below 6. The nitride 657 is then selectively removed by a chemical dry etch. Phosphorous per cm ² for N-drain 602 after setting nitride spacers 1E14.7E1
A dose of between 5 and 5 is implanted at an energy of 50-100 KeV. Continue the vertical dry etch of the silicon substrate to create a 50 nm step. The ion implantation of the N-drain may be performed after the step is formed. A cross-sectional view here is FIG. 12B. After removing the photoresist 662, the oxide 66 is removed.
5 is wet-etched with a diluted HF buffer solution. The thermal oxide film (50-100 nm) has a channel region 6
20 and on the sidewall polysilicon 630 are grown.
(The sidewall oxide film on poly is slightly thicker than on a single crystal silicon substrate.)

The oxide layer is nitrided in an N ₂ O environment and repeats oxidation to minimize pinholes. Instead of nitride, a thin CVD silicon nitride layer (about 6 nm) may be used. The floating gate polysilicon is then conformally deposited by CVD as shown in FIG.
Thereafter, a vertical etch by RIE is performed. The thickness of the polysilicon controls the sidewall dimensions, and the sidewall dimensions control the floating gate length. Since the thickness of the CVD is very precisely controlled (within 5%), the length of the horizontal channel and the length of Ln can be set very accurately by the two sidewall processes using nitride and polysilicon CVD. . The purpose of nitriding and forming a nitride layer on poly sidewall oxide 630 is to reduce leakage current between word gate 645 and floating gate 640 and improve retention time. The nitride film may be changed to a silicon-rich oxide to reduce the tunnel erase voltage. After the sidewall polyetch, the contact poly between the floating gate and the adjacent cell is simultaneously formed using a photoresist mask (conventional EEP).
Separate by careful reactive ion etching as shown at 640S and 671S in FIG. 11H (like the slit mask used in the ROM floating gate process).
This is followed by the thermal oxidation of the polysilicon floating gate and the nitride composite layer 629. The purpose of the composite layer 629 is to protect the floating gate polysilicon 640 from contamination and moisture.

Then follow the usual steps: deposition of a passivation layer such as PSG, flattening by CMP, filling of contact holes, and wiring metal steps. If you look at the memory cell from above,
Looks like H. Thus, a horizontal step channel / n-drain region can be achieved by self-alignment.

In this way, the channel length, the horizontal channel length below the floating gate of the split gate, and the N-drain length can be accurately set by using two side wall techniques.
Self-aligned contacts embedded in polysilicon have also been provided.

[0111]

Embodiment: Method of Manufacturing Trench Split Gate Transistor FIGS. 13A to 13G show a transistor-60.
The manufacturing method of 0d and 600e is shown, but 600e is a variation of the transistor -600d. Immediately after device isolation (shallow trench or LOCOS), a 50 nm thick nitride layer 65 is formed in the device region shown in FIG. 13A.
Two still remain. Source 60 of this nitride layer
4 and the drain 606 region (FIG. 13B) are removed using a photoresist mask. Then, a CVD oxide film is deposited slightly thicker than the nitride film as shown by a dotted line in FIG. Flattening fills the holes on the diffusion layer and provides at least 50 nm thick oxide. In order to form a buried floating gate in the step region, the floating gate region is exposed by using a photoresist mask 662 as shown in FIG.
Etch silicon 100 nm to 300 nm with E. Step side wall 61 to achieve shallow junction 603 while adjusting the implantation amount of arsenic by different amounts and the inclination angle of implantation
In 3, but has a higher addition levels in the bottom of the step 602 becomes the surface concentration of between 5E17 cm ³ from 1E17 cm ^3, it is 5E19 cm ³ or less. Optionally, boron halo may be implanted slightly deeper than the shallow arsenic sidewall junction to increase the electric field at the corners of the horizontal and vertical planes, in which case this is the injection point.

After removing the photoresist mask 662, the surface of the stepped silicon is cleaned and a thin oxide film of 7 to 12 nm is thermally grown as shown in FIG. 13E. The polysilicon layer should then be slightly thicker than the depth of the step, but is conformally deposited by CVD as shown by the dashed line in FIG. 13E. The polysilicon layer is chemically polished (C
MP), and slightly lower the surface by dry RIE. The remaining buried polysilicon in the step region of FIG. 13E becomes a floating gate. After thermally growing a thin oxide film, the nitride film 652 is selectively removed by phosphoric acid (phosphoric acid) or chemical polishing. After cleaning the surface, the oxide film 628 (7 nm to 15 n
m thickness) is thermally grown on the coupling oxide 630 on the select channel gate 618 and the floating gate. The oxide film 630 on polysilicon is slightly thicker than the oxide film on the silicon substrate. This is because the growth rate of polysilicon doping is high. The oxide film is nitrided in a NO environment and lightly oxidized again to minimize pinholes. Instead of nitriding, use a nitride layer (about 6 nm) or silicon lithoxide by CVD.
Deposit may be made as shown in 3F. The polysilicon of the select gate is conformally deposited by CVD. As shown in FIG. 13G, the polysilicon layer is etched to separate the selection gate on the adjacent STI region. Thus, a memory transistor 600d is obtained. Then passivation, contact hole setting,
The usual FET process, called wiring, follows. FIG. 13H shows a memory cell viewed from above. Using the same process, except for the N + drain forming portion of the above design, a highly integrated cell 60
0e is obtained. A highly integrated memory array can be realized by arranging many 600e-type transistors in a convoluted manner.

[0113]

According to the present invention, the floating gate is placed perpendicularly to the horizontal plane in the direction of the velocity of the channel hot electrons, and the impurity distribution in the vertical channel is optimized.
By constructing the vertical step transistor structure, the horizontal electric field synergistic effect of the vertical gate and drain voltage and the non-scattering straight injection can significantly increase the efficiency of electron injection into the floating gate. It can be applied to low voltage, high speed EEPROM, Flash memory,
N can be written and erased simultaneously when the bit line voltage is selected.
VRAM is also possible.

[Brief description of the drawings]

FIG. 1A shows a prior art EP in which channel hot electrons are injected into a floating gate and programmed.
It is sectional drawing of a ROM cell. FIG. 1B is a cross-sectional view of a prior art split EPROM cell in which channel hot electrons are programmed by injection into a floating gate. FIG. 2 shows a stack E according to the prior art.
FIG. 4 is a cross-sectional view of a PROM cell, used to describe channel hot electron injection into the floating gate of the 'lucky electron model'. FIG. 3A is a cross-sectional view of a stacked EEPROM cell according to the prior art, erased by tunneling electrons from the floating gate to the source region. FIG. 3B is a cross-sectional view of a prior art triple polysilicon flash EEPROM that erases by tunneling from the floating gate to the erase gate. FIGS. 4A and 4B are cross-sectional views of a stacked gate EEPROM cell having a step channel / drain structure according to the first aspect of the present invention, in which channel hot electrons are straightened to a floating gate which is present perpendicular to the electron traveling direction. Injected through oxide. In a third aspect of the invention, electrons in the floating gate are removed by tunneling from the floating gate to the step drain diffusion. FIG. 4C is an angle measurement diagram of the step, and an appropriate angle is 30 degrees or more measured from the channel silicon surface in order to take the degree of integration into consideration. FIG. 5A is a cross-sectional view of a single-polysilicon EPROM cell having a stepped channel / drain structure according to the second aspect of the present invention, in which channel hot electrons are straightened into a floating gate existing perpendicularly to the electron traveling direction. Injected through oxide. FIG. 5B is a cross-sectional view of the capacitor, and the polysilicon gate is the EP of FIG. 5A.
It is electrically connected to the floating gate polysilicon of the ROM cell to provide a control / select (select) gate function. FIG. 5C is a cross-sectional view of an EPROM memory cell. The EPROM transistor 500a of FIG. 5A is a conventional FE that provides a memory transistor selection function.
It is connected in series with the T transistor 500c. FIG. 6A shows a step channel / channel related to the fourth aspect of the present invention.
Stacked EEPROM with large overlapping drain structure
Tunnel erasure is performed in a sectional view of a cell.
Here, the electrons on the floating gate are removed by tunneling from the floating gate to the control gate, in addition to the first feature that electrons on the floating gate are injected straight through the step channel oxide in the traveling direction. FIG. 6B
According to a fourth aspect of the present invention, there is provided a sectional view of a split gate EEPROM having a step channel / large overlapping drain structure, in which tunnel erasing is performed. Here, electrons on the floating gate are removed from the floating gate to the control gate by tunneling. The transistor operates as a non-volatile RAM with an appropriate design and conditions, which is the fifth feature of the present invention. FIG. 6C is a cross-sectional view of another split gate EEPROM cell structure having a step channel, which is a variation having the same operation function as the transistor 600b of FIG. 6B. 6D and 6E are variations of the double polysilicon split gate transistor of FIG. 6B with a step channel. FIG. 7A is FIG.
A, 6B, 6C, 6D, 6E transistors with simplified capacitance model for polytunnel erase EEP
This is for explaining the operation of the ROM and the nonvolatile (non-volatile) RAM. FIG. 7B is a table showing an example of voltage conditions for writing “φ” and “1” of the nonvolatile RAM related to the fifth feature of the present invention. FIG. 8A is a cross-sectional view of a triple polysilicon split gate EEPROM cell having a long vertical (step) channel in the floating gate related to the sixth aspect of the present invention, and the channel hot electrons are channels perpendicular to the direction in which electrons travel in a straight line. It is injected into the floating gate through the oxide. Electrons in the floating gate are removed by tunneling from the floating gate to drain diffusion (diffusion) or from the floating gate to the select gate. FIG. 8B is a cross section of a triple polysilicon split gate EEPROM cell which is a variation of the transistor of FIG. 8A, and is a vertical channel for a normal gate in accordance with the sixth aspect of the present invention, where hot electrons are also directed straight ahead. Is implanted into the floating gate through the horizontal channel oxide. Electrons in the floating gate are removed by tunneling from the floating gate to the drain diffusion. 9A and 9B are cross-sectional views illustrating a process for creating a self-aligned drain n-diffusion during a step channel formation step according to a seventh aspect of the present invention. 9C and 9D show FIGS. 4A, 5A,
FIG. 4B is a cross-sectional view of stack gate cell formation at various stages of the production process A. 10A to 10C show FIGS. 4B and 6B
5A to 5C are cross-sectional views of various stages of the production process of the split gate cell. FIGS. 11A to 11G are cross-sectional views during each production step during the formation of the split gate of FIG. 6C, where the floating gate width is at least 150 nm.
FIG. 11H is a cross-sectional view taken along line 11G-11G ′ of FIG. 11H. FIG. 11H is a top view of a split gate transistor having a step injection channel. 12A to 12C are cross-sectional views at various stages of the split gate transistor formation manufacturing process of FIG. 6C, where the horizontal floating channel is less than 100 nm. 13A to 13G show a transistor 600
FIGS. 4D and 4D are cross-sectional views at various stages of the production process of the transistor 600e. FIG. 13G shows line 13 in FIG. 13H.
It is sectional drawing which followed G-13G '. FIG. 13H shows a transistor 600d of the memory array after the process is completed.
FIG. 4 is a view of the device viewed from above.

Claims (43)

[Claims] 1. An electrically programmable memory device which can more efficiently inject channel hot electrons from a channel to a floating gate, having the following characteristics: a substrate having a channel between a source and a drain; A structure in which a floating gate layer of a conductive layer is provided on the channel region and a part of the source / drain, and a dielectric layer is provided between the substrate and the floating gate layer; Have both 2. The electrically programmable memory device of claim 1 wherein said horizontal and vertical portions are a horizontal channel and a vertical channel, wherein said vertical channel is adjacent to said drain region. Is adjacent to the source region, and when the device is operating, the electrons accelerated in the horizontal channel travel straight in the direction of motion and pass through the vertical channel oxide in the direction of travel. Providing for being injected into a vertical portion of the floating gate on a vertical channel 3. The electrically programmable memory device of claim 2 wherein said vertical channel has a depth of about 20 to 2
What is 00nm 4. The electrically programmable memory device of claim 2 wherein said vertical channel angle is between 30 degrees and 150 degrees as measured from a horizontal plane. 5. The electrically programmable memory device of claim 2, wherein the vertical channel under said floating gate is of N-type material, wherein 1E17 cm ³ to 1E.
Lightly doped between 19 cm ³ 6. The electrically programmable memory device of claim 1, wherein said horizontal channel extension is covered by another separate (non-floating) control gate; and said vertical step. The channels are covered by floating gates, whereby the horizontal and vertical channels are electrically controlled by two isolated gates. Electrons accelerated in the horizontal channel go straight in the direction of travel and are injected into the vertical floating gate 7. A single polysilicon EEPROM memory cell having the following characteristics: a conventional FET transistor and a floating gate device connected in series; said horizontal and vertical lines below a floating gate of the floating gate device. Having a step channel / drain, but the length of the step N-drain under the floating gate is intentionally lengthened to increase the coupling capacitance between the drains; and the horizontal channel / drain is normally 'on' thing 8. A single-polysilicon EEPROM memory cell having the following characteristics: a floating gate memory transistor having horizontal and vertical step channels /
One with a drain; and one with an external coupling capacitor; the gate of the capacitor being made of the same conductive material as the floating gate and connected together; "Off"; and the floating gate memory transistor is selected by applying a voltage to the diffusion layer, the other terminal of the coupling capacitor 9. A single-polysilicon EPROM memory cell device having the following characteristics: a floating gate memory cell transistor having a horizontal and vertical step channel / drain; and a coupling capacitor; Although the floating gate of the transistor is connected and may be smaller than the length of the horizontal portion of the length of the step N-drain below the floating gate, the coupling capacitor is used in the floating gate transistor Greater than at least; the horizontal channel is usually 'off'
The memory transistor can be selected by applying a voltage to the coupling capacitor 10. The EPROM memory cell of claim 9 wherein said step N of said floating gate memory transistor having a step channel / drain structure.
Erasing and programming operations are performed reliably on the same side of the junction, with N deeper than the source to withstand high voltages for tunneling from the floating gate to the N-drain diffusion.
-Lightly doping the drain junction 11. A double-polysilicon memory cell having the following characteristics: a horizontal and vertical floating stack gate memory transistor having a source, a drain and a channel for providing efficient electron injection from a channel to said floating gate. At the horizontal and vertical step junctions above the source so as to withstand the high voltage for tunneling from the floating gate to the N-drain diffusion (diffusion).
-Providing a reliable erase operation of said memory cell provided by lightly doping the drain junction; 12. A double polysilicon split gate E
A PROM memory cell having the following characteristics: a floating split gate memory transistor having a source, a drain and a channel, having a horizontal and vertical step channel / drain structure, and providing efficient electron injection from the channel to the floating gate. What to do; light doping to withstand high voltage for tunneling from floating gate to N-drain diffusion, and reliability of the memory cell at the horizontal and vertical step junction provided by deeper N-drain junction That provide a reliable erasure method 13. A double polysilicon floating gate transistor in a double polysilicon gate EPROM memory cell having a horizontal / vertical step channel / drain; having a structure for efficiently injecting electrons from said channel into said floating gate; There is a control gate; the length of the overlap on the floating gate over the N-drain diffusion is adjusted to be longer than the length of the horizontal channel; and the memory is tunneled from the floating gate to the control gate. What can erase cells 14. The single polysilicon EPR according to claim 9,
The word line selected by the OM memory cell is erased with a small erase block size, and unnecessary program erase cycles are minimized by the floating gate transistor, thereby improving the durability. 15. A double polysilicon stacked EPROM memory cell according to claim 11, wherein the length of the overlapping floating gate on the N-drain diffusion is adjusted to be longer than the length of the horizontal channel. Providing erase operation even when the junction is as shallow as the source junction 16. The double polysilicon split gate EPROM memory cell of claim 12, wherein the length of the overlapped floating gate on the N-drain diffusion is adjusted to be longer than the length of the horizontal channel and the drain junction. That provides an erase operation even if it is as shallow as the source junction 17. A non-volatile RAM capable of both low voltage programming and erasing from polysilicon to polysilicon and having the following characteristics: a substrate having source and drain regions and a channel between them; A floating gate layer overlying the source and drain regions and a portion of the channel, the structure including a dielectric layer and a conductor layer;
The channel below the floating gate has both horizontal and vertical portions; and a wordline select gate in a portion of the horizontal channel portion 18. A nonvolatile RAM according to claim 17, wherein a low voltage programming method and a polysilicon to polysilicon erasing operation method are provided simultaneously. 19. A triple-polysilicon electrically programmable memory device for more efficiently injecting electrons from a channel to a floating gate with the following characteristics: a substrate having a channel region between a source and a drain; Another polysilicon double layer polysilicon structure stacked with the floating gate on the vertical channel portion is present on a portion of the drain and a third layer is formed on the horizontal channel portion and a portion of the source. The presence of polysilicon, with a dielectric layer of a dielectric layer between the substrate and the polysilicon; and the vertical channel stack floating gate structure directly connected to the horizontal FET device and separated polysilicon. Accelerate in horizontal channel with gate Those electrons which utilizes the electron injection mechanism that is injected into the vertical floating gate 20. The triple polysilicon electrically programmable memory device of claim 19, wherein an extension of said horizontal polysilicon gate is provided on said floating gate, thereby storing on said floating gate. Electrons are erased and removed by tunneling from the floating gate to the horizontal polysilicon gate 21. A method of manufacturing an electrically programmable memory device in which electrons are efficiently injected from a channel to a floating gate, the method having the following characteristics: a substrate having a channel between a source and a drain; A structure having a floating gate layer of a conductive layer on the channel region and part of the source / drain, and having a dielectric layer between the substrate and the floating gate layer;
The channel below the floating gate has both horizontal and vertical portions; the edge of the N-drain is formed self-aligned to a vertical step; its N-region is lower than the source region 22. The electrically programmable memory device of claim 21, wherein said horizontal and vertical portions are horizontal and vertical channels, said vertical channels being adjacent to said drain region. The horizontal channel is adjacent to the source region;
When the device operates, the electrons accelerated in the horizontal channel travel straight in the direction of travel and are injected into the vertical channel lying perpendicular to the direction of travel and the vertical portion of the floating gate structure on the vertical channel. That provide 23. The method of claim 22, wherein the angle of the vertical channel is between 30 and 150 degrees measured from a horizontal plane. 24. The method of claim 23, wherein said vertical channel is formed by etching at an early stage of field effect device fabrication; its depth is 20 to 100 nm. 25. The vertical channel according to claim 2, wherein said vertical channel is formed by etching at an early stage of the field effect device manufacturing and has a depth of 20 to 300 nm.
Method 3 of electrically programmable memory 26. A vertical channel step is set using the same mask after the vertical channel formation; a channel / N self-aligned to the vertical channel step region using ions from the group consisting of phosphorus, arsenic, and antimony for implantation. 26. The method of electrically programmable memory of claim 25, forming a drain. 27. Forming a tunnel silicon oxide on said channel, patterning said first polysilicon layer to become said floating gate thereon, and forming a floating gate on said vertical channel step. 27. The method of claim 26, wherein forming. 28. The method of claim 27, wherein a stacked gate memory cell is formed. 29. The method according to claim 27, wherein the split gate memory cell is formed. 30. By patterning the first polysilicon layer to be the floating gate, a die electric layer deposited thereon, and a second polysilicon layer for the control gate thereon. 27. The method of claim 26 formed. 31. A method of forming an electrically programmable memory device that improves the efficiency of electron injection from a channel to a floating gate, having the following features: providing a semiconductor substrate having an isolated surface area; There is at least one isolation region between the source and drain regions; by etching the substrate to a desired depth between the source and drain, a vertical step is formed in at least one of the isolation regions; Implanting ions into the vertical steps to form an N region, which is adjacent to one of the source and drain regions;
The N-drain is self-aligned and formed at the end of the step, the N-drain being lower than the source; having a portion of the source and drain regions and a floating gate on the channel, the conductor of which (Floating gate poly) A layer consisting of a dielectric layer between the layer and the channel; and the channel below the floating gate has both horizontal and vertical portions 32. The method of claim 31, wherein a control gate is formed on the composite die electric layer on said floating gate; forming a polysilicon layer and patterning said polysilicon layer. The control gate of 33. The method of claim 31, wherein said horizontal and vertical portions are horizontal and vertical channels, wherein said vertical channel is adjacent to said drain region. The horizontal channel is adjacent to the source region, and during the operation of the device, the electrons accelerated in the horizontal channel are directed in the momentum direction to the vertical channel and the vertical portion of the floating gate on the vertical channel. , Go straight and inject, 34. The vertical channel has a depth of 20-3.
32. The electrically programmable memory method of claim 31, wherein the distance is between 00 nm. 35. The method of claim 31, wherein the angle of the vertical channel is between 30 and 150 degrees measured from a horizontal plane. 36. The electrically programmable memory method according to claim 31, wherein after the vertical channel is formed, the step of the vertical channel is set (defined) using the same mask. 37. The method of claim 31, wherein said floating gate is formed on said vertical channel, wherein said dielectric layer, said tunnel silicon oxide, is formed on said channel and said conductive layer is formed thereon. Forming a first polysilicon layer and patterning it into a floating gate 38. The method for forming a stacked gate memory cell according to claim 31. 39. The method according to claim 31, wherein the drain is at the bottom of the step. 40. A method of forming an electrically programmable memory device for more efficiently injecting electrons from a channel to a floating gate, the method comprising: having an isolation region on a surface of a semiconductor substrate; Forming a source region adjacent to the word line gate structure; forming a source region adjacent to the word line gate structure;
Forming a drain region but spaced from said source region; having a vertical step in said one isolation region, with said N-drain region on the substrate between said source and drain The vertical step is formed by etching to the depth; in the N-drain region, the lower drain region is formed by high-concentration ion implantation; Forming a source contact; forming a floating gate structure on the channel and a portion of the source and drain regions, the structure comprising a die electric layer and a conductor layer thereon; and forming a floating gate structure below the floating gate. The channel has both horizontal and vertical parts. 41. A method of forming an electrically programmable memory device capable of more efficient electron injection from a channel to a floating gate having the following characteristics: providing an isolation region on a surface of a semiconductor substrate; A channel region interposed between the source and drain regions; the source, drain and drain regions being lower than the surface of the isolation region; and the source and drain drains within the isolation region. A trench drain region is formed by etching into the substrate to a depth of 300 nm or more between the source and the drain, and a vertical step is formed by the trench; contacting the drain region Forming a vertical stepped N- region by ion implantation; Forming a floating gate structure on said channel, said structure including a die electric layer and a conductor layer thereon; said die electric layer being formed on said step and on said trench, and On the rick layer is the conductor layer polysilicon, which is deposited on the die electric layer inside and outside the trench; the polysilicon layer is used to complete the floating gate structure. The channel is flattened, leaving only that portion of the layer within the trench; and the channel below the floating gate has both horizontal and vertical portions. 42. The method according to claim 41, wherein said vertical channel is between 30 and 150 degrees measured from a horizontal plane.
Electrically programmable memory method 43. The method according to claim 43, wherein the vertical channel is 100-300.
42. The electrically programmable memory method of claim 41 formed by etching to a depth between nm.