JP2001168219A - Nonvolatile semiconductor storage device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a write speed, keeping an operation voltage low, in a MONOS-type memory transistor. SOLUTION: This device is equipped with a substrate 1, a channel formation region 1a for a semiconductor provided at the surface of the substrate, first and second impurity regions 2 and 4 made at the surface of the substrate with the channel formation region 1a in-between, a gate insulating film 6 including within a charge accumulating means (carrier trap) dispersed in the direction of interior of the face opposed to the channel formation area 1a and the direction of film thickness, and a gate electrode 8 provided on the gate insulating film 6. Charge is accelerated in the vertical direction to the substrate such as substrate hot electron, secondary collision ionized hot electron, or the like, or a step 1b is made at the surface of the channel formation region 1a. As a result, the charge accumulating means comes to be positioned in the direction of charge accumulation, and implantation efficiency rises.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge storage means (for example, a MONOS type or MNOS type) which is discretized planarly in a gate insulating film between a channel forming region of a memory transistor and a gate electrode. A charge trap in the nitride film, a charge trap near the interface between the top insulating film and the nitride film, or a small-diameter conductor, and electrically injects charges (electrons or holes) into the charge storage means. The present invention relates to a nonvolatile semiconductor memory device having a basic operation of storing and extracting data and a driving method thereof.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory is expected to be a large-capacity and small-sized information recording medium. Is being required. Therefore, compared with the nonvolatile semiconductor memory, the scaling property is good, and the writing speed of 100 μsec / cell is 1 time.
There is a need to improve the writing speed by an order of magnitude or more.

In a nonvolatile semiconductor memory, an FG (Floating Gate) in which charge storage means for storing charges is continuous in a plane.
In addition to the mold, the charge storage means is discretized in a plane, such as MONOS (Metal-Oxide-Nitride-Oxide Semicondu
ctor) type.

In a MONOS type nonvolatile semiconductor memory,
The nitride film [Six Ny (0
<X <1, 0 <y <1)] because carrier traps in the film or at the interface between the top insulating film and the nitride film are spatially dispersed (that is, in the plane direction and the film thickness direction) and spread. In addition to the tunnel insulating film thickness,
It depends on the energy and spatial distribution of the charge trapped by the carrier trap in the xNy film.

When a leak current path is generated locally in the tunnel insulating film, a large amount of charge leaks through the leak path in the FG type and the charge retention characteristic is apt to deteriorate, whereas in the MONOS type, the charge storage characteristic is reduced. Since the means is spatially discretized, local charges around the leak path only leak locally through the leak path, and the charge retention characteristics of the entire storage element are unlikely to deteriorate. Therefore, MO
In the NOS type, the problem of deterioration of the charge retention characteristics due to the thinning of the tunnel insulating film is not as serious as in the FG type. Therefore, the scaling property of the tunnel insulating film in a very small memory transistor having a very short gate length is MON
The OS type is superior to the FG type. Further, when charges are locally injected into the distribution plane of the carrier traps discretized in a plane, the charges are held without being diffused in the plane and in the film thickness direction unlike the FG type.

It is important to improve the disturb characteristics in order to realize a fine memory cell with a MONOS type nonvolatile memory. For this purpose, a tunnel insulating film having a normal thickness (1.6) is required.
nm to 2.0 nm).

[0007]

However, the conventional MO
In the NOS type non-volatile memory, increasing the thickness of the tunnel insulating film or reducing the operating voltage is becoming more and more disadvantageous for improving the writing speed. For this reason, in the conventional nonvolatile memory such as the MONOS type, when the reliability (for example, the data holding characteristic, the read disturb characteristic, or the data rewriting characteristic) is sufficiently satisfied,
The writing speed is limited to 100 μsec.

[0008] Considering only the writing speed, the injection method using channel hot electrons (CHE) tends to be faster than the FN tunneling over the entire channel. However, in a normal CHE injection method in which CHE is generated at the drain end, the injection efficiency is 1 × 10 ⁻⁶ , which is not sufficient. A source side injection type MONOS transistor in which CHE is injected from the source side in order to increase the injection efficiency has been reported (IEEE Electron Device Letter19,
1998, pp153), this source side injection type MONOS
The transistor has an operating voltage as high as 12 V at the time of writing and 14 V at the time of erasing, and has insufficient reliability such as read disturb characteristics and data rewriting characteristics.

As described above, in the conventional nonvolatile memory such as the MONOS type, there is a trade-off between the improvement of the writing speed and the reduction of the operating voltage and the securing of the reliability.
Overcoming this trade-off has been an important issue in developing a high-speed large-capacity nonvolatile memory from the viewpoint of embedding with a logic circuit in a system LSI which has been actively developed in recent years.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory transistor which performs basic operation by accumulating electric charges in a planarly discrete carrier trap or the like, such as a MONOS type, to maintain good reliability such as read disturb characteristics, and to operate properly. An object of the present invention is to provide a nonvolatile semiconductor memory device having a structure capable of improving a writing speed while keeping a voltage low, and a driving method thereof.

[0011]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device including a substrate, a semiconductor channel formation region provided on a surface of the substrate, and the channel formation region interposed therebetween. First and second impurity regions formed on the substrate surface and serving as a source or a drain during operation;
A gate insulating film provided on the channel formation region;
A gate electrode provided on the gate insulating film; and a gate electrode provided in the gate insulating film in a direction opposed to the channel formation region and in a film thickness direction, and provided in a direction in which electric charges are accelerated during operation. Charge accumulation means. The direction in which the charges are mainly accelerated may be either the horizontal direction or the vertical direction with respect to the substrate.

In the nonvolatile semiconductor memory device according to the first aspect, since the discrete charge storage means is provided in the direction in which the charge is accelerated, the momentum of the charge is easily maintained at the time of injection. For this reason, charges are efficiently injected into the charge storage means.

[0013] A nonvolatile semiconductor memory device according to a second aspect of the present invention is formed on a substrate, a semiconductor channel forming region provided on the surface of the substrate, and a substrate surface with the channel forming region interposed therebetween. First and second impurity regions serving as a source or a drain during operation; a gate insulating film provided on the channel formation region; a gate electrode provided on the gate insulating film;
Charge accumulation means discrete in an in-plane and film thickness direction facing the channel formation region, wherein the first impurity region is provided on the surface of the channel formation region relative to the second impurity region. Is provided with a step which is lowered.

Preferably, the charge storage means is formed around a gate insulating film portion between the step and the first impurity region. Preferably, the length in the channel direction above the step where the charge is accelerated (for example, the length from the end of the second impurity region of the channel forming region to the step) is equal to or less than the mean free path of electrons in the channel. Alternatively, the length is set to a range of a predetermined distance or less, for example, 50 nm or less, in which electrons in the channel can travel without being affected by impurity scattering.

In general, in a nonvolatile semiconductor memory device in which writing is performed by using hot electron injection, when a predetermined bias voltage is applied between a source and a drain, and when a predetermined writing voltage is applied to a gate electrode, the formation is performed. The electric charge (in this case, electrons) supplied from the source in the set channel is accelerated by an electric field. Charges (hot electrons) that gained high energy near the drain due to the acceleration
Are attracted to the electric field by the gate electrode and injected into the charge storage means.

In a nonvolatile semiconductor memory device according to a second aspect of the present invention, a step is provided on the surface of a substrate, and O
Charge accumulation means (carrier trap) inside NO film etc.
Is provided. Therefore, high-energy charges (for example, hot electrons) generated near the drain are efficiently and rapidly injected into the carrier trap without losing kinetic energy while maintaining the momentum (direction and magnitude). Second
The non-volatile semiconductor memory device according to the first aspect shows an embodiment of horizontal charge acceleration of the non-volatile semiconductor memory device according to the first aspect. If the length in the channel direction above the step where the charges are accelerated is, for example, 50 nm or less, the charges are ballistically transmitted through the inside of the channel almost without being influenced by impurity scattering or the like. Therefore, the efficiency and speed of charge injection are further increased.

According to a third aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a substrate; a semiconductor channel formation region provided on the surface of the substrate; and a semiconductor channel formation region sandwiching the channel formation region. First and second impurity regions serving as a source or a drain during operation; a gate insulating film provided on the channel formation region; a gate electrode provided on the gate insulating film;
Charge accumulation means which is discretized in a plane facing the channel formation region and in the film thickness direction, and wherein the gate electrode has charge accumulation means inside the channel formation region on the side of the first impurity region. A first gate electrode stacked via a first gate insulating film having no charge storage layer, and a second gate insulating film having charge storage means therein on the side of the channel formation region on the side of the second impurity region. A second gate electrode. Preferably, the second gate electrode is formed on a side wall of the first gate electrode via an insulating film.

In the nonvolatile semiconductor memory device according to the third aspect, the first gate electrode on the first impurity region side and the second gate electrode on the second impurity region side are separately provided.
Therefore, the gate voltage application condition at the time of acceleration and the gate voltage application condition at the time of injection can be set separately, and accordingly, control for maximizing the injection efficiency and speeding up the writing is easy. Since it is not necessary to form the charge storage means in the gate insulating film (first gate insulating film) on the first gate electrode side, the first gate insulating film can be made thinner to increase the acceleration electric field. If the acceleration electric field is kept constant, the applied voltage can be reduced. On the other hand, when the second gate electrode is of a sidewall type, the cell area can be small.

According to a fourth aspect of the present invention, there is provided a method for driving a nonvolatile semiconductor memory device, comprising: a substrate; a semiconductor channel formation region provided on the surface of the substrate; First and second impurity regions formed and serving as a source or a drain during operation, a gate insulating film provided on the channel forming region, a gate electrode provided on the gate insulating film, and the gate insulating film A method for driving a non-volatile semiconductor storage device, comprising: charge storage means that is discrete in an in-plane and film thickness direction facing the channel forming region.
The charge is accelerated in the channel formation region or the depletion layer in the periphery thereof, and injected into the discretized charge storage means while maintaining the momentum. Preferably, at the time of writing, partial charge injection is performed independently on the first impurity region side and the second impurity region side of the charge storage means. Specifically, writing is performed with the voltage application conditions reversed. In reading, preferably, a voltage application direction between the first and second impurity regions is determined so that a charge corresponding to information to be read is on the source side, a predetermined read drain voltage is applied, and a gate electrode is applied. A predetermined read gate voltage is applied. In the case of reading a plurality of bits, such reading is performed by reversing the voltage application direction between the first and second impurity regions. In erasing, charges injected from the first and / or second impurity regions and held in the charge storage means on one or both sides in the channel direction are individually or collectively collected by direct tunneling or FN tunneling. Pull out to the side.

According to a fifth aspect of the present invention, there is provided a method for driving a nonvolatile semiconductor memory device, comprising: a substrate; a semiconductor channel formation region provided on the surface of the substrate; First and second impurity regions formed and serving as a source or a drain during operation, a gate insulating film provided on the channel forming region, a gate electrode provided on the gate insulating film, and the gate insulating film A method for driving a non-volatile semiconductor storage device having charge accumulation means in the plane facing the channel forming region and discretized in the film thickness direction.
The charge is accelerated in the channel formed in the channel forming region, and injected into the discretized charge storage means using ballistic electric conduction.

According to a sixth aspect of the present invention, there is provided a method of driving a nonvolatile semiconductor memory device, comprising: a substrate; a semiconductor channel formation region provided on the surface of the substrate; First and second impurity regions formed and serving as a source or a drain during operation, a gate insulating film provided on the channel forming region, a gate electrode provided on the gate insulating film, and the gate insulating film A method for driving a non-volatile semiconductor storage device having charge accumulation means in the plane facing the channel forming region and discretized in the film thickness direction.
Hot electrons generated by secondary impact ionization are injected into the discretized charge storage means.

According to a seventh aspect of the present invention, there is provided a method of driving a nonvolatile semiconductor memory device, comprising the steps of: providing a substrate; a semiconductor channel formation region provided on the surface of the substrate; First and second impurity regions formed and serving as a source or a drain during operation, a gate insulating film provided on the channel forming region, a gate electrode provided on the gate insulating film, and the gate insulating film A method for driving a non-volatile semiconductor storage device having charge accumulation means in the plane facing the channel forming region and discretized in the film thickness direction.
The charge is accelerated in the depletion layer formed in the channel forming region, and is converted into hot electrons in the substrate and injected into the discrete charge storage means.

According to an eighth aspect of the present invention, there is provided a method for driving a nonvolatile semiconductor memory device, comprising: forming a substrate, a semiconductor channel formation region provided on the surface of the substrate, and forming the semiconductor channel formation region on the substrate surface with the channel formation region interposed therebetween. The first and second impurity regions serving as a source or a drain during operation, a gate insulating film formed on the channel forming region, a gate electrode formed on the gate insulating film, and Discretely formed in the opposing surface and in the film thickness direction, and formed in the gate insulating film, and caused by channel hot electrons, ballistic hot electrons, secondary impact ionization hot electrons, substrate hot electrons, or interband tunnel current during operation. Of a nonvolatile semiconductor memory device having charge storage means into which hot electrons are injected In erasing, charges injected from the first and / or second impurity regions and held in the charge storage means on one or both sides in the channel direction are individually separated by direct tunneling or FN tunneling. Alternatively, pull them all together toward the substrate.

In the method of driving a nonvolatile semiconductor memory device according to the fourth to seventh aspects, for example, channel hot electron injection through a step, charge injection using ballistic conduction, secondary collision ionization hot electron injection, or substrate injection Since hot electron injection is used, the efficiency of charge injection is high, and sufficiently high-speed writing is possible even at a low operating voltage. In the present invention, by appropriately selecting the injection method, the direction in which the electric charge is accelerated can be made vertical in addition to the horizontal direction with respect to the substrate. Can also be partially injected. In addition, in the method of driving the nonvolatile semiconductor memory device according to the eighth aspect, erasing is performed by extracting charges to the substrate side by tunneling, so that a large amount of holes exist in the bottom insulating film during the erasing operation as in the related art. Never move to. Note that the present invention relates to a MONOS or MNOS type or the like including a nitride film or an oxynitride film on a bottom insulating film in a gate insulating film, or a small-grain conductive material insulated from the bottom insulating film in a gate insulating film. It is suitable for a small particle size conductor type including a body.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a schematic configuration of a memory cell array of a source line isolated NOR type nonvolatile semiconductor memory according to an embodiment of the present invention.

In this nonvolatile memory device, each memory cell of the NOR type memory cell array is a memory transistor 1
It is composed of individual pieces. As shown in FIG. 1, memory transistors M11 to M22 are arranged in a matrix, and these transistors are wired by word lines, bit lines, and separated source lines. That is, each drain of the memory transistors M11 and M12 adjacent in the bit direction is connected to the bit line BL1, and each source is connected to the source line S1.
L1. Similarly, each drain of memory transistors M21 and M22 adjacent in the bit direction is connected to bit line BL2, and each source is connected to source line SL2.
It is connected to the. Each gate of the memory transistors M11 and M21 adjacent in the word direction is connected to the word line WL.
1, and similarly, each gate of the memory transistors M12 and M22 adjacent in the word direction is connected to the word line WL2.
It is connected to the. In the entire memory cell array, such cell arrangement and connection between cells are repeated.

FIG. 2 is a schematic plan view of the fine NOR type cell array according to the first embodiment. FIG. 3 is a bird's-eye view as viewed from a cross-sectional side along the line AA ′ in FIG.

In this fine NOR type memory cell array,
As shown in FIG. 3, an n-type or p-type semiconductor substrate SUB
An element isolation insulating layer ISO is formed on the surface of an n-well or a p-well by a trench or LOCOS. As shown in FIG. 2, the element isolation insulating layers ISO are arranged in a parallel stripe shape that is long in the bit direction (vertical direction in FIG. 2). Each of the word lines WL1, WL2, WL3, WL4,... Is substantially orthogonal to the element isolation insulating layer ISO.
Are wired at equal intervals. As will be described later, this word line is formed by laminating a gate insulating film composed of a bottom insulating film, a nitride film, and a top insulating film, and a gate electrode.

In the active region within the space between the element isolation insulating layers ISO, the substrate 101 is provided in the space between the word lines.
And a source impurity region (second impurity region) S and a drain impurity region (first impurity).
Impurity regions) D are formed alternately. The source impurity region S and the drain impurity region D have an element isolation insulating layer ISO in the word direction (the horizontal direction in FIG. 2).
And only the word line interval in the bit direction. Therefore, since the source impurity region S and the drain impurity region D hardly introduce a mask alignment error with respect to variations in size and arrangement,
It is formed very uniformly.

The upper part and the side wall of the word line are covered with an insulating layer. That is, the offset insulating layers are arranged in the same pattern above the word lines WL1, WL2,.
Sidewall insulating layers are formed on both side walls of a laminated pattern including an offset insulating layer, a gate electrode (word line) thereunder, and a gate insulating film. By the offset insulating layer and the side wall insulating layer, an elongated self-aligned contact hole is opened in the space between the word lines along the word line.

A conductive material is alternately embedded in the self-aligned contact hole so as to partially overlap the source impurity region S or the drain impurity region D, thereby forming a bit contact BC and a source contact SC. In forming these contacts BC and SC,
A conductive material is deposited so as to fill the self-aligned contact hole, and a resist pattern for an etching mask is formed thereon. At this time, the resist pattern is slightly larger than the width of the self-aligned contact hole.
A part is overlapped on the element isolation insulating layer ISO. Then, using the resist pattern as a mask, the conductive material around the resist pattern is removed by etching. This gives 2
Kinds of contacts BC and SC are formed simultaneously.

The recess around the contact is buried with an insulating film (not shown). The bit lines BL1, BL2,... Contacting on the bit contact BC and the source lines SL1, SL contacting on the source contact SC are formed on the insulating film.
Are alternately formed in parallel stripes.

In this fine NOR type cell array, formation of a contact to the bit line or source line is achieved by forming a self-aligned contact hole and forming a plug. In the formation of the self-aligned contact hole, the isolation from the word line is achieved, and the exposed surface of the source impurity region S or the drain impurity region D is formed uniformly. The bit contact BC and the source contact SC are formed on the exposed surface of the source impurity region S or the drain impurity region D in the self-aligned contact hole. Therefore, the size of the plug contact surface of each plug in the bit direction is substantially determined by the formation of the self-aligned contact hole, and the contact area varies accordingly.

It is easy to isolate the bit contact BC or the source contact SC from the word line. That is, an offset insulating layer is formed at once when forming a word line, and thereafter, a sidewall insulating layer is formed only by forming an insulating film and etching the entire surface (etchback). In addition, since the bit contact BC and the source contact SC, and furthermore, the bit line and the source line are formed by patterning conductive layers in the same layer, the wiring structure is extremely simple, the number of steps is small, and the manufacturing cost is low. It has an advantageous structure to suppress. In addition, since there is almost no wasted space, when each layer is formed at the minimum line width F at the wafer process limit, it can be manufactured with a very small cell area close to 8F ² .

FIG. 4 is a sectional view showing the element structure of the MONOS type memory transistor according to this embodiment.

In FIG. 4, reference numeral 1 denotes a semiconductor substrate SUB or well (hereinafter referred to as a substrate) such as a silicon wafer having n-type or p-type conductivity, 1a denotes a channel formation region,
2 and 4 indicate a source impurity region S and a drain impurity region D of the memory transistor. In the present invention, the “channel forming region” refers to a region where a channel through which electrons or holes conduct is formed inside the surface side. The “channel formation region” in this example corresponds to a portion between the source impurity region 2 and the drain impurity region 4 in the substrate.

The source impurity region 2 and the drain impurity region 4 are regions having a high conductivity formed by introducing an impurity of a conductivity type opposite to that of the channel formation region 1a into the substrate 1 at a high concentration. is there. Normally, an LDD (Lightly Doped Dr.) is formed at a substrate surface position facing the channel formation region 1a of the source impurity region 2 and the drain impurity region 4.
ain) is often provided.

On the channel forming region 1a, a gate electrode 8 of the memory transistor is laminated via a gate insulating film 6. In general, the gate electrode 8 is made of polysilicon made conductive by introducing p-type or n-type impurities at a high concentration.
(doped poly-Si) or a laminated film of doped poly-Si and high melting point metal silicide. The length (gate length) of gate electrode 8 in the channel direction is 0.25 μm or less, for example, about 0.18 μm.

The gate insulating film 6 in this embodiment is composed of a bottom insulating film 10, a nitride film 12, and a top insulating film 14 in order from the lower layer. As the bottom insulating film 10, for example, an oxide film is formed, and this is used after nitriding.
The thickness of the bottom insulating film 10 is 2.0 n in accordance with the intended use.
It can be determined within a range from m to 5.0 nm, and is set to 5.0 nm here.

The nitride film 12 is composed of, for example, a 5.0 nm silicon nitride (Six Ny (0 <x <1, 0 <y <1)) film. This nitride film 12 is, for example,
Fabricated by VD (LP-CVD), contains a lot of carrier traps in the film, Pool Frenkel type (PF type)
Shows the electrical conduction characteristics of

The top insulating film 14 needs to form deep carrier traps in the vicinity of the interface with the nitride film 12 at a high density. Therefore, the top insulating film 14 is formed, for example, by thermally oxidizing the formed nitride film. Further, the top insulating film 14 is made of HTO (High Tem).
It may be a SiO ₂ film formed by the method of (perature chemical vapor deposited oxide). Top insulating film 14 is C
When formed by VD, this trap is formed by heat treatment. The thickness of the top insulating film 14 must be at least 3.0 nm, preferably at least 3.5 nm, in order to effectively prevent holes from being injected from the gate electrode 8 and to prevent the number of times data can be rewritten. It is. Here, the top insulating film has a thickness of 3.5 nm.

In manufacturing a memory transistor having such a configuration, first, an element isolation insulating layer ISO and a well W are formed on a prepared semiconductor substrate, and ion implantation for adjusting a threshold voltage is performed as necessary. After that, the gate insulating film 6 is formed. Specifically, for example, heat treatment is performed at 1000 ° C. for 10 seconds by a short-time high-temperature heat treatment method (RTO method) to form a silicon oxide film (bottom insulating film 10). Next, a silicon nitride film (nitride film 12) is formed on the bottom insulating film 10 by the LP-CVD method to a final film thickness of 5 nm.
Is deposited to be thicker than this. This CVD
Is performed at a substrate temperature of 650 ° C. using, for example, a gas obtained by mixing dichlorosilane (DCS) and ammonia. The surface of the formed silicon nitride film is oxidized by a thermal oxidation method to form, for example, a 3.5 nm-thick silicon oxide film (top insulating film 1).
4) is formed. This thermal oxidation is performed, for example, in a H ₂ O atmosphere at a furnace temperature of 950 ° C. As a result, a deep carrier trap having a trap level (an energy difference from the conduction band of the silicon nitride film) of about 2.0 eV or less is formed at a density of about 1 to 2 × 10 ¹³ / cm ² . Also,
The thermal silicon oxide film (top insulating film 14) is formed to a thickness of about 1.6 nm with respect to the nitride film 12 having a thickness of 1 nm, and the nitride film thickness of the base decreases at this ratio, and the final film thickness of the nitride film 12 becomes 5 nm.

A laminated film of a conductive film serving as the gate electrode 8 and an offset insulating layer (not shown) is laminated. Then, the laminated film of the gate insulating film 6, the conductive film, and the offset insulating layer is collectively processed in the same pattern. Source and drain impurity regions 2 and 4 are formed by ion implantation in a self-aligned manner with the formed laminated pattern.

Subsequently, in order to obtain the memory cell array structure of FIG. 3, a self-aligned contact hole is formed together with the sidewall insulating layer, and the source and drain impurity regions S and D (source and drain) exposed by the self-aligned contact hole are formed. A bit contact BC and a source contact SC are formed on the impurity regions 2 and 4). After that, the area around these contacts is buried with an interlayer insulating film,
Bit lines BL1,... And source lines SL are formed on the interlayer insulating film.
After forming 1,..., The non-volatile memory cell array is completed through formation of an upper layer wiring via an interlayer insulating layer, overcoat film formation, and pad opening step, if necessary.

Next, a description will be given of a bias setting example and an operation of the nonvolatile memory having such a configuration at the time of writing, with a case where data is written to the memory transistor M11 as an example. In the present embodiment, writing is performed using hot electrons generated by secondary impact ionization. In the secondary impact ionization hot electron injection, when a hole, which is a substrate current generated near the drain, is injected into the substrate across the depletion layer near the drain, the electron receives energy from the electric field in the depletion layer, and electrons and positive electrons are injected. Hole pairs are generated, and the generated electrons are accelerated mainly in the vertical direction by the electric field and injected into the charge storage means.

At the time of writing, in FIG.
0 V is applied to the source impurity region 2, 3.3 V to the drain impurity region 4, 5 V to the gate electrode 8, and 3 V to the well 1. Under this condition, holes injected from the drain impurity region 4 and entering the nearby depletion layer collide with silicon atoms, and the collision generates an electron-hole pair in the depletion layer. Among them, holes are dissipated to the substrate side with a lower potential, but electrons are accelerated by the electric field between the gate electrode and the substrate and accelerated upward through the depletion layer. Due to this acceleration, the electrons become hot electrons, and a part of the electrons cross the energy barrier of the bottom insulating film 10 and are injected into the charge storage means (carrier trap) in the nitride film 12. At this time, the distribution of injected electrons is localized on the side into which holes that cause collision are injected, that is, on the first region in FIG. Therefore, when the threshold voltage of the memory transistor M11 is in the erased state, it rises to the written state, and writing is performed. Page writing is possible for a plurality of memory cells connected to the selected word line by appropriately setting the writing and the writing inhibition by changing the voltage application condition.

In reading, the bias value is changed to such an extent that a channel is formed according to the writing state. For example, with the drain impurity region 4 grounded, 1.5 V is applied to the source impurity region 2 and 2 V is applied to the gate electrode 8. Accordingly, in the case of page reading, a channel is formed in an erased memory transistor in which electrons have not been injected into the first region of the charge storage means, and a write state memory in which electrons have been injected into the first region of the charge storage means. No channel is formed in the transistor. Therefore, a potential change appears on bit lines BL1,... Depending on whether or not the channel is formed. When this potential change is detected by the sense amplifier, the stored data in the page is read out collectively.

The erasing is performed by extracting charges from the entire surface of the channel or from the drain impurity region 4 side by using FN tunneling or direct tunneling.

On the other hand, when the same writing is performed on the source impurity region side of the charge storage means in order to store 2-bit data in one cell, in the second writing, the source and the drain are applied. The voltage is reversed from the first time. As a result, secondary impact ionization similar to the first time occurs on the source impurity region side, and the generated electrons are injected into the region (third region) on the source impurity region side of the charge storage means.
In a cell in which both bits are written, hot electrons are injected and held in the first region of the charge storage means,
Independently, hot electrons are injected and held in the third region. That is, since the second region into which the hot electrons are not injected is interposed between the first region and the third region of the charge storage means, the hot electrons corresponding to the two-bit information are surely distinguished.

The reading of the charges held in the third region is performed as follows.
The operation is performed by reversing the voltage direction between the source and the drain as compared with the case of the charges in the first region. Thus, 2-bit data can be read independently. The erasing is also performed by reversing the voltage applied to the source impurity region 2 and the drain impurity region 4 in the first region. When erasing is performed on the entire channel, the source and drain impurity regions 2 and
4 have the same potential as the substrate, so that the
The data in the area is erased collectively.

The current-voltage characteristics of the memory transistor in the written state and the erased state were examined. As a result, the off-leak current value from a non-selected cell at a drain voltage of 1.5 V was about 1 nA. The read current in this case is 1
Since the current is 0 μA or more, no erroneous reading of unselected cells does not occur. Therefore, M having a gate length of 0.18 μm
It has been found that the ONOS type memory transistor has a sufficient margin for the punch-through withstand voltage at the time of reading.
In addition, the read disturb characteristic at a gate voltage of 1.5 V was also evaluated, and it was found that reading was possible even after a lapse of 3 × 10 ⁸ sec or more.

It was found that the number of times of data rewriting was satisfactory because the carrier traps were spatially discretized, and satisfied 1 × 10 ⁶ times. The data retention characteristic is 1
After x10 ⁶ data rewrites, 85 ° C for 10 years was satisfied.

As described above, a MON having a gate length of 0.18 μm
It was confirmed that sufficient characteristics were obtained as an OS type nonvolatile memory transistor.

In the secondary impact ionization hot electron injection method according to the present embodiment, hot electrons can be injected into the charge storage means discretized with a relatively low drain current. Therefore, punch-through during writing is suppressed as compared with normal hot electron injection, and as a result, there is an advantage that scaling of the gate length is easy. In addition, since the charge is mainly accelerated in the direction perpendicular to the substrate, the injection is performed while the momentum of the accelerated charge is maintained. Therefore, the charge injection efficiency is higher than that of the normal CHE injection method.

Second Embodiment The second embodiment relates to a virtual ground NOR type nonvolatile memory device. The virtual grounding type is roughly classified into a split gate type and an AMG (Alternate Metal Virtual Ground) type. The split gate type prevents the write disturbance by providing the function of the selection transistor substantially in the memory transistor. In the AMG type, writing of adjacent cells is performed by connecting every other diffusion layer wiring composed of a semiconductor impurity region to a metal wiring and selecting, for example, a metal wiring as a bit line and a diffusion layer wiring between the metal wirings as a source line. Prevent disturb.

FIG. 5 is a circuit diagram showing an AMG type memory cell array configuration of the virtual ground NOR type. In this memory cell array, a source line is shared between adjacent memory cells. This common source line functions as a bit line when operating an adjacent memory cell. Therefore, in this memory cell array, all the wirings in the bit direction are called "bit lines". Each bit line BL1-B
L3 is a diffusion layer wiring made of a semiconductor impurity region. Every other one, for example, bit lines BL1 and BL3
Are connected to an upper metal wiring via a bit contact (not shown).

As described above, except that the cell array structure is different,
The basics of the MONOS type memory transistor structure and the write, read and erase operations are the same as in the first embodiment. In the case of the virtual ground NOR type, since the source line is used instead of the bit line of the adjacent cell, the size in the bit direction can be reduced as compared with the isolated source line type, and a cell area of 6F ² can be achieved. Two bits of data can be physically recorded in one memory cell. In this case, the cell area per bit is effectively 3F ² .

Third Embodiment In this embodiment, channel hot electrons (CH
E) Injection writing and tunnel erasing of the entire channel are performed. Writing is a normal CHE injection, and the details are omitted here.

When the memory transistor has the same configuration as that of FIG. 4 and electrons held in the first region of the charge storage means are directly extracted from the entire channel by tunneling, 0 V is applied to the gate electrode 8 and 8 V is applied to the drain impurity region 4. The source impurity region 2 is opened, and a voltage of 8 V is applied to the well 1. As a result, the electrons held in the first region of the charge storage means are extracted toward the substrate, thereby performing cell erasure. At this time, the erasing speed was about 1 msec. When erasing the charge in the third region, the first region
The erasing on the region side is performed by reversing the voltage applied to the source impurity region 2 and the drain impurity region 4. Furthermore, the first and third
When charge is held in the region, when erasing is performed on the entire surface of the channel, the source and drain impurity regions 2 and 4 are both set to the same potential as the substrate, so that the data on the first region side and the third region side are transferred. It may be erased all at once.

In this erasing method, the amount of holes passing through the bottom insulating film 10 during operation is much smaller than that of hot hole injection or the like, so that the bottom insulating film 10 is hardly deteriorated, and its reliability and durability (for example, Lance characteristics).

Fourth Embodiment In a fourth embodiment, a high-speed writing method using a substrate hot electron injection phenomenon will be described by taking a MONOS type memory transistor as an example.

In the substrate hot electron injection method, a source and a drain are applied at the same potential, and a substrate bias voltage is applied to form a thick depletion layer under the gate electrode. (Electrons) are injected. The injected electrons are accelerated in the depletion layer to obtain energy equal to or higher than the barrier energy of the insulating film, and are injected into the charge accumulating means that is planarized beyond the insulating film, whereby writing is performed. .

The first configuration of the MONOS type memory transistor according to the present embodiment is the same as that of the first embodiment shown in FIG. In the present embodiment, the basic configuration is the same as that of the first embodiment, but each constituent film 1 of the gate insulating film 6 here.
0, 12, and 14 are set to, for example, 3/5 / 3.5 nm. The fabrication of the gate insulating film 6 and the fabrication of the memory cell are performed using the same apparatus and process conditions as in the above-described embodiment.

Next, the operation of the memory cell will be described. An AC bias voltage is applied to the pn junction between the source impurity region 2 and the well 1 so that the pn junction is alternately biased in the forward and reverse directions. In this case, when the pn junction is forward biased, electrons are injected into the p well 1 from the pn junction. The channel forming region in the well is depleted by the substrate bias. For this reason, electrons injected from the pn junction are accelerated by the positive bias voltage applied to the gate, exceed the barrier potential of the bottom insulating film 10, and are injected into the carrier trap in the nitride film 12 serving as charge storage means by hot carriers. Thus, writing is performed.

For example, with the drain open and the well potential maintained at 0 V, the gate electrode 8 is supplied with a positive bias voltage of 5 V and an AC bias voltage of the source impurity region 2.
, A pulse voltage of 0.7 V in the forward direction and V _CC in the reverse direction. In this case, hot carrier injection was performed at a high speed, and a write time of 1 μsec or less was realized at an operating voltage of 5 V or less. As for reliability, characteristics equivalent to those of a conventional MONOS type memory cell of the FN tunnel injection method were obtained.

Since the charge accumulating means is discretized in a plane, the injection condition of the substrate hot electrons is changed so that not only the injection to the entire surface of the nitride film 12 but also the
Partial injection into is possible. For example, as described above, in the injection from the source side, the charge is injected into the source side portion (first region) of the charge storage means. Conversely, the charge is stored by injecting the charge from the drain side as the source is open. Charge injection is possible in the drain side portion (third region) of the means. In the case of FIG. 4, a second region into which no charge is injected is formed between the first region and the second region.
It is possible to distinguish two bits of information. In addition, charge is locally extracted during erasing, and the threshold voltage of the second region where no charge is injected does not change. Therefore, excessive erasing is prevented, and the convergence of the threshold voltage in the erased state is prevented. There is an advantage that is high. On the other hand, for source and drain,
By applying the AC bias voltage at the same phase with a large voltage value, the first and third regions in FIG. 4 are connected, and charges can be injected into the entire charge storage means.

FIG. 6 shows a second structural example of the MONOS type memory transistor according to the present embodiment. The memory transistor shown in FIG. 6 has a double well structure. That is, the n-well 60 is formed on the p-type semiconductor substrate 1,
A p-well 61 is formed in the n-well 60, and a memory transistor is formed in the p-well 61. Other basic configurations are the same as those in FIG. However, the film thickness specifications of the constituent films 10, 12, and 14 of the gate insulating film 6 of this example are as follows.
It was 3.5 / 5/4 nm.

By forward-biasing the pn junction formed by the n-well 60 and the p-well 61, electrons are injected into the depleted channel formation region, and the electrons are accelerated by the electric field toward the gate electrode. Electrons are injected into a carrier trap in the nitride film 12.

For example, with the drain open, a gate voltage of 5 V and a source voltage V _CC were set, and 0.7 V was applied between the n-well 60 and the p-well 61 in the forward direction. As a result, when the operating voltage is 5 V or less, the write time
sec was achieved. As for the reliability of the memory cell, characteristics equivalent to those of the conventional MONOS memory cell of the FN tunnel injection method were obtained.

In the hot electron injection of the substrate, the operating voltage is as low as 5 V or less as in the case of the secondary impact ionization.
There is an advantage that the injection efficiency is high because the acceleration is mainly performed perpendicular to the substrate.

Fifth Embodiment In the fifth embodiment, a step is provided in the channel formation region, and CHE implantation is performed from this step. FIG. 7 is a sectional view of a MONOS memory transistor according to the fifth embodiment.

This memory transistor differs from the memory transistor according to the first embodiment shown in FIG. 4 in that a step 1b is provided on the surface of the substrate in the channel forming region 1a. The step 1b has a height of about 5 to 50 nm, for example, 10 nm, and is formed to be relatively high on the source impurity region 2 side and low on the drain impurity region 4 side. Other configurations are the same as in the first embodiment. However, here, each constituent film 1 of the gate insulating film 6 is used.
The film thickness specifications of 0, 12, and 14 were set to 3.5 / 8.0 / 3.5.
nm.

In the manufacture of the memory transistor having such a configuration, the difference from the first embodiment is that a step 1b is formed. The details will be described in an embodiment described later.

Next, the CHE injection / write operation to the nonvolatile memory having such a configuration will be described by taking as an example a case where data is written to the memory transistor M11 in FIG.

At the time of writing, a program inhibit voltage is set as required, and then a program voltage is applied. For example, 5V is applied to the selected bit line BL1, and a predetermined voltage, for example, 3V, is applied to the unselected word line WL2, the unselected source line SL2, and the unselected bit line BL2 when the substrate potential is 0V. Also, the selected source line SL1
Are kept at the ground potential 0V. In this state, when the substrate potential is 0 V, a predetermined voltage, for example, 7 V is applied to the selected word line WL1.

Under this writing condition, the source impurity region 2
An inversion layer (channel) is formed on the surface of the channel formation region between the gate electrode and the drain impurity region 4, and electrons are injected into the channel from the source impurity region 2 side to accelerate the electric field. The accelerated electrons become hot electrons near the horizontal channel edge, and a part of the electrons are injected into the gate insulating film 6 with high energy through the potential barrier of the bottom insulating film 10 and are captured by carrier traps in the gate insulating film 6. Therefore, the threshold voltage of the memory transistor M11 increases from the erased state to the written state, and writing is performed.

In the transistor structure according to the present embodiment,
A step 1b is provided in the middle of the channel forming region 1a, and the gate insulating film 6 extends on the bottom side of the step 1b. Therefore, if the height of the step 1b is optimized in accordance with the specification of the thickness of the gate insulating film 6, the carrier traps on an extended line in the traveling direction of electrons or on a trajectory bent by an electric field due to the voltage applied to the gate electrode 8. Can be located. That is, in the writing of the memory transistor according to the present embodiment, it is possible to directly inject the electrons into the carrier trap while substantially maintaining the momentum (magnitude and direction) of the field-accelerated electrons. Therefore, energy loss at the time of injection is reduced as compared with the conventional case, and high-speed and efficient charge injection can be performed. As a result, a higher writing speed is achieved.

In the conventional channel hot electron injection, the charge that has jumped out of the channel due to scattering after being excited by energy is attracted to the carrier trap side by the electric field, so that the injection efficiency is 1 × 10 ⁻⁶ and 10 × 10 ⁻⁶ .
There was only a low ratio of 1 in 100,000. In contrast,
In the transistor structure according to the present embodiment, the injection efficiency is improved by one digit or more in the case of channel hot electron injection, and a writing speed of 10 μsec or less has been achieved.

Furthermore, if the channel length of the portion where electrons are accelerated, that is, the distance from the end of the source impurity region 2 to the step 1b is reduced to, for example, 50 nm or less, this distance is almost equal to or equal to the mean free path of the channel electrons. Since the following condition is satisfied, the electrons accelerated by the electric field conduct ballistically in the channel. Since the ballistic electrons are trajectively injected into the carrier trap at a high speed without being affected by impurity scattering or the like, the injection efficiency can be further increased and the data writing speed is increased.

In the case where the writing speed is maintained as it is, or when a certain speed-up is sufficient, by applying such a transistor structure and the writing method, the channel formation region (substrate or well) and the gate electrode can be connected. Can be set to 10 V or less. When the voltage application to the gate electrode and the substrate or well is performed by dividing the voltage into a positive power supply and a negative power supply, the operating voltage can be reduced to 5 V or less in absolute value.

Since the charge injection efficiency increases, there is room for reducing the channel current at the time of writing. Therefore, in the conventional channel hot electron injection, parallel writing, which has been difficult due to the limitation of the current driving capability of the high voltage circuit, for example, has been made possible for a large number of memory cells connected to the same word line at a time.

In the case of erasing, when the blocks were collectively erased by charge extraction using FN tunneling from the entire surface of the channel as usual, the erasing speed was about 100 msec.

Sixth Embodiment FIG. 8 is a sectional view of a MONOS type memory transistor according to a sixth embodiment.

This memory transistor is significantly different from the MONOS type memory transistor of the fifth embodiment in that:
The gate electrode is divided into a first gate electrode 8a on the source side and a second gate electrode 8b on the drain side. The first gate electrode 8a is provided facing a portion where electrons are accelerated, that is, the upper part of the step 1b, and the second gate electrode 8b is provided mainly facing the bottom of the step 1b. At the time of writing, the first gate electrode 8a mainly controls generation of a channel for accelerating charges, and the second gate electrode 8b mainly controls an electric field for injecting charges. Among the films constituting the gate insulating film 6, the nitride film 12 and the top insulating film 14 do not extend toward the first gate electrode 8a. That is, only the bottom insulating film 10 is interposed between the first gate electrode 8a and the channel formation region 1a. In contrast,
As in the fifth embodiment, a gate insulating film 6 having a three-layer structure is interposed between the second gate electrode 8b and the channel forming region 1a. The gap between the first and second gate electrodes 8a, 8b is filled with an insulating layer 9a, and a sidewall insulating layer 9b is formed on the outer surfaces of the first and second gate electrodes 8a, 8b, respectively.

By ion implantation before and after the formation of the sidewall insulating layer 9b, the source / drain impurity regions 2 and
An impurity region having an LDD structure including LDD regions 4 and LDD regions 2 a and 4 a is formed on the surface of substrate 1. A thin p-type impurity region 3 is formed on the surface of the channel formation region 1a from the end of the LDD region 4a on the drain side to the step 1b. The p-type impurity region 3 and the L
The DD regions 2a and 4a are not essential components.

FIGS. 9A to 10E show this MON.
An example of a method for manufacturing an OS memory transistor is shown in a cross-sectional view.

After forming the element isolation insulating layer and the well on the surface of the semiconductor substrate, a step 1b is formed on the surface of the substrate 1 in FIG. In the formation of this step 1b,
As shown in the drawing, after a part of the substrate surface is covered with a mask layer, for example, a resist R1, a silicon surface which is not protected by the resist R1 by dry etching is etched to a predetermined depth. Subsequently, ion implantation is performed using the same resist R1 as a mask layer to form a p-type impurity region 3 at the bottom and side of the formed step 1b.

After removing the resist R1, in FIG. 9B,
Bottom insulating film 10, nitride film 12, and top insulating film 14
Are sequentially formed by the same method as in the first embodiment. Then, after forming a mask layer, for example, a pattern of the resist R2, which covers a part of the step 1b on the bottom side, the top insulating film 14 and the nitride film 12 around the resist R2 are removed by dry etching.

After removing the resist R2, in FIG.
A conductive film serving as a gate electrode, for example, a doped poly-Si film 8
On top of the top insulating film 14 and the nitride film 12 patterned in the previous step, a mask layer, for example, a resist R3 is formed to cover a predetermined portion above the step. Using this resist R3 as a mask, the doped region around the resist R3 is used.
The poly-Si film 8c is removed. Then, the same resist R3
Is performed using the mask layer as a mask layer to form low-concentration n-type LDD regions 2a and 4a on the surface of the substrate 1 outside the doped poly-Si film 8c. Before or after this ion implantation, by etching using the resist R3 as a mask layer,
The peripheral portion of the bottom insulating film 10 is removed.

After the removal of the resist R3, in FIG. 10D, a resist R4 having an opening crossing the center of the doped poly-Si film 8c is formed. Using the resist R4 as a mask, the doped poly-Si film 8c exposed from the opening.
Remove the central part of. Thereby, the first gate electrode 8
a and the second gate electrode 8b are formed separately.

After removing the resist R4, in FIG. 10E, for example, a silicon oxide-based insulating film is deposited on the entire surface, and the first and second gate electrodes 8a and 8b are covered with an insulator. The gap between both electrodes is filled with an insulator.
By performing anisotropic etching (etch back) on the entire surface in this state, the insulating layer 9a between the first and second gate electrodes 8a and 8b and the sidewall insulating layer 9b are simultaneously formed.

As shown in FIG. 8, high-concentration n-type impurities are ion-implanted using the first and second gate electrodes 8a and 8b and the insulating layers 9a and 9b as a self-aligned mask, and the source and drain impurity regions 2, 4 are formed. To form After that, the first
The memory cell array is completed through the same steps as in the embodiment.

Writing is performed by setting the voltage to the memory transistor having such a configuration in substantially the same manner as in the fifth embodiment. At this time, in this embodiment, since the gate electrodes are provided separately for the first gate electrode 8a for forming the channel and the second gate electrode 8b for controlling the injection electric field, the program voltages can be set separately. it can. Therefore, there is an advantage that bias setting at the time of writing is easily optimized.

For example, at the time of writing, the program voltage applied to the first gate electrode 8a is set to 3V, and the program voltage applied to the second gate electrode 8b is set to 5V. After optimizing the bias voltage at the time of writing in this way,
When direct injection by ballistic electron conduction is performed, the writing speed can be increased to 1 μsec or less, for example, to about 100 nsec.

Seventh Embodiment FIG. 11 is a sectional view of a MONOS type memory transistor according to a seventh embodiment.

This memory transistor is largely different from the MONOS type memory transistor of the sixth embodiment in that:
The second gate electrode 8d for controlling the charge injection electric field has a sidewall shape. As a result, the area occupied by the transistor can be made considerably smaller than that in the second embodiment. With the formation of the sidewall-shaped second gate electrode 8d, a nitride film 12 and a top insulating film 14 constituting the gate insulating film 6 are used as an insulating layer between the first and second gate electrodes 8a and 8d. Other configurations are basically the same as the sixth embodiment.

Since the second gate electrode 8d has a sidewall shape, the drain impurity region 4 and the step 1
The distance from b was shorter than that in the second embodiment, and the channel formation was made easier. Therefore, FIG.
In No. 1, the p-type impurity region is not formed on the surface of the channel forming region 1a, but, of course, the p-type impurity region 3 may be provided as in the sixth embodiment. Further, similarly to the sixth embodiment, LDD regions may be provided inside the source and drain impurity regions 2 and 4, respectively.

FIGS. 12A to 13D show this MO.
An example of a method for manufacturing a NOS type memory transistor is shown in a sectional view.

First, as shown in FIG. 12A, a step 1b is formed on the substrate surface by the same method as in the sixth embodiment. Next, a bottom insulating film 10 and a conductive film serving as a gate electrode are formed, and the conductive film serving as the gate electrode is patterned by etching using a resist (not shown) as a mask. Thus, the first gate electrode 8a is formed at a predetermined position above the step 1b.

After removing the resist, in FIG. 12B, a nitride film 12 and a top insulating film 14 are sequentially formed by the same method as in the first embodiment.

Thereafter, as shown in FIG. 13C, a conductive film serving as a gate electrode is thickly deposited on the entire surface, and is etched back. Thereby, on both side walls of the first gate electrode 8a,
Sidewall-shaped conductive layers 8d and 8e are formed with nitride film 12 and top insulating film 14 interposed therebetween.

In FIG. 13D, first, the conductive layer 8
d, 8e are used as a self-aligned mask, and the top insulating film 14, the nitride film 12, and the bottom insulating film 10 exposed therearound.
Are sequentially removed. A mask layer, for example, a resist R5 is formed over the conductive layer (second gate electrode) 8d and the first gate electrode 8a on the step bottom side. Etching is performed using the resist R5 as a mask to remove one of the conductive layers 8e. Subsequently, the top insulating film 14, the nitride film 12, and the bottom insulating film 10 are sequentially removed.

After removing the resist R5, as shown in FIG. 11, the first and second gate electrodes 8a and 8d, the insulating film 1
The n-type impurity is ion-implanted at a high concentration using the self-aligned masks 2 and 14 as source and drain impurity regions 2 and 4.
To form Thereafter, through the same steps as in the first embodiment, the memory cell array is completed.

In writing to a memory transistor having such a configuration, the area occupied by the transistor is different from that in the fifth embodiment shown in FIG. 7 even though gate electrodes for forming a channel and controlling an injection electric field are separately provided. Is almost unchanged. Therefore, there is an advantage that a fine memory cell suitable for high integration can be realized.

The voltage setting method at the time of writing is basically the same as that of the sixth embodiment. However, in this embodiment, the insulating film between the first and second gate electrodes 8a and 8d is equivalent to an oxide film. Since it is as thin as less than 10 nm, the horizontal electric field strength according to the voltage applied to the first gate electrode 8a is high, and the horizontal electric field acts to assist the carrier injection. Therefore, electric charges are efficiently injected into the carrier trap near the corner of the step 1a. That is, there is an advantage that the ratio of the charge storage amount to the occupied area of the gate electrode can be increased as compared with the transistor structure of the sixth embodiment. Further, the charge injection efficiency is further increased by the assist of the lateral electric field, and the writing speed can be increased accordingly.

Eighth Embodiment FIG. 14 is a sectional view of a MONOS type memory transistor according to an eighth embodiment.

This memory transistor is significantly different from the MONOS type memory transistor of the seventh embodiment in that:
That is, no step is provided in the channel forming region 1a of the substrate. Therefore, the injection method itself is basically a source side injection. Other configurations are basically the same as those of the seventh embodiment. In the present embodiment, as in the seventh embodiment, the gate electrode is formed separately for forming a channel and for controlling an injection electric field. In this embodiment, the writing speed is increased to 1 μsec, and the operating voltage is reduced to 7V. For this purpose, the bottom insulating film 10 of the gate insulating film 6 is compared with the known example.
Is set to 4 nm or less, and erasing is performed by extracting electrons in the channel direction.

As for the manufacturing method, the step of forming the steps in the manufacturing method of the seventh embodiment may be omitted, and the description is omitted here.

Writing is performed by setting a voltage to the memory transistor having such a configuration in substantially the same manner as in the seventh embodiment. For example, when programming, the program voltage applied to the first gate electrode 8a is set to 5
V, the program voltage applied to the second gate electrode 8b is 7
Set to V. After optimizing the bias voltage at the time of writing as described above, writing is performed by channel hot electron injection.

In the present embodiment, as in the seventh embodiment, the gate electrodes are provided separately for the first gate electrode 8a for forming the channel and the second gate electrode 8b for controlling the injection electric field. The voltages can be set separately. Therefore, there is an advantage that bias setting at the time of writing is easily optimized. Although the gate electrodes for forming the channel and controlling the injection electric field are separately provided, the area occupied by the transistor is almost the same as that of the fifth embodiment shown in FIG. Therefore, there is an advantage that a fine memory cell suitable for high integration can be realized.

Hereinafter, another embodiment relating to the memory cell array structure and the structure of the memory cell and the memory transistor will be described.

Ninth Embodiment A memory cell and a memory cell array according to the ninth embodiment are of a separated source line NOR type in which bit lines and source lines are hierarchized. FIG. 15 shows a circuit configuration of this NOR type memory cell array. FIG. 16 shows this NOR.
FIG. 17 is a plan view of the type memory cell array, and FIG.
The bird's-eye view seen from the section side along line -B 'is shown.

In this nonvolatile memory device, the bit lines are hierarchized into main bit lines and sub-bit lines, and the source lines are hierarchized into main source lines and sub-source lines. Main bit line M
BL1 is connected to the sub-bit line S via the selection transistor S11.
BL1 is connected, and the sub-bit line SBL2 is connected to the main bit line MBL2 via the selection transistor S21. The selection transistor S1 is connected to the main source line MSL1.
The sub-source line SSL1 is connected to the sub-source line SSL2 via the select transistor S22, and the sub-source line SSL2 is connected to the main source line MSL2 via the select transistor S22.

Sub bit line SBL1 and sub source line SSL1
, Memory transistors M11 to M1n (for example, n = 128) are connected in parallel, and sub bit line SBL2
Between the memory transistor M and the sub-source line SSL2.
21 to M2n are connected in parallel. The n memory transistors connected in parallel with each other and two select transistors (S11 and S12 or S21 and S22)
Thus, a unit block forming the memory cell array is formed.

The gates of the memory transistors M11, M21,... Adjacent in the word direction are connected to the word line WL1. Similarly, memory transistors M12, M2
, Are connected to the word line WL2.
Each gate of the memory transistors M1n, M2n,... Is connected to a word line WLn. The selection transistors S11,... Adjacent in the word direction are controlled by a selection line SG11, and the selection transistors S21,.
Is controlled by Similarly, the select transistors S12,... Adjacent in the word direction are controlled by a select line SG12, and the select transistors S22,.

In this fine NOR type cell array, FIG.
As shown in FIG. 7, a p-well W is formed on the surface of a semiconductor substrate SUB. The p-well W is insulated and isolated in the word direction by an element isolation insulating layer ISO in which an insulator is buried in a trench and arranged in parallel stripes.

Each p-well portion separated by the element isolation insulating layer ISO becomes an active region of the memory transistor. On both sides in the width direction in the active region, n-type impurities are introduced at a high concentration in parallel stripes spaced apart from each other, whereby sub-bit lines SBL1 and SBL2 (hereinafter, SBL2) are introduced.
) And sub-source lines SSL1 and SSL2 (hereinafter, referred to as
SSL). The sub bit line SBL corresponds to a “first impurity region”, and the sub source line SSL corresponds to a “second impurity region”. Each word line WL is orthogonal to the sub bit line SBL and the sub source line SSL via an insulating film.
1, WL2, WL3, WL4, ... (hereinafter referred to as WL)
Are wired at equal intervals. These word lines WL
It is in contact with the p-well W and the element isolation insulating layer ISO via an insulating film including a charge storage means therein. The intersection of the p-well W between the sub-bit line SBL and the sub-source line SSL and each word line WL becomes a channel forming region of the memory transistor, and the sub-bit line portion in contact with the channel forming region is a drain, The sub source line portion functions as a source.

The upper surface and the side wall of the word line WL are covered with an offset insulating layer and a side wall insulating layer (in this example, a normal interlayer insulating layer is also possible). In these insulating layers, bit contacts BC reaching the sub-bit lines SBL at predetermined intervals and source contacts SC reaching the sub-source lines SSL are formed. These contacts BC and SC are provided, for example, for every 128 memory transistors in the bit direction. The main bit line MB contacting the bit contact BC on the insulating layer.
, And the main source lines MSL1, MBL2, ... that are in contact with the source contact SC are alternately formed in a parallel stripe shape.

In this fine NOR type cell array, a first common line (bit line) and a second common line (source line) are hierarchized, and it is not necessary to form a bit contact BC and a source contact SC for each memory cell. Therefore, there is basically no variation in the contact resistance itself. The bit contact BC and the source contact SC are provided, for example, for every 128 memory cells. However, when the plug formation is not performed in a self-aligned manner, the offset insulating layer and the sidewall insulating layer are not required. That is, a normal interlayer insulating film is deposited thickly to bury the memory transistor, and then a contact is opened by normal photolithography and etching.

Since there is almost no wasteful space as a pseudo contactless structure in which the sub bit line and the sub source line are formed of impurity regions, when each layer is formed at the minimum line width F of the wafer process limit, it becomes 8F ² . Can be manufactured with a very small cell area. In the present embodiment, since electrons can be independently injected at high speed into two locations in one memory cell, the cell area per bit is 4F ² . Also, since the source lines are separated, page writing is also possible. Further, the bit lines and the source lines are hierarchized, and the selection transistor S11 or S21 separates the parallel memory transistor group in the unselected unit block from the main bit line MBL1 or MBL2, so that the capacity of the main bit line is significantly reduced. This is advantageous for high speed and low power consumption. Further, by the operation of the selection transistor S12 or S22, the sub-source line can be separated from the main source line, and the capacitance can be reduced. In order to further increase the speed, the sub-bit line SBL and the sub-source line SSL are preferably formed of silicide-attached impurity regions, and the main bit line MBL and the main source line MSL are preferably formed of metal wiring.

Tenth Embodiment A memory cell and a memory cell array according to a tenth embodiment have a fine NOR using a self-alignment technique and a meandering source line.
Type. FIG. 18 is a schematic plan view of a NOR type cell array according to the tenth embodiment.

In this NOR type cell array, element isolation insulating layers ISO made of vertical strip-like trenches or LOCOS are arranged at equal intervals in the bit direction (vertical direction in FIG. 18) on the surface of the p-well. The word lines WLm-2, WLm-1, WLm,
WLm + 1 are wired at equal intervals. The laminated structure including the word lines is composed of a laminated film of a bottom insulating film, a nitride film, a top insulating film, and a gate electrode, as in the above-described embodiment.

In the active region within the space between the element isolation insulating layers, for example, an n-type impurity is introduced at a high concentration in the space between the word lines so that the source impurity region S and the drain impurity region D are alternately formed. ing. The size of the source impurity region S and the drain impurity region D is defined only by the interval between the element isolation insulating layers ISO in the word direction (horizontal direction in FIG. 18) and only by the word line interval in the bit direction. You. Therefore, the source impurity region S and the drain impurity region D are formed very uniformly because errors in mask alignment with respect to variations in size and arrangement are scarcely introduced.

By forming a sidewall insulating layer around each word line, a contact hole for connecting a bit line and a contact hole for connecting a source line are formed with respect to the source impurity region S and the drain impurity region D. It is formed while diverting two self-aligned contact techniques simultaneously. Moreover, the above process does not require a photomask. Therefore, as described above, source impurity region S
And the size and arrangement of the drain impurity region D are uniform,
On the other hand, the size of a contact hole for connecting a bit line or a source line formed in a two-dimensional self-alignment is also very uniform. Further, the contact hole has an area corresponding to the area of the source impurity region S and the drain impurity region D.
It has almost the maximum size.

The source lines SLn-1, SLn, SLn + 1 (hereinafter, referred to as SL) wired in the bit direction thereon.
Are meanderingly arranged on the element isolation insulating layer ISO and the source impurity region S while avoiding the drain impurity region D,
It is connected to each lower source impurity region S via the source line connection contact hole. Source line S
On L, the bit line BLn-1 is interposed via a second interlayer insulating film.
, BLn, and BLn + 1 (hereinafter, referred to as BL) are wired at equal intervals. This bit line BL is located above the active area, and via a contact hole for connecting the bit line.
It is connected to each lower drain impurity region D.

In the cell pattern having such a structure, as described above, the formation of the source impurity region S and the drain impurity region D is hardly affected by the mask alignment, and the contact hole for bit line connection and the source line connection Contact holes are formed by diverting the self-alignment technique twice, so that the contact holes do not become a limiting factor for reducing the cell area, and the source wiring and the like can be formed with a minimum line width F of the wafer process limit. Since there is little wasteful space, a very small cell area close to 6F ² can be realized. Electrons can be independently injected into two locations in one memory cell, and in this case, the cell area per bit is 3F ² .

Eleventh Embodiment The eleventh embodiment is a nonvolatile transistor using a large number of mutually insulated Si nanocrystals embedded in a gate insulating film and having a particle size of, for example, 10 nanometers or less, as charge storage means of a memory transistor. The present invention relates to a semiconductor memory device (hereinafter, referred to as a Si nanocrystal type).

FIG. 19 is a sectional view showing the element structure of this Si nanocrystal type memory transistor. The Si nanocrystal nonvolatile memory according to the present embodiment is different from the fifth embodiment in that the charge storage means is a nanocrystal 32;
Further, the gate insulating film 30 of the present embodiment is composed of the bottom insulating film 10 having the Si nanocrystals 32 formed on the upper surface, and the oxide film 34 thereon. Other configurations are the same as in the fifth embodiment.

The size (diameter) of the Si nanocrystal 32 is
However, it is preferably 10 nm or less, for example, about 4.0 nm, and individual Si nanocrystals are spatially separated by the oxide film 34 at an interval of, for example, about 4 nm. The bottom insulating film 10 in this example is slightly thicker than the fifth embodiment because of the fact that the charge storage means (Si nanocrystals 32) is closer to the substrate side, and from 2.6 nm to 5.0 depending on the application.
It can be appropriately selected within the range up to nm. Here, 4.0
The thickness was about nm.

In the manufacture of a memory transistor having such a configuration, after the bottom insulating film 10 is formed, for example, the plasma C
A large number of Si nanocrystals 32 are formed on the bottom insulating film 10 by the VD method. Further, an oxide film 34 is formed to a thickness of, for example, about 7 nm by LP-CVD so as to bury the Si nanocrystals 32. In this LP-CVD, the source gas is DC
The mixed gas of S and N ₂ O and the substrate temperature are, for example, 700 ° C. At this time, the Si nanocrystals 32 are embedded in the oxide film 34. If planarization is required, a new planarization process (eg, CMP) may be performed. Thereafter, a gate electrode 8 is formed, and a step of collectively patterning the gate laminated film is performed, thereby completing the Si nanocrystal type memory transistor.

The thus formed Si nanocrystal 32
Function as carrier traps discretized in the plane direction. The trap level can be estimated by a band discontinuity with the surrounding silicon oxide, and the estimated value is about 3.
It is about 1 eV. Individual Si nanocrystals 32 of this size can hold several injected electrons. Note that the Si nanocrystal 32 may be made smaller to hold a single electron.

With respect to the Si nanocrystal type nonvolatile memory having such a configuration, data retention characteristics were examined by a Landkist back tunneling model. In order to improve the data retention characteristics, it is important to increase the trap level and increase the distance between the charge center of gravity and the semiconductor substrate 1. Therefore, the simulation using the Landkist model as a physical model yields a trap level of 3.1e.
Data retention in the case of V was studied. As a result, it was found that by using a deep carrier trap having a trap level of 3.1 eV, good data retention was exhibited even when the distance from the charge retention medium to the channel formation region 1a was relatively short, 4.0 nm.

Twelfth Embodiment A twelfth embodiment is a nonvolatile semiconductor memory device (hereinafter referred to as a fine divided FG) using a large number of finely divided floating gates embedded in an insulating film and separated from each other as charge storage means of a memory transistor. Type).

FIG. 20 is a sectional view showing the element structure of this finely divided FG type memory transistor. The finely divided FG nonvolatile memory of this embodiment is different from the fifth embodiment in that the charge storage means is formed of a finely divided floating gate, the memory transistor is formed on an SOI substrate, and The gate insulating film 40 of the present embodiment comprises a bottom insulating film 10 having a finely divided floating gate 42 formed on an upper surface thereof, and an oxide film 4 thereon.
4 and 4. Other configurations are
This is the same as the fifth embodiment. This finely divided floating gate 42 is made of the Si nanocrystal 3 of the eleventh embodiment.
2 corresponds to a specific example of the “small particle size conductor” in the present invention.

As an SOI substrate, SIMOX (Separation by Impl) in which oxygen ions are implanted into a silicon substrate at a high concentration and a buried oxide film is formed at a position deeper than the substrate surface.
An oxygen) substrate or a bonded substrate in which an oxide film is formed on one silicon substrate surface and bonded to another substrate are used. The SOI substrate formed by such a method and shown in FIG. 20 includes a support substrate 46, an isolation oxide film 48, and a silicon layer 50. In the silicon layer 50, a channel formation region 1a, a source impurity region 2, and a drain Impurity region 4 is provided. Note that a glass substrate, a plastic substrate, a sapphire substrate, or the like may be used as the support substrate 46 in addition to the semiconductor substrate.

The finely divided floating gate 42 is obtained by processing a normal FG type floating gate into fine poly-Si dots having a height of, for example, about 5.0 nm and a diameter of, for example, 8 nm. The bottom insulating film 10 in this example is slightly thicker than in the first embodiment, but is formed much thinner than a normal FG type, and is appropriately selected from the range of 2.5 nm to 4.0 nm according to the intended use. it can. Here, the thinnest film thickness is 2.5 nm.

In manufacturing a memory transistor having such a configuration, after a bottom insulating film 10 is formed on an SOI substrate, a polysilicon film (final film thickness: 5 nm). In this LP-CVD, the source gas is a mixed gas of DCS and ammonia, and the substrate temperature is, for example, 650 ° C. Next, the polysilicon film is processed into fine poly-Si dots having a diameter of, for example, up to 8 nm by using, for example, an electron beam exposure method. This poly-Si dot is the finely divided floating gate 42 (charge storage means). Thereafter, an oxide film 44 is formed to a thickness of, for example, about 9 nm by LP-CVD while burying the finely divided floating gate 42. In this LP-CVD, the source gases are DCS and N ₂ O.
And the substrate temperature is, eg, 700 ° C. At this time, the finely divided floating gate 42 is
Embedded in If planarization is required, a new planarization process (eg, CMP) may be performed. Thereafter, the gate electrode 8 is formed, and the finely divided FG type memory transistor is completed through a step of collectively patterning the gate laminated film.

As to the fact that the floating gate is finely divided by using the SOI substrate in this manner, as a result of evaluating the characteristics of a prototype device, it was confirmed that the expected good characteristics were obtained.

Modifications In the first to twelfth embodiments described above, various modifications are possible.

Although not particularly shown, the present invention is applicable to various NOR type cells such as a fine NOR type cell which is a DINOR type, that is, a so-called HiCR type, and is composed of a separated source type cell array in which a source line is shared by two adjacent source regions. The invention is applicable.

The “planar discrete charge storage means” in the present invention includes a carrier trap formed in the bulk of the nitride film and a carrier trap formed near the interface between the oxide film and the nitride film. (Nitride-Oxid
e) The present invention is applicable to an MNOS type film.

The present invention can be applied not only to a stand-alone nonvolatile memory but also to an embedded nonvolatile memory integrated with a logic circuit on the same substrate. The use of the SOI substrate as in the twelfth embodiment can be applied to the memory transistor structures of the first to eleventh embodiments.

[0143]

According to the nonvolatile semiconductor memory device and the method of driving the same according to the present invention, the accelerated charges are efficiently and rapidly injected into the charge storage means while maintaining the momentum (direction and magnitude). , A high writing speed can be obtained. Further, for example, since the first and second gate electrodes are provided for channel formation and injection field control, it is easy to set a gate voltage for obtaining a high writing speed. Further, there are advantages such as high reliability and durability due to erasing by extracting electrons, easy application of multi-bit writing, and easy reduction of bit cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a source-separated NOR memory cell array of a nonvolatile semiconductor memory according to a first embodiment.

FIG. 2 is a schematic plan view of a NOR memory cell array according to the first embodiment.

FIG. 3 is a perspective view of the memory cell array of FIG. 2 according to the first embodiment as viewed from a cross-sectional side along line AA ′.

FIG. 4 is a sectional view showing the element structure of the MONOS type memory transistor according to the first embodiment.

FIG. 5 is a circuit diagram showing a schematic configuration of a virtual ground NOR type memory cell array of a nonvolatile semiconductor memory according to a second embodiment.

FIG. 6 is a cross-sectional view illustrating an example of an element structure of a memory transistor according to a fourth embodiment.

FIG. 7 is a sectional view showing an element structure of a MONOS memory transistor according to a fifth embodiment.

FIG. 8 is a sectional view showing an element structure of a MONOS memory transistor according to a sixth embodiment.

FIG. 9 is a cross-sectional view after an LDD region is formed in the manufacture of the MONOS memory transistor according to the sixth embodiment.

FIG. 10 is a cross-sectional view following FIG. 9 after separating a gate electrode and forming an insulating layer on an end face;

FIG. 11 is a sectional view showing an element structure of a MONOS memory transistor according to a seventh embodiment.

FIG. 12 is a cross-sectional view after a gate insulating film is formed in the manufacture of the MONOS memory transistor according to the seventh embodiment.

FIG. 13 is a sectional view following FIG. 12 after removing one of the sidewall-type conductive layers.

FIG. 14 is a sectional view showing an element structure of a MONOS memory transistor according to an eighth embodiment.

FIG. 15 is a circuit diagram showing a configuration of a NOR memory cell array according to a ninth embodiment.

FIG. 16 is a plan view of a NOR type memory cell array according to a ninth embodiment.

FIG. 17 is a bird's-eye view of the NOR-type memory cell array according to the ninth embodiment as viewed from a cross-sectional side along the line BB ′ of FIG. 16;

FIG. 18 is a plan view showing a schematic configuration of a fine NOR type cell array according to a tenth embodiment.

FIG. 19 is a sectional view showing an element structure of a Si nanocrystal memory transistor according to an eleventh embodiment.

FIG. 20 is a sectional view showing an element structure of a finely divided FG type memory transistor according to a twelfth embodiment;

[Explanation of symbols]

1 semiconductor substrate or well, 1a channel formation region, 2S source impurity region (second impurity region),
4, D ... drain impurity region (first impurity region), 6,
Reference numerals 30, 40: gate insulating film, 8: gate electrode, 10: bottom insulating film, 12: nitride film, 14: top insulating film, 32
... Si nanocrystals, 34, 44 oxide film, 42 fine-divided floating gate, 46 semiconductor substrate, 48 isolation oxide film, 50 silicon layer, 60 n-well, 61
p-well, ISO: element isolation insulating layer, PW: p-well,
M11 to M22: memory transistors, S11, ST0
Etc .... Selection transistor, BL1 etc .... Bit line, MBL1
Etc .: main bit line, SBL: sub-bit line, SL1, etc .: source line, MSL: main source line, SSL1, etc .: sub-source line,
WL1 etc .... word line, BC ... bit contact, SC ...
Source contact.

Continued on front page F term (reference) 5F001 AA14 AA19 AA34 AB02 AB03 AC02 AC04 AC06 AC62 AD15 AD17 AD18 AD21 AD23 AE02 AE08 AF06 AF20 AG02 AG21 AG30 5F083 EP09 EP14 EP15 EP17 EP18 EP22 EP49 EP55 EP63 EP68 EP77 ER02 ER05 ER06 ER30 GA30 HA03 JA04 JA35 JA39 JA53 KA06 KA12 MA02 MA06 MA20 PR12 PR21 PR33 ZA21 5F101 BA16 BA46 BA54 BB02 BB04 BC02 BC07 BC11 BC13 BD05 BD07 BD09 BD13 BD15 BE05 BE07 BF02 BF05 BH02 BH03 BH16

Claims (40)

[Claims] 1. A substrate, a semiconductor channel formation region provided on the surface of the substrate, and first and second impurity regions formed on the substrate surface with the channel formation region interposed therebetween and serving as a source or a drain during operation. A gate insulating film provided on the channel forming region; a gate electrode provided on the gate insulating film; and a gate electrode in the gate insulating film in a plane facing the channel forming region and in a film thickness direction. A non-volatile semiconductor storage device having charge storage means which is discretized and provided in a direction in which charges are accelerated during operation. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the charge injected into said charge storage means is hot electrons. 3. The non-volatile semiconductor memory device according to claim 1, wherein said electric charge is accelerated mainly by a vertical electric field component between said first impurity region and said gate electrode. 4. The non-volatile semiconductor device according to claim 3, wherein said charge storage means has a first region into which said charge is injected during operation and a second region into which no charge is injected. Storage device. 5. The charge accumulating means has a third region into which charges are injected during operation at a position on the side of the second impurity region facing the first region in the channel direction with the second region interposed therebetween. The nonvolatile semiconductor memory device according to claim 4. 6. The charge injected into the charge storage means is 2
4. The nonvolatile semiconductor memory device according to claim 3, wherein the non-volatile semiconductor memory device is hot electrons generated by secondary impact ionization. 7. The nonvolatile semiconductor memory device according to claim 3, wherein the charge injected into said charge storage means is substrate hot electrons generated by being accelerated in a depletion layer of said channel formation region. 8. The method according to claim 1, further comprising:
A step is provided for lowering the impurity region relatively to the second impurity region. The acceleration of the charge is mainly caused by a horizontal electric field component between the first and second impurity regions on the upper side of the step. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the operation is performed along a channel formation region. 9. The nonvolatile semiconductor memory device according to claim 8, wherein said charge storage means is formed around a gate insulating film portion between said step and said first impurity region. 10. The non-volatile semiconductor memory device according to claim 8, wherein a length of the upper part of the step in which the charge is accelerated in a channel direction is equal to or less than a mean free path of the charge in the channel. 11. A length of the upper portion of the step where the charge is accelerated in a channel direction is set to be within a predetermined distance within which the charge in the channel can travel without being affected by impurity scattering. 3. The nonvolatile semiconductor memory device according to 1. 12. The nonvolatile semiconductor memory device according to claim 8, wherein a length in a channel direction above said step at which said electric charges are accelerated is 50 nm or less. 13. The charge accumulating means does not have conductivity as a whole surface facing the channel forming region when there is no movement of electric charge at least between the outside and the outside.
3. The nonvolatile semiconductor memory device according to 1. 14. The nonvolatile semiconductor memory device according to claim 13, wherein said gate insulating film includes a bottom insulating film on said channel formation region, and a nitride film or an oxynitride film on said bottom insulating film. 15. The gate insulating film according to claim 13, wherein the gate insulating film includes a bottom insulating film on the channel formation region, and a small-diameter conductor formed on the bottom insulating film and insulated from each other as the charge storage means. 14. The nonvolatile semiconductor memory device according to claim 1. 16. The nonvolatile semiconductor memory device according to claim 15, wherein said small-diameter conductor has a particle size of 10 nanometers or less. 17. A substrate, a channel forming region of a semiconductor provided on the surface of the substrate, and first and second impurity regions formed on the substrate surface with the channel forming region interposed therebetween and serving as a source or a drain during operation. A gate insulating film provided on the channel forming region; a gate electrode provided on the gate insulating film; and a gate electrode in the gate insulating film in a plane facing the channel forming region and in a film thickness direction. A non-volatile semiconductor storage device having discrete charge storage means, wherein a step is provided on the surface of the channel forming region to make the first impurity region relatively lower than the second impurity region. . 18. A substrate, a semiconductor channel formation region provided on the surface of the substrate, and first and second impurity regions formed on the substrate surface with the channel formation region interposed therebetween and serving as a source or a drain during operation. A gate insulating film provided on the channel forming region; a gate electrode provided on the gate insulating film; and in the gate insulating film, in a plane facing the channel forming region and in a film thickness direction. The gate electrode is stacked on the first impurity region side of the channel forming region via a first gate insulating film having no charge storage unit therein. A first gate electrode; and a second gate electrode stacked on the second impurity region side of the channel formation region via a second gate insulating film having charge storage means therein. Non-volatile semiconductor storage device. 19. The semiconductor device according to claim 18, wherein the second gate electrode is formed on a side wall of the first gate electrode via an insulating film.
3. The nonvolatile semiconductor memory device according to 1. 20. The nonvolatile semiconductor memory device according to claim 18, further comprising a step on a surface of said channel formation region, said step being relatively lower than said first impurity region with respect to said second impurity region. 21. A substrate, a semiconductor channel formation region provided on the surface of the substrate, and first and second impurity regions formed on the substrate surface with the channel formation region interposed therebetween and serving as a source or a drain during operation. A gate insulating film provided on the channel forming region; a gate electrode provided on the gate insulating film; and a surface and a film thickness direction in the gate insulating film facing the channel forming region. A method for driving a non-volatile semiconductor storage device having charge storage means discretized in the above manner, wherein, during operation, electric charges are accelerated in the channel formation region or the depletion layer in the periphery and the momentum is maintained A method for driving a non-volatile semiconductor memory device injecting charge into discrete charge storage means. 22. The accelerated charge is injected into a portion of the charge storage means on the first impurity region side.
3. The method for driving a nonvolatile semiconductor memory device according to claim 1. 23. A method of applying a bias to said first and second impurity regions in a reverse manner, and
23. The method for driving a nonvolatile semiconductor memory device according to claim 22, wherein the impurity is implanted into a portion on an impurity region side. 24. The method of driving a nonvolatile semiconductor memory device according to claim 21, wherein a traveling distance from the start of the charge acceleration to the injection thereof is 50 nm or less. 25. The method of driving a nonvolatile semiconductor memory device according to claim 21, wherein said electric charges are ballistically conducted in a channel. 26. The driving method of a nonvolatile semiconductor memory device according to claim 21, wherein acceleration and injection of the electric charge are controlled by separate gate electrodes. 27. The method according to claim 21, wherein the maximum value of the voltage applied to the gate electrode is 5 V or less. 28. The channel forming region, the first and second channels.
28. The method according to claim 27, wherein the maximum value of the voltage applied to the impurity region and the gate electrode is 5 V or less. 29. At the time of reading, a predetermined read drain voltage is applied between the first and second impurity regions so that the first impurity region serves as a source, and a predetermined read gate voltage is applied to the gate electrode. A method for driving a nonvolatile semiconductor memory device according to claim 21. 30. A method according to claim 23, wherein a plurality of bits of data stored according to the charge partially injected into said charge storage means are read out by changing a voltage application direction between said first and second impurity regions. The driving method of the nonvolatile semiconductor memory device described in the above. 31. The non-volatile memory according to claim 22, wherein at the time of erasing, the charge injected from the first impurity region side and held in the charge storage means is drawn to the first impurity region side by direct tunneling or FN tunneling. For driving a volatile semiconductor memory device. 32. At the time of erasing, charges injected from the first or second impurity region side and held in the charge storage means separately on both sides in the channel direction are individually or collectively collected by direct tunneling or FN tunneling. 24. The method of driving a non-volatile semiconductor storage device according to claim 23, wherein the pull-out operation is performed. 33. The charge accumulating means does not have conductivity as a whole surface facing the channel forming region when there is no movement of electric charge at least between the outside and the outside.
2. The method for driving a nonvolatile semiconductor memory device according to item 1. 34. The nonvolatile semiconductor memory device according to claim 33, wherein said gate insulating film includes a bottom insulating film on said channel formation region, and a nitride film or an oxynitride film on said bottom insulating film. Method. 35. The gate insulating film according to claim 33, wherein the gate insulating film includes a bottom insulating film on the channel formation region, and small-diameter conductors formed on the bottom insulating film and insulated from each other as the charge storage means. The driving method of the nonvolatile semiconductor memory device described in the above. 36. The driving method for a nonvolatile semiconductor memory device according to claim 35, wherein the small-diameter conductor has a particle size of 10 nanometers or less. 37. A substrate, a semiconductor channel formation region provided on the surface of the substrate, and first and second impurity regions formed on the substrate surface with the channel formation region interposed therebetween and serving as a source or a drain during operation. A gate insulating film provided on the channel forming region; a gate electrode provided on the gate insulating film; and a gate electrode in the gate insulating film in a plane facing the channel forming region and in a film thickness direction. A method of driving a non-volatile semiconductor storage device having charge storage means that is discretized, wherein during operation, charges are accelerated in a channel formed in the channel formation region, and a ballistic electric conduction phenomenon is utilized. A method for driving a nonvolatile semiconductor memory device injecting the charge into the discrete charge storage means. 38. A substrate, a semiconductor channel formation region provided on the surface of the substrate, and first and second impurity regions formed on the substrate surface with the channel formation region interposed therebetween and serving as a source or a drain during operation. A gate insulating film provided on the channel forming region; a gate electrode provided on the gate insulating film; and a gate electrode in the gate insulating film in a plane facing the channel forming region and in a film thickness direction. A method for driving a non-volatile semiconductor storage device, comprising: charge storage means which are discretized, wherein hot electrons generated by secondary impact ionization are injected into said charge storage means during operation. A method for driving a semiconductor memory device. 39. A substrate, a semiconductor channel formation region provided on the surface of the substrate, and first and second impurity regions formed on the substrate surface with the channel formation region interposed therebetween, and serving as a source or a drain during operation. A gate insulating film provided on the channel forming region; a gate electrode provided on the gate insulating film; and a gate electrode in the gate insulating film in a plane facing the channel forming region and in a film thickness direction. A method of driving a non-volatile semiconductor storage device having charge storage means that is discretized, comprising: accelerating charges in a depletion layer formed in the channel formation region during operation to convert the charge into substrate hot electrons; A method for driving a non-volatile semiconductor storage device injecting into a charged charge storage means. 40. A substrate, a semiconductor channel formation region provided on the surface of the substrate, and first and second impurity regions formed on the substrate surface with the channel formation region interposed therebetween and serving as a source or a drain during operation. A gate insulating film formed on the channel forming region; a gate electrode formed on the gate insulating film; and a gate insulating film that is discretized in a plane facing the channel forming region and in a film thickness direction. Charge storage means formed therein, into which channel hot electrons, ballistic hot electrons, secondary impact ionization hot electrons, substrate hot electrons or hot electrons caused by band-to-band tunnel current are injected during operation. A method of driving a device, comprising: A method for driving a nonvolatile semiconductor memory device in which charges injected from a region side and held on one side or both sides in the channel direction in the charge storage means are individually or collectively drawn to the substrate side by direct tunneling or FN tunneling. .