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CN109585404A - 半导体封装及其形成方法 - Google Patents

半导体封装及其形成方法 Download PDF

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Publication number
CN109585404A
CN109585404A CN201810141147.0A CN201810141147A CN109585404A CN 109585404 A CN109585404 A CN 109585404A CN 201810141147 A CN201810141147 A CN 201810141147A CN 109585404 A CN109585404 A CN 109585404A
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CN
China
Prior art keywords
hole
conductive features
dielectric layer
seed layer
layer
Prior art date
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Granted
Application number
CN201810141147.0A
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English (en)
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CN109585404B (zh
Inventor
余振华
蔡豪益
曾明鸿
郭庭豪
林彦良
黄子松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109585404A publication Critical patent/CN109585404A/zh
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Abstract

提供一种半导体封装，所述半导体封装包括第一装置封装，所述第一装置封装包括：第一重布线结构，包括第一重布线及第二重布线；管芯，位于第一重布线结构上；第一通孔，耦合到第一重布线的第一侧；第二通孔，耦合到第二重布线的第一侧且延伸穿过所述第二重布线；包封体，环绕管芯、第一通孔、及第二通孔；以及第二重布线结构，位于包封体之上，所述第二重布线结构电连接到管芯、第一通孔、及第二通孔。所述半导体封装还包括：第一导电连接件，耦合到第一重布线的第二侧，所述第一导电连接件沿与第一通孔的纵向轴线不同的轴线设置；第二导电连接件，耦合到第二重布线的第二侧，所述第二导电连接件沿第二通孔的纵向轴线设置。

Description

半导体封装及其形成方法
优先权主张及交叉参考
本申请主张2017年9月29日提出申请的美国临时申请第62/565,321的权利，所述美国临时申请并入本文供参考。
技术领域
本发明的实施例是有关于一种半导体封装及其形成方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速发展。在很大程度上，集成密度的提高来自于最小特征大小(minimum feature size)的重复减小，此使得更多的组件能够集成到给定区域中。随着对缩小电子装置的需求的增长，需要更小且更具创造性的半导体管芯封装技术。此种封装系统的一个实例是叠层封装(Package-on-Package，PoP)技术。在叠层封装装置中，顶部半导体封装被堆叠在底部半导体封装顶上，以提供高集成水平及组件密度。叠层封装技术一般能够生产功能性得到增强且在印刷电路板(printed circuit board，PCB)上占用空间(footprint)小的半导体装置。
发明内容
本发明的一实施例公开一种半导体封装包括第一装置封装，所述第一装置封装包括：第一重布线结构，包括第一重布线及第二重布线；管芯，位于第一重布线结构上；第一通孔，耦合到第一重布线的第一侧；第二通孔，耦合到第二重布线的第一侧且延伸穿过所述第二重布线；包封体，环绕管芯、第一通孔、及第二通孔；以及第二重布线结构，位于包封体之上，所述第二重布线结构电连接到管芯、第一通孔、及第二通孔。所述半导体封装还包括：第一导电连接件，耦合到第一重布线的第二侧，所述第一导电连接件沿与第一通孔的纵向轴线不同的轴线设置；以及第二导电连接件，耦合到第二重布线的第二侧，所述第二导电连接件沿第二通孔的纵向轴线设置。
本发明的一实施例公开一种半导体封装的形成方法包括形成第一重布线结构，所述形成第一重布线结构包括：在载体衬底之上沉积第一介电层；在第一介电层上形成第一导电特征；在第一介电层上形成第二导电特征；在第一介电层上形成第三导电特征；以及在第一导电特征、第二导电特征、及第三导电特征上沉积第二介电层。所述半导体封装的形成方法还包括：在第一导电特征上形成第一通孔；在第二导电特征上、第三导电特征上、以及所述第二导电特征与所述第三导电特征之间形成第二通孔；将管芯贴合到邻近第一通孔及第二通孔的第一重布线结构；使用包封体包封管芯、第一通孔、及第二通孔；将包封体、第一通孔、及第二通孔平坦化；以及在包封体、第一通孔、第二通孔、及管芯之上形成第二重布线结构。
本发明的一实施例公开一种半导体封装的形成方法包括：在第一介电层上沉积第一晶种层；在第一晶种层上镀覆第一导电特征及第二导电特征；在第一导电特征及第二导电特征上沉积第二介电层；在第二介电层中形成第一开口，所述第一开口暴露出第一导电特征、第二导电特征、及第一介电层；在第二介电层上及第一开口中沉积第二晶种层；在第一开口中从第二晶种层的一些部分镀覆第一通孔；将管芯贴合到第二介电层；以及使用包封体包封第一通孔及管芯。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1至图14是根据一些实施例的形成装置封装的工艺期间各中间步骤的各种图。
图15至图18是根据一些实施例的形成封装结构的工艺期间各中间步骤的各种图。
附图标号说明
100：载体衬底
102：释放层
104、112：介电层
106、118：晶种层
108：金属化图案
108A：第一重布线
108B：第二重布线
110：间隙
114A、150A：第一开口
114B、150B：第二开口
116：背侧重布线结构
120：光刻胶
122、306：穿孔
122A：第一通孔
122B：第二通孔
124：集成电路管芯
126：粘着剂
128：半导体衬底
130：内连线结构
132：接垫
134：钝化膜
136：管芯连接件
138：介电材料
140：包封体
142：前侧重布线结构
144：凸块下金属
146：导电连接件
148：胶带
150：开口
200、300：装置封装
302：衬底
303、502：结合接垫
304A：主体铜部分
304B：镍表面处理
308A、308B：堆叠管芯
310：导线结合件
312：模塑材料
314：导电连接件
316：底部填充胶材料
318A、318B：金属间化合物
320：单体化工艺
322：狭槽
400：封装结构
500：衬底/封装衬底
600：封装区
DI、DO：距离
WA、WG、WO、WP：宽度
WB：组合宽度
具体实施方式
以下公开内容提供用于实作本发明的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。此种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)，且本文中所使用的空间相对性描述语可同样相应地进行解释。
根据一些实施例，公开半导体封装及其形成方法。具体来说，形成具有重布线的第一重布线结构。形成从第一导电特征(conductive feature)的表面延伸的第一通孔。形成从第二导电特征与第三导电特征之间的间隙延伸的第二通孔。第二通孔比第一通孔长。将例如焊料等导电连接件贴合到第一重布线结构的背侧。将第一导电连接件耦合到第一导电特征，且相对于第一通孔偏置。这样一来，在回焊(reflow)期间形成的金属间化合物(intermetallic compound，IMC)不在侧向上延伸到第一通孔。将第二导电连接件耦合到第二导电特征及第三导电特征，且所述第二导电连接件与第二通孔对齐。这样一来，当在回焊期间形成金属间化合物时，铜会从第二通孔扩散，而不会从第二导电特征及第三导电特征扩散。避免铜从第二导电特征及第三导电特征扩散可避免在形成通孔期间使用的晶种层层离(delamination)。
图1至图14是根据一些实施例的形成装置封装200的工艺期间各中间步骤的各种图。图1至图14是剖视图。可将装置封装200称作集成扇出(integrated fan-out，InFO)型封装。
在图1中，示出处于加工的中间阶段的装置封装200，装置封装200包括形成在载体衬底100上的释放层(release layer)102。用于形成装置封装200的封装区600也被例示出。尽管仅示出一个封装区，然而也可形成有许多封装区。
载体衬底100可为玻璃载体衬底、陶瓷载体衬底等。载体衬底100可为晶片，使得可在载体衬底100上同时形成多个封装。释放层102可由聚合物系材料形成，所述聚合物系材料可与载体衬底100一起从将在后续步骤中形成的上覆结构被移除。在一些实施例中，释放层102是会在受热时失去其粘着特性的环氧树脂系热释放材料，例如光热转换(light-to-heat-conversion，LTHC)释放涂层。在其他实施例中，释放层102可为会在被暴露至紫外光时失去其粘着特性的紫外光(ultra-violet，UV)胶。释放层102可作为液体进行分配并进行固化，释放层102可为被叠层到载体衬底100上的叠层体膜(laminate film)，或可为其他形式。释放层102的顶表面可以是等高(leveled)且释放层102的顶表面可具有高共面程度(degree of coplanarity)。
在图2中，在释放层102上形成介电层104。介电层104的底表面可接触释放层102的顶表面。在一些实施例中，介电层104是由例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene，BCB)等聚合物形成。在其他实施例中，介电层104是由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)等；或者类似材料。可通过例如旋转涂布(spin coating)、化学气相沉积(chemical vapor deposition，CVD)、叠层(laminating)、类似工艺、或其组合等任何可接受的沉积工艺来形成介电层104。
在图3中，在介电层104之上形成晶种层106。在一些实施例中，晶种层106为金属层，所述金属层可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层106包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积(physical vapordeposition，PVD)等来形成晶种层106。
在图4中，在介电层104之上形成金属化图案108。在晶种层106上形成光刻胶(图中未示出)并将所述光刻胶图案化。可通过旋转涂布(spin coating)等来形成光刻胶并可将所述光刻胶暴露至光以进行图案化。光刻胶的图案对应于金属化图案108。所述图案化会形成穿过光刻胶的开口以暴露出晶种层106。在光刻胶的开口中及晶种层106的被暴露部分上形成导电材料。可通过例如电镀(electroplating)或无电镀覆(electroless plating)等镀覆工艺来形成所述导电材料。所述导电材料可为金属或金属合金，例如铜、钛、钨、铝等或其组合。接着，移除光刻胶以及晶种层106的上面未形成有导电材料的部分。可通过例如使用氧等离子体等的可接受灰化工艺(ashing process)或剥除工艺(stripping process)来移除光刻胶。一旦光刻胶被移除，则例如使用可接受的刻蚀工艺(如通过湿刻蚀(wetetching)或干刻蚀(dry etching))来移除晶种层106的被暴露部分。晶种层106的其余部分及导电材料会形成金属化图案108。
可将金属化图案108的导电特征称作重布线层或重布线。可不将重布线形成为具有均匀的宽度，且所述重布线中的一些重布线可包括多个导电特征。第一重布线108A可各自包括单一导电特征，所述单一导电特征将电连接到装置封装200的各装置。第二重布线108B可各自包括通过间隙110而隔开的多个导电特征，且所述多个导电特征电连接在一起并电连接到装置封装200的各装置。第二重布线108B的组合宽度WB实质上等于第一重布线108A的宽度WA，或者可有所不同。
在一些实施例中，在形成金属化图案108期间单独地形成第二重布线108B的导电特征，例如每一导电特征可对应于光刻胶中的暴露出晶种层106的开口。在一些实施例中，在形成金属化图案108期间形成单一导电特征，且之后使用可接受的刻蚀技术形成间隙110以将所述单一导电特征划分成多个导电特征。间隙110被形成为具有宽度WG。间隙110可从第二重布线108B的顶表面延伸到第二重布线108B的底表面，从而暴露出介电层104。间隙110可形成在第二重布线108B的中心中，使得第二重布线108B的各导电特征为相同长度，或者可被形成为相对于第二重布线108B的中心偏置，使得第二重布线108B的各导电特征为不同长度。
在图5中，在金属化图案108及介电层104上形成介电层112。在一些实施例中，介电层112是由聚合物形成，所述聚合物可为例如聚苯并恶唑、聚酰亚胺、苯并环丁烯等可使用光刻掩模(lithography mask)进行图案化的感光性材料。在其他实施例中，介电层112是由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃；或者类似材料。可通过旋转涂布、叠层、化学气相沉积、类似工艺、或其组合来形成介电层112。
接着将介电层112图案化以形成暴露出金属化图案108的一些部分的开口114。通过可接受的工艺来进行所述图案化，例如当介电层112为感光性材料时通过将所述介电层暴露至光来进行所述图案化，或者通过使用例如各向异性刻蚀(anisotropic etch)进行刻蚀来进行所述图案化。形成暴露出第一重布线108A的第一开口114A，且形成暴露出第二重布线108B的第二开口114B。第二开口114B形成在第二重布线108B的间隙110之上；这样一来，导电特征的侧边被暴露出，所述导电特征的顶表面的一些部分被暴露出，且介电层104的一些部分被暴露出。在所说明实施例中，第一开口114A与第二开口114B各自具有相同的宽度WO。在其他实施例中，第一开口114A与第二开口114B具有不同的宽度。开口114的宽度WO比间隙110的宽度WG大。
开口114可形成在金属化图案108中的每一者的中心之上，或者可被形成为相对于所述中心偏置。在所示实施例中，第一开口114A被形成为相对于金属化图案108的中心偏置，且第二开口114B形成在金属化图案108的中心之上。
可将介电层104及112以及金属化图案108称作背侧重布线结构(back-sideredistribution structure)116。如图所示，背侧重布线结构116包括所述两个介电层104及112以及一个金属化图案108。在其他实施例中，背侧重布线结构116可包括任何数目的介电层、金属化图案、及通孔。可通过重复进行所述形成金属化图案108及介电层112的工艺而在背侧重布线结构116中形成一个或多个额外的金属化图案及介电层。可在所述形成金属化图案期间通过在下伏介电层的开口中形成所述晶种层以及所述金属化图案的导电材料来形成通孔。所述通孔可因此对各种金属化图案进行内连及电耦合。
在图6中，在背侧重布线结构116之上及开口114中形成晶种层118。晶种层118位于介电层112之上、金属化图案108的被暴露部分之上、及介电层104的被暴露部分之上。在一些实施例中，晶种层118为金属层，所述金属层可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层118包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积等来形成晶种层118。
在图7中，在晶种层118上形成光刻胶120并将光刻胶120图案化。可通过旋转涂布等来形成光刻胶120并可将光刻胶120暴露至光以进行图案化。光刻胶120的图案对应于随后将形成的穿孔。所述图案化会形成穿过光刻胶120的开口以暴露出晶种层118。在介电层112中在开口114之上设置穿过光刻胶120的开口，且各所述开口可在第一开口114A与第二开口114B二者之上具有相同宽度WP。所述开口的宽度WP比开口114的宽度WO大。
在图8中，在光刻胶120的开口中及晶种层118的被暴露部分上形成导电材料。可通过例如电镀或无电镀覆等镀覆工艺来形成所述导电材料。所述导电材料可为金属或金属合金，例如铜、钛、钨、铝等或其组合。移除光刻胶120以及晶种层118的上面未形成有导电材料的一些部分。可通过例如使用氧等离子体等的可接受灰化工艺或剥除工艺来移除光刻胶。一旦光刻胶被移除，则例如使用可接受的刻蚀工艺(例如通过湿刻蚀或干刻蚀)来移除晶种层118的被暴露部分。晶种层的其余部分与导电材料会形成穿孔122，穿孔122电连接到重布线。
由于晶种层118形成在第二重布线108B的间隙110中，因此会形成延伸穿过第二重布线108B的第二通孔122B。相反，在第一重布线108A上会形成第一通孔122A，且第一通孔122A不延伸穿过第一重布线108A。第一通孔122A与第二通孔122B二者可在介电层112之上具有相同宽度WP，且在开口114中具有相同宽度WO。第二通孔122B还在间隙110中具有宽度WG。由于第二通孔122B具有分别递减的三种不同的宽度，因此可将第二通孔122B称作具有梯形结构(ladder structure)。由于第一开口114A被形成为相对于金属化图案108的中心偏置，因此第一通孔122A被形成为相对于第一重布线108A的中心偏置。
尽管将第一通孔122A示为在宽度上具有一种变化且将第二通孔122B示为在宽度上具有两种变化，然而应知，在其他实施例中，第一通孔122A与第二通孔122B可在宽度上具有任意变化量。根据实施例，第二通孔122B在宽度上具有比第一通孔122A多的变化。
在图9中，通过粘着剂126将集成电路管芯124粘着到介电层112。如图9所示，在封装区600中粘着一个集成电路管芯124。在其他实施例中，可在每一区中粘着多个集成电路管芯124。集成电路管芯124可为裸管芯，例如逻辑管芯(例如，中央处理器(centralprocessing unit)、微控制器等)、存储器管芯(例如，动态随机存取存储器(dynamicrandom access memory，DRAM)管芯、静态随机存取存储器(static random accessmemory，SRAM)管芯等)、电力管理管芯(例如，电力管理集成电路(power managementintegrated circuit，PMIC)管芯)、射频(radio frequency，RF)管芯、传感器管芯、微机电系统(micro-electro-mechanical-system，MEMS)管芯、信号处理管芯(例如，数字信号处理(digital signal processing，DSP)管芯)、前端管芯(例如，模拟前端(analog front-end，AFE)管芯)等或其组合。此外，在一些实施例中，集成电路管芯124在不同封装区(图中未示出)中可为不同大小(例如，不同高度及/或表面积)，且在其他实施例中，集成电路管芯124可为相同大小(例如，相同高度及/或表面积)。
在粘着到介电层112之前，可根据适用于在集成电路管芯124中形成集成电路的制造工艺来加工集成电路管芯124。举例来说，集成电路管芯124各自包括半导体衬底128，例如经掺杂的或未经掺杂的硅、或绝缘体上半导体(semiconductor-on-insulator，SOI)衬底的有源层。半导体衬底可包含：其他半导体材料，例如锗；化合物半导体，包括碳化硅、镓砷、磷化镓、磷化铟、砷化铟、及/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或者其组合。也可使用例如多层式衬底(multi-layeredsubstrate)或梯度衬底(gradient substrate)等其他衬底。可在半导体衬底128中及/或半导体衬底128上形成例如晶体管、二极管、电容器、电阻器等装置且可通过由例如位于半导体衬底128上的一个或多个介电层中的金属化图案所形成的内连线结构130将各所述装置进行内连以形成集成电路。
集成电路管芯124还包括与外部连接的接垫132(例如，铝接垫)。接垫132位于可被称作集成电路管芯124的相应有源侧的部位上。钝化膜(passivation film)134位于集成电路管芯124上及接垫132的一些部分上。开口穿过钝化膜134到达接垫132。例如导电柱(例如，包含例如铜等金属)等管芯连接件136位于穿过钝化膜134的开口中，并且机械地耦合到且电耦合到相应接垫132。可通过例如镀覆等来形成管芯连接件136。管芯连接件136对集成电路管芯124的相应集成电路进行电耦合。
介电材料138位于集成电路管芯124的有源侧上，例如位于钝化膜134及管芯连接件136上。介电材料138在侧向上包封管芯连接件136，且介电材料138在侧向上与相应集成电路管芯124相接。可首先将介电材料138形成为掩埋或覆盖管芯连接件136；当管芯连接件136被掩埋时，介电材料138的顶表面可具有不均匀拓扑(topology)。介电材料138可为聚合物(例如聚苯并恶唑、聚酰亚胺、苯并环丁烯等)、氮化物(例如氮化硅等)，氧化物(例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃等)、类似材料、或其组合，且可例如通过旋转涂布、叠层、化学气相沉积等来形成。
粘着剂126位于集成电路管芯124的背侧上并将集成电路管芯124粘着到背侧重布线结构116(例如图中的介电层112)。粘着剂126可为任何适合的粘着剂、环氧树脂、管芯贴合膜(die attach film，DAF)等。粘着剂126可被涂覆到集成电路管芯124的背侧，例如涂覆到相应半导体晶片的背侧或者可镀覆在载体衬底100的表面之上。可例如通过锯切(sawing)或切割(dicing)而将集成电路管芯124单体化，并使用例如拾取及放置工具(pick-and-place tool)通过粘着剂126而将集成电路管芯124粘着到介电层112。
尽管以上将集成电路管芯124说明及阐述为裸管芯(例如，未经封装管芯)，然而在其他实施例中，集成电路管芯124可为经封装芯片(例如，与例如重布线结构、无源装置等其他封装特征集成在一起的一个或多个裸管芯)。举例来说，集成电路管芯124可为包括多个经堆叠且经内连存储器管芯的存储器封装(例如，混合存储器立方(hybrid memorycube))。
在图10中，在各种组件上形成包封体(encapsulant)140。包封体140可为模塑化合物、环氧树脂等，且可通过压缩模塑(compression molding)、传递模塑(transfermolding)等来涂覆。包封体140可形成在载体衬底100之上，从而隐埋或覆盖集成电路管芯124的管芯连接件136及/或穿孔122。接着将包封体140固化。
在图11中，对包封体140执行平坦化工艺(planarization process)以暴露出穿孔122及管芯连接件136。所述平坦化工艺也可对介电材料138进行研磨。在平坦化工艺之后，穿孔122的顶表面、管芯连接件136的顶表面、介电材料138的顶表面、及包封体140的顶表面是共面的(coplanar)。平坦化工艺可为例如化学机械抛光(chemical-mechanical polish，CMP)、研磨工艺(grinding process)等。在一些实施例中，例如如果已暴露出穿孔122及管芯连接件136，则可省略所述平坦化。如上所述，第二通孔122B延伸穿过金属化图案108。这样一来，在平坦化工艺之后，当第一通孔122A及第二通孔122B连接到背侧重布线结构116的同一金属化层时，第二通孔122B比第一通孔122A长。
在图12中，在包封体140、穿孔122、及管芯连接件136上形成前侧重布线结构(front-side redistribution structure)142。前侧重布线结构142包括多个介电层及金属化图案。举例来说，前侧重布线结构142可被图案化成通过相应一个或多个介电层而彼此隔开的多个分立的金属化图案。
在一些实施例中，介电层是由聚合物形成，所述聚合物可为例如聚苯并恶唑、聚酰亚胺、苯并环丁烯等可使用光刻掩模进行图案化的感光性材料。在其他实施例中，介电层是由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃；或者类似材料。可通过旋转涂布、叠层、化学气相沉积等或其组合来形成介电层。
在形成之后，将介电层图案化以暴露出下伏导电特征。将底部介电层图案化以暴露出穿孔122的一些部分及管芯连接件136的一些部分，且将一个或多个中间介电层图案化以暴露出下伏金属化图案的一些部分。可通过可接受的工艺来进行所述图案化，例如当介电层为感光性材料时通过将所述介电层暴露至光来进行所述图案化，或者通过使用例如各向异性刻蚀进行刻蚀来进行所述图案化。如果介电层为感光性材料，则所述介电层可在曝光之后显影。
在每一介电层上形成具有通孔的金属化图案。在介电层之上及穿过所述介电层的开口中形成晶种层(图中未示出)。在一些实施例中，晶种层为金属层，所述金属层可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积等沉积工艺来形成晶种层。接着在晶种层上形成光刻胶并将所述光刻胶图案化。可通过旋转涂布等来形成光刻胶并可将所述光刻胶暴露至光以进行图案化。光刻胶的图案对应于金属化图案。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中及晶种层的被暴露部分上形成导电材料。可通过例如电镀或无电镀覆等镀覆工艺来形成所述导电材料。所述导电材料可包括金属或金属合金，例如铜、钛、钨、铝等或其组合。接着，移除光刻胶以及晶种层的上面未形成有导电材料的一些部分。可通过例如使用氧等离子体等的可接受灰化工艺或剥除工艺来移除光刻胶。一旦光刻胶被移除，则例如使用可接受的蚀刻工艺(例如通过湿蚀刻或干蚀刻)来移除晶种层的被暴露部分。晶种层的其余部分与导电材料形成前侧重布线结构142的一个金属化层阶的金属化图案及通孔。
示出前侧重布线结构142作为实例。可在前侧重布线结构142中形成比所示出的更多或更少的介电层及金属化图案。所属领域中的普通技术人员将易于理解，哪些步骤及工艺将被省略或重复进行以形成更多或更少的介电层及金属化图案。
将前侧重布线结构142的顶部介电层图案化以暴露出金属化图案的一些部分从而形成导电接垫。导电接垫用于耦合到导电连接件，且可被称作凸块下金属(under bumpmetallurgy，UBM)144。可通过可接受的工艺来进行所述图案化，例如当顶部介电层为感光性材料时通过将所述顶部介电层暴露至光来进行所述图案化，或者通过使用例如各向异性刻蚀进行刻蚀来进行所述图案化。如果顶部介电层为感光性材料，则所述顶部介电层可在曝光之后显影。接着在前侧重布线结构142的外侧(exterior side)上形成凸块下金属144。凸块下金属144被形成为延伸穿过顶部介电层中的开口以接触前侧重布线结构142的金属化层。
作为形成凸块下金属144的实例，在顶部介电层之上以及穿过所述顶部介电层的开口中形成晶种层(图中未示出)。在一些实施例中，晶种层为金属层，所述金属层可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积等沉积工艺来形成晶种层。接着在晶种层上形成光刻胶并将所述光刻胶图案化。可通过旋转涂布等来形成光刻胶并可将所述光刻胶暴露至光以进行图案化。光刻胶的图案对应于前侧重布线结构142中的导电接垫的图案。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中及晶种层的被暴露部分上形成导电材料。可通过例如电镀或无电镀覆等镀覆工艺来形成所述导电材料。所述导电材料可包括金属或金属合金，例如铜、钛、钨、铝等或其组合。接着，移除光刻胶以及晶种层的上面未形成有导电材料的一些部分。可通过例如使用氧等离子体等的可接受灰化工艺或剥除工艺来移除光刻胶。一旦光刻胶被移除，则例如使用可接受的蚀刻工艺(例如通过湿蚀刻或干蚀刻)来移除晶种层的被暴露部分。晶种层的其余部分与导电材料形成凸块下金属144。
在凸块下金属144上形成导电连接件146。导电连接件146可为球栅阵列封装连接件、焊料球、金属柱、受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、微凸块、无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块等。导电连接件146可由金属或金属合金形成，所述金属或金属合金例如为焊料、铜、铝、金、镍、银、钯、锡等或其组合。在一些实施例中，通过首先使用例如蒸镀(evaporation)、电镀、印刷、焊料转移(solder transfer)、植球(ball placement)等常用方法形成焊料层来形成导电连接件146。一旦已在结构上形成焊料层，则可执行回焊以便将所述材料造型成所期望凸块形状。在另一实施例中，导电连接件146为通过溅镀、印刷、电镀、无电镀覆、化学气相沉积等而形成的金属柱(例如铜柱)。所述金属柱可不具有焊料且具有实质上垂直的侧壁。在一些实施例中，在凸块下金属144的顶部上形成金属顶盖层(metal cap layer)(图中未示出)。金属顶盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，且可通过镀覆工艺来形成。
在图13中，执行载体衬底剥离(carrier substrate de-bonding)以将载体衬底100从背侧重布线结构116(例如，介电层104)脱离(剥离)。根据一些实施例，所述剥离包括将例如激光或紫外光等光投射在释放层102上以使得释放层102在光的热量下分解，且载体衬底100可被移除。接着将所述结构翻转并放置在胶带148上。
进一步在图13中，形成穿过介电层104的开口150以暴露出金属化图案108的一些部分。可例如使用激光钻孔(laser drilling)、可接受的刻蚀技术等来形成所述开口。形成暴露出第一重布线108A的第一开口150A，且形成暴露出第二重布线108B的第二开口150B。第一开口150A被形成为相对于第一通孔122A的中心偏置，使得第一开口150A设置成与介电层112中的第一通孔122A的一些部分相距距离DO。第二开口150B形成在第二通孔122B的中心下方，使得暴露出延伸穿过第二重布线108B的晶种层118以及晶种层106的一些部分。
在图14中，将被开口150暴露出的晶种层106及118的一些部分薄化或完全移除。可通过可接受的刻蚀工艺(例如通过湿刻蚀或干刻蚀)将晶种层106及118的所述被暴露部分薄化或移除。在其中晶种层106及118包括多个层的实施例中，刻蚀工艺可移除被暴露的多个层中的一些层或所有层。在其中晶种层106及118包括位于介电层104之上的钛层及位于所述钛层之上的铜层的实施例中，刻蚀工艺可移除所述钛层且使所述铜层保持原样，由此将所述层薄化。在此种实施例中，使用对于钛层来说具有选择性的一种或多种刻蚀剂(例如，以比刻蚀所述铜层的速率实质上更高的速率刻蚀所述钛层的刻蚀剂)来执行刻蚀工艺。在其他实施例中，完全移除晶种层106及118的被暴露部分(例如，移除所有层)。
图15至图18是根据一些实施例的形成封装结构400的工艺期间各中间步骤的各种图。图15至图18是剖视图。封装结构400可指代叠层封装(PoP)结构。
在图15中，将装置封装300结合到装置封装200。可在每一封装区600中将装置封装300结合到装置封装200。装置封装300包括衬底302及耦合到衬底302的一个或多个堆叠管芯308(308A及308B)。尽管例示出单个管芯堆叠308(308A及308B)，然而在其他实施例中，可并排地设置与衬底302的同一表面耦合的多个堆叠管芯308(各自具有一个或多个堆叠管芯)。
衬底302可由例如硅、锗、金刚石等半导体材料制成。在一些实施例中，也可使用化合物材料，例如硅锗、碳化硅、镓砷、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、这些的组合等。另外，衬底302可为绝缘体上硅(silicon-on-insulator，SOI)衬底。通常，绝缘体上硅衬底包括一层半导体材料，例如外延硅、锗、硅锗、绝缘体上硅、绝缘体上硅锗(silicongermanium on insulator，SGOI)、或其组合。在一个替代性实施例中，衬底302是基于绝缘芯，例如玻璃纤维强化树脂芯(fiberglass reinforced resin core)。一种示例性芯材料是玻璃纤维树脂，例如FR4。所述芯材料的替代方案包括双马来酰亚胺-三嗪(bismaleimide-triazine，BT)树脂，或作为另一选择，包括其他印刷电路板(PCB)材料或膜。可对衬底302使用例如味之素增层膜(Ajinomoto build-up film，ABF)等的增层膜或其他叠层体。
衬底302可包括有源装置及/或无源装置(图中未示出)。如所属领域中的普通技术人员应意识到，可使用各种各样的装置(例如晶体管、电容器、电阻器、这些的组合等)来产生装置封装300的设计的结构性要求及功能性要求。可使用任何适合的方法来形成所述装置。
衬底302还可包括金属化层(图中未示出)及穿孔306。所述金属化层可形成在有源装置及无源装置之上且被设计成连接各种装置以形成功能性电路系统。金属化层可由交替的介电质(例如，低介电常数介电材料(low-k dielectric material))层与导电材料(例如，铜)层形成且可通过任何适合的工艺(例如，沉积、镶嵌(damascene)、双重镶嵌(dualdamascene)等)来形成，其中通孔对各所述导电材料层进行内连。在一些实施例中，衬底302实质上不具有有源装置及无源装置。
衬底302可具有位于衬底302的第一侧上以耦合到堆叠管芯308的结合接垫303以及位于衬底302的第二侧上以耦合到导电连接件314的结合接垫304，所述第二侧与衬底302的第一侧相对。在一些实施例中，结合接垫303及304是通过向衬底302的第一侧及第二侧上的介电层(图中未示出)中形成凹槽(图中未示出)而形成。所述凹槽可被形成为容许结合接垫303及304被嵌入到所述介电层中。在其他实施例中，由于结合接垫303及304可形成在所述介电层上，因而所述凹槽被省略。在一些实施例中，结合接垫303及304包括由铜、钛、镍、金、钯等或其组合制成的薄晶种层(图中未示出)。可在所述薄晶种层之上沉积结合接垫303及304的导电材料。可通过电化学镀覆工艺(electro-chemical plating process)、无电镀覆工艺、化学气相沉积、原子层沉积(atomic layer deposition，ALD)、物理气相沉积等或其组合来形成导电材料。结合接垫303及304的导电材料可为铜、钨、铝、银、金、镍等或其组合。
在实施例中，结合接垫304及304为包括三个导电材料层的凸块下金属，所述三个导电材料层例如为钛层、铜层、及镍层。举例来说，结合接垫304可包括钛层(图中未示出)、主体铜部分304A、及镍表面处理(nickel finish)304B。镍表面处理304B可提高装置封装300的货架寿命(shelf life)，此在装置封装300为例如DRAM模组等存储器装置时可格外有利。然而，所属领域中的普通技术人员应意识到尚有许多适合于形成凸块下金属303及304的适合的材料与层的排列方式，例如铬/铬-铜合金/铜/金的排列方式、钛/钛钨/铜的排列方式、或铜/镍/金的排列方式。可用于凸块下金属304及304的任何适合的材料或材料层完全旨在包含于当前申请的范围内。在一些实施例中，穿孔306延伸穿过衬底302且将至少一个结合接垫303耦合到至少一个结合接垫304。
在所说明实施例中，尽管可使用例如导电凸块等其他连接方式，然而堆叠管芯308是通过导线结合件(wire bond)310而耦合到衬底302。在实施例中，堆叠管芯308是堆叠存储器管芯。举例来说，堆叠存储器管芯308可包括低功率(low-power，LP)双倍数据速率(double data rate，DDR)存储器模块，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4、或类似的存储器模块。如上所述，在此种实施例中，结合接垫304可具有镍表面处理304B。
在一些实施例中，可通过模塑材料312来包封堆叠管芯308及导线结合件310。可例如使用压缩模塑在堆叠管芯308及导线结合件310上模塑出模塑材料312。在一些实施例中，模塑材料312是模塑化合物、聚合物、环氧树脂、氧化硅填充胶材料等或其组合。可执行固化步骤以将模塑材料312固化，其中所述固化可为热固化、紫外光固化等或其组合。
在一些实施例中，将堆叠管芯308及导线结合件310掩埋在模塑材料312中，且在模塑材料312被固化之后，执行平坦化步骤(例如研磨)，以移除模塑材料312的过量部分并为装置封装300提供实质上平坦的表面。
在形成装置封装300之后，通过导电连接件314、结合接垫304及金属化图案108将装置封装300机械地结合到且电结合到装置封装200。在一些实施例中，通过导线结合件310、结合接垫303及304、穿孔306、导电连接件314、穿孔122、前侧重布线结构142将堆叠存储器管芯308耦合到集成电路管芯124。
尽管导电连接件314与导电连接件146无需相同，然而导电连接件314可相似于上述导电连接件146且本文中不再对其予以赘述。导电连接件314可设置在衬底302的与堆叠存储器管芯308相对的侧上。在一些实施例中，还可在衬底302的与堆叠存储器管芯308相对的所述侧上形成阻焊剂(solder resist)(图中未示出)。可在阻焊剂(图中未示出)中的开口中将导电连接件314设置成电耦合到且机械地耦合到衬底302中的导电特征(例如，结合接垫304)。阻焊剂可用于保护衬底302的各区域免受外部损坏影响。
在一些实施例中，在对导电连接件314进行结合之前，使用例如免清洗焊剂(no-clean flux)等焊剂(图中未示出)来涂布导电连接件314。可将导电连接件314浸入焊剂中，或可将所述焊剂喷射到导电连接件314上。在另一实施例中，可将焊剂涂覆到金属化图案108的表面。
在一些实施例中，导电连接件314上可在其被回焊之前先形成有可选的环氧树脂焊剂(图中未示出)，其中所述环氧树脂焊剂的环氧树脂部分中的至少一些环氧树脂部分在装置封装300贴合到装置封装200之后被保留。此保留的环氧树脂部分可充当底部填充胶(underfill)，以减小因对导电连接件314进行回焊而产生的应力并保护因对导电连接件314进行回焊而产生的接头(joint)。
可选地，可在装置封装200与300之间形成底部填充胶材料316。在实施例中，底部填充胶材料316是用于减缓运行及环境劣化(例如，因运行期间的产热而造成的应力)对装置封装200及300的影响且支撑装置封装200及300的保护性材料。底部填充胶材料316可被注射到装置封装200与300之间的空间中或以另一种方式形成在所述空间中，且底部填充胶材料316可例如为分配在装置封装200与300之间且被接着固化而变硬的液态环氧树脂。
图16A、图16B、图16C、及图16D是在执行结合工艺以将装置封装200与300实体地耦合且电耦合之后导电连接件314及金属化图案108的细节图。装置封装200与300之间的结合可为焊料结合。在实施例中，通过回焊工艺将装置封装300结合到装置封装200。图16A及图16B分别为示出第一重布线108A的连接的剖视图及平面图。图16C及图16D分别为示出第二重布线108B的连接的剖视图及平面图。
在图16A、图16B、图16C、及图16D中，执行结合工艺以将导电连接件314回焊成接触结合接垫304及金属化图案108。在结合工艺之后，在金属化图案108与导电连接件314的界面处可形成金属间化合物(IMC)318。由于晶种层106及118的被暴露部分被局部移除或完全移除，因此金属间化合物318可局部地或完全地延伸穿过金属化图案108。金属间化合物318还可相对于第一开口150A的侧在侧向上沿金属化图案108延伸距离DI。
通过结合工艺形成的结合件包括与两种不同金属接触的导电连接件314(例如，焊料)。在实施例中，金属化图案108是由铜形成，且结合接垫304具有镍表面处理304B，从而形成镍-焊料-铜连接。当形成有此种连接时，在回焊期间铜会从金属化图案108扩散到导电连接件314中并朝镍表面处理304B扩散。在导电连接件314中在实箭头所示方向上会形成铜扩散梯度。过量的铜从金属化图案108扩散到接近晶种层118可能会使晶种层118从金属化图案108层离。具体来说，铜从位于晶种层118与介电层104之间的金属化图案108的一些部分扩散可能会使晶种层118层离。
在图16A及图16B中，将介电层104中的第一开口150A设置成在侧向上与介电层112中的第一通孔122A的一些部分相距距离DO。这样一来，导电连接件314被设置成在平面图中在侧向上与第一通孔122A的侧相距距离DO，且不沿第一通孔122A的纵向轴线设置。距离DO被选择成足够大以使得金属间化合物318A不在侧向上延伸到第一通孔122A的侧。换句话说，距离DO比距离DI大，且可为距离DI的至少两倍大。在实施例中，距离DI可介于约2微米(μm)至约13μm范围内(例如，为约13μm)，且距离DO可介于约25μm至约35μm范围内(例如，为约35μm)。将第一开口150A(参见例如图13)形成为使得金属间化合物318A不在侧向上延伸到第一通孔122A的侧可避免铜从位于晶种层118与介电层104之间的第一重布线108A的一些部分扩散，从而避免晶种层118层离。
在图16C及图16D中，将介电层104中的第二开口150B设置成在侧向上对齐第二重布线108B中的间隙110。这样一来，在平面图中导电连接件314在侧向上不与第二通孔122B的侧间隔开，且沿第二通孔122B的纵向轴线设置。由于晶种层106及118的被暴露部分被局部移除或完全移除，因此金属间化合物318B在纵向方向上延伸到第二通孔122B中。将金属间化合物318B形成为延伸到第二通孔122B中可使一些铜从第二通孔122B而非从金属化图案108扩散出。此可减少从金属化图案108扩散的铜，从而避免晶种层118层离，并且还会避免第二重布线108B的厚度减小。
如图所示，金属化图案108还包括狭槽322，狭槽322设置在导电连接件314及穿孔122的周边周围。狭槽322提供应力缓和，从而提高电连接的可靠性。具体来说，狭槽322为金属化图案108提供额外的侧壁，从而改善金属化图案108与例如介电层112等聚酰亚胺材料之间的粘着。狭槽322被设置成至少局部地围绕第一重布线108A中的导电连接件314，且可被设置成完全围绕第二重布线108B中的导电连接件314。
在图17中，通过沿例如位于相邻封装区之间的切割道区(scribe line region)进行单体化来执行单体化工艺(singulation process)320。在一些实施例中，单体化工艺320包括锯切工艺、激光工艺或其组合。单体化工艺320将封装区600从相邻封装区(图中未示出)单体化。示出在单体化之后的所得封装结构400，所得封装结构400可来自于封装区600。
图18示出贴合到衬底500之后的封装结构400。可将衬底500称为封装衬底500。通过使用导电连接件146将装置封装200安装到衬底500而将封装结构400贴合到衬底500。
封装衬底500可由例如硅、锗、金刚石等半导体材料制成。作为另外一种选择，也可使用例如硅锗、碳化硅、镓砷、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、其组合等化合物材料。另外，封装衬底500可为绝缘体上硅衬底。一般来说，绝缘体上硅衬底包括例如外延硅、锗、硅锗、绝缘体上硅、绝缘体上硅锗、或其组合等半导体材料的层。在一个替代性实施例中，封装衬底500是基于绝缘芯，例如玻璃纤维强化树脂芯。一种示例性芯材料是玻璃纤维树脂，例如FR4。芯材料的替代方案包括双马来酰亚胺-三嗪BT树脂，或作为另外一种选择，包括其他印刷电路板材料或膜。可对封装衬底500使用例如味之素增层膜等增层膜或其他叠层体。
封装衬底500可包括有源装置及无源装置(图中未示出)。如所属领域中的普通技术人员应意识到，可使用例如晶体管、电容器、电阻器、其组合等各种各样的装置来产生封装结构400的设计的结构性要求及功能性要求。可使用任何适合的方法来形成所述装置。
封装衬底500也可包括金属化层及通孔(图中未示出)以及位于所述金属化层及通孔之上的结合接垫502。所述金属化层可形成在有源装置及无源装置之上且被设计成连接各种装置以形成功能性电路系统。金属化层可由交替的介电质(例如，低介电常数介电材料)层与导电材料(例如，铜)层形成且可通过任何适合的工艺(例如，沉积、镶嵌、双重镶嵌等)来形成，其中通孔对各所述导电材料层进行内连。在一些实施例中，封装衬底500实质上不具有有源装置及无源装置。
在一些实施例中，可对导电连接件146进行回焊以将装置封装200贴合到结合接垫502。导电连接件146将封装衬底500(包括位于封装衬底500中的金属化层)电耦合到及/或实体地耦合到装置封装200。在一些实施例中，可在安装在封装衬底500上之前将无源装置(例如，表面安装装置(surface mount device，SMD)(图中未例示))贴合到装置封装200(例如，结合到结合接垫502)。在此种实施例中，可将无源装置结合到装置封装200的与导电连接件146相同的表面。
导电连接件146，导电连接件146上可在其被回焊之前先形成有环氧树脂焊剂(图中未示出)，所述环氧树脂焊剂的环氧树脂部分中的至少一些环氧树脂部分会在将装置封装200贴合到封装衬底500之后被保留。此保留的环氧树脂部分可充当底部填充胶，以减小因对导电连接件146进行回焊而产生的应力并保护因对导电连接件314进行回焊而产生的接头。在一些实施例中，可在装置封装200与封装衬底500之间形成环绕导电连接件146的底部填充胶(图中未示出)。可在贴合装置封装200之后通过毛细管流动工艺(capillary flowprocess)而形成所述底部填充胶，或可在贴合装置封装200之前通过适合的沉积方法而形成所述底部填充胶。
各实施例可实现多个优点。将导电连接件314设置成在平面图中在侧向上与第一通孔122A的侧相距足够的距离DO可避免铜从金属化图案108扩散到接近晶种层118。将金属间化合物318B形成为延伸到第二通孔122B中可使一些铜从第二通孔122B而非从金属化图案108扩散出。减少从位于晶种层118下方的金属化图案108扩散的铜的量可避免晶种层118层离，从而提高所得装置的可靠性。
根据一些实施例，一种半导体封装包括第一装置封装，所述第一装置封装包括：第一重布线结构，包括第一重布线及第二重布线；管芯，位于第一重布线结构上；第一通孔，耦合到第一重布线的第一侧；第二通孔，耦合到第二重布线的第一侧且延伸穿过所述第二重布线；包封体，环绕管芯、第一通孔、及第二通孔；以及第二重布线结构，位于包封体之上，所述第二重布线结构电连接到管芯、第一通孔、及第二通孔。所述装置还包括：第一导电连接件，耦合到第一重布线的第二侧，所述第一导电连接件沿与第一通孔的纵向轴线不同的轴线设置；以及第二导电连接件，耦合到第二重布线的第二侧，所述第二导电连接件沿第二通孔的纵向轴线设置。
在一些实施例中，所述半导体封装还包括：第二装置封装，包括第一结合接垫及第二结合接垫，第一导电连接件耦合到所述第一结合接垫，第二导电连接件耦合到所述第二结合接垫。在一些实施例中，第一结合接垫及第二结合接垫具有镍表面处理。在一些实施例中，第一重布线及第二重布线是由铜形成。在一些实施例中，第一重布线结构还包括：第一介电层，第一重布线及第二重布线设置在所述第一介电层上；以及第二介电层，位于第一介电层上。在一些实施例中，第二通孔比第一通孔长。
根据一些实施例，一种半导体封装的形成方法包括形成第一重布线结构，所述形成第一重布线结构包括：在载体衬底之上沉积第一介电层；在第一介电层上形成第一导电特征；在第一介电层上形成第二导电特征；在第一介电层上形成第三导电特征；以及在第一导电特征、第二导电特征、及第三导电特征上沉积第二介电层。所述半导体封装的形成方法还包括：在第一导电特征上形成第一通孔；在第二导电特征上、第三导电特征上、以及所述第二导电特征与所述第三导电特征之间形成第二通孔；将管芯贴合到邻近第一通孔及第二通孔的第一重布线结构；使用包封体包封管芯、第一通孔、及第二通孔；将包封体、第一通孔、及第二通孔平坦化；以及在包封体、第一通孔、第二通孔、及管芯之上形成第二重布线结构。
在一些实施例中，所述半导体封装的形成方法还包括：将载体衬底从第一重布线结构剥离；以及将装置封装贴合到第一重布线结构，所述装置封装通过第一连接件贴合到第一导电特征，所述装置封装通过第二连接件贴合到第二导电特征及第三导电特征。在一些实施例中，第一连接件不沿第一通孔的纵向轴线设置。在一些实施例中，第二连接件沿第二通孔的纵向轴线设置。在一些实施例中，在平坦化之后，第一通孔比第二通孔长。
根据一些实施例，一种半导体封装的形成方法包括：在第一介电层上沉积第一晶种层；在第一晶种层上镀覆第一导电特征及第二导电特征；在第一导电特征及第二导电特征上沉积第二介电层；在第二介电层中形成第一开口，所述第一开口暴露出第一导电特征、第二导电特征、及第一介电层；在第二介电层上及第一开口中沉积第二晶种层；在第一开口中从第二晶种层的一些部分镀覆第一通孔；将管芯贴合到第二介电层；以及使用包封体包封第一通孔及管芯。
在一些实施例中，所述半导体封装的形成方法还包括：在第一介电层中形成第二开口，所述第二开口暴露出第一晶种层及第二晶种层；对所述第一晶种层的被暴露部分及所述第二晶种层的被暴露部分进行刻蚀，以移除所述第一晶种层的至少一部分及所述第二晶种层的至少一部分；在第二开口中形成能够回焊的材料，所述能够回焊的材料沿第一通孔的纵向轴线设置；以及对能够回焊的材料进行回焊，以从所述能够回焊的材料以及第一晶种层的导电材料、第二晶种层的导电材料、及第一通孔的导电材料形成金属间化合物。在一些实施例中，所述半导体封装的形成方法还包括：使用能够回焊的材料将装置封装贴合到第一导电特征及第二导电特征。在一些实施例中，对能够回焊的材料进行回焊包括将第一通孔的导电材料的一些部分扩散到所述能够回焊的材料中。在一些实施例中，所述半导体封装的形成方法还包括：在第一介电层上形成第三导电特征；在第三导电特征上沉积第二介电层；在第二介电层中形成第二开口，所述第二开口暴露出第三导电特征；在第二开口中沉积第二晶种层；以及在第二开口中从第二晶种层的一些部分镀覆第二通孔。在一些实施例中，所述半导体封装的形成方法还包括：在第一介电层中形成第三开口，所述第三开口暴露出第一晶种层；对所述第一晶种层的被暴露部分进行刻蚀，以移除所述第一晶种层的至少一部分；在第三开口中形成能够回焊的材料，所述能够回焊的材料沿与第二通孔的纵向轴线不同的轴线设置；以及对能够回焊的材料进行回焊，以从所述能够回焊的材料以及第一晶种层的导电材料形成金属间化合物。在一些实施例中，对能够回焊的材料进行回焊包括将第三导电特征的导电材料的一些部分扩散到所述能够回焊的材料中。在一些实施例中，在第二通孔与第一介电层之间不形成任何部分的金属间化合物。在一些实施例中，所述半导体封装的形成方法还包括：将第一通孔、第二通孔、及包封体平坦化，在所述平坦化之后，所述第一通孔比所述第二通孔长。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替、及变更。

Claims (10)

1.一种半导体封装，其特征在于，包括：
第一装置封装，包括：
第一重布线结构，包括第一重布线及第二重布线；
管芯，位于所述第一重布线结构上；
第一通孔，耦合到所述第一重布线的第一侧；
第二通孔，耦合到所述第二重布线的第一侧且延伸穿过所述第二重布线；
包封体，环绕所述管芯、所述第一通孔、及所述第二通孔；以及
第二重布线结构，位于所述包封体之上，所述第二重布线结构电连接到所述管芯、所述第一通孔、及所述第二通孔；
第一导电连接件，耦合到所述第一重布线的第二侧，所述第一导电连接件沿与所述第一通孔的纵向轴线不同的轴线设置；以及
第二导电连接件，耦合到所述第二重布线的第二侧，所述第二导电连接件沿所述第二通孔的纵向轴线设置。
2.根据权利要求1所述的半导体封装，其特征在于，还包括：
第二装置封装，包括第一结合接垫及第二结合接垫，所述第一导电连接件耦合到所述第一结合接垫，所述第二导电连接件耦合到所述第二结合接垫。
3.一种半导体封装的形成方法，其特征在于，包括：
形成第一重布线结构，包括：
在载体衬底之上沉积第一介电层；
在所述第一介电层上形成第一导电特征；
在所述第一介电层上形成第二导电特征；
在所述第一介电层上形成第三导电特征；以及
在所述第一导电特征、所述第二导电特征、及所述第三导电特征上沉积第二介电层；
在所述第一导电特征上形成第一通孔；
在所述第二导电特征上、所述第三导电特征上、以及所述第二导电特征与所述第三导电特征之间形成第二通孔；
将管芯贴合到邻近所述第一通孔及所述第二通孔的所述第一重布线结构；
使用包封体包封所述管芯、所述第一通孔、及所述第二通孔；
将所述包封体、所述第一通孔、及所述第二通孔平坦化；以及
在所述包封体、所述第一通孔、所述第二通孔、及所述管芯之上形成第二重布线结构。
4.根据权利要求3所述的半导体封装的形成方法，其特征在于，还包括：
将所述载体衬底从所述第一重布线结构剥离；以及
将装置封装贴合到所述第一重布线结构，所述装置封装通过第一连接件贴合到所述第一导电特征，所述装置封装通过第二连接件贴合到所述第二导电特征及所述第三导电特征。
5.根据权利要求4所述的半导体封装的形成方法，其特征在于，所述第一连接件不沿所述第一通孔的纵向轴线设置。
6.一种半导体封装的形成方法，其特征在于，包括：
在第一介电层上沉积第一晶种层；
在所述第一晶种层上镀覆第一导电特征及第二导电特征；
在所述第一导电特征及所述第二导电特征上沉积第二介电层；
在所述第二介电层中形成第一开口，所述第一开口暴露出所述第一导电特征、所述第二导电特征、及所述第一介电层；
在所述第二介电层上及所述第一开口中沉积第二晶种层；
在所述第一开口中从所述第二晶种层的一些部分镀覆第一通孔；
将管芯贴合到所述第二介电层；以及
使用包封体包封所述第一通孔及所述管芯。
7.根据权利要求6所述的半导体封装的形成方法，其特征在于，还包括：
在所述第一介电层中形成第二开口，所述第二开口暴露出所述第一晶种层及所述第二晶种层；
对所述第一晶种层的被暴露部分及所述第二晶种层的被暴露部分进行刻蚀，以移除所述第一晶种层的至少一部分及所述第二晶种层的至少一部分；
在所述第二开口中形成能够回焊的材料，所述能够回焊回焊的材料沿所述第一通孔的纵向轴线设置；以及
对所述能够回焊的材料进行回焊，以从所述能够回焊的材料以及所述第一晶种层的导电材料、所述第二晶种层的导电材料、及所述第一通孔的导电材料形成金属间化合物。
8.根据权利要求6所述的半导体封装的形成方法，其特征在于，还包括：
在所述第一介电层上形成第三导电特征；
在所述第三导电特征上沉积所述第二介电层；
在所述第二介电层中形成第二开口，所述第二开口暴露出所述第三导电特征；
在所述第二开口中沉积所述第二晶种层；以及
在所述第二开口中从所述第二晶种层的一些部分镀覆第二通孔。
9.根据权利要求8所述的半导体封装的形成方法，其特征在于，还包括：
在所述第一介电层中形成第三开口，所述第三开口暴露出所述第一晶种层；
对所述第一晶种层的被暴露部分进行刻蚀，以移除所述第一晶种层的至少一部分；
在所述第三开口中形成能够回焊的材料，所述能够回焊的材料沿与所述第二通孔的纵向轴线不同的轴线设置；以及
对所述能够回焊的材料进行回焊，以从所述能够回焊的材料以及所述第一晶种层的导电材料形成金属间化合物。
10.根据权利要求9所述的半导体封装的形成方法，其特征在于，在所述第二通孔与所述第一介电层之间不形成任何部分的所述金属间化合物。
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US20190244935A1 (en) 2019-08-08
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