CN109545744B - A kind of magnetic random access memory cell array and manufacturing method of peripheral circuit connection - Google Patents

Abstract

The present invention provides a manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring, and provides a manufacturing process and an alignment method of a magnetic random access memory device and its surrounding logic circuit between two layers of metals. In the storage area, bottom electrode vias, bottom electrode contacts, magnetic tunnel junction structural units and top electrode vias are sequentially fabricated on the metal connection lines, and aligned in sequence; in the logic circuit area, top electrode vias and bottom electrodes are used The contact is directly connected, and the top electrode through hole, the bottom electrode contact, and the bottom electrode through hole are aligned in sequence; finally, a layer of metal wiring is made on the top electrode through hole to realize the magnetic random access memory between the logic area and the storage area. Connection. Because a layer of bottom electrode contact is added under the magnetic tunnel junction unit array, the direct connection between the copper in the rear section of the CMOS and the bottom of the magnetic tunnel junction array is effectively blocked, which is beneficial to the improvement of the electrical performance and yield of the device.

Description

A kind of magnetic random access memory cell array and manufacturing method of peripheral circuit connection

technical field

The invention relates to a manufacturing method of a magnetic random access memory (MRAM) cell array and peripheral circuit connections, belonging to the technical field of magnetic random access memory (MRAM, Magnetic Radom Access Memory).

Background technique

In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered to be the future solid-state non-volatile memory, which has the characteristics of high-speed read and write, large capacity and low power consumption. Ferromagnetic MTJs are usually sandwich structures, which include: a magnetic memory layer, which can change the direction of magnetization to record different data; an insulating tunnel barrier layer in the middle; a magnetic reference layer, located on the other side of the tunnel barrier layer, Its magnetization direction does not change.

In order to be able to record information in such a magnetoresistive element, a writing method based on a spin-momentum transfer or spin transfer torque (STT, Spin Transfer Torque) conversion technology is proposed, and such MRAM is called STT-MRAM. According to the different magnetic polarization directions, STT-MRAM is divided into in-plane STT-MRAM and vertical STT-MRAM (ie pSTT-MRAM), the latter has better performance. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying a spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the spin-polarized current that needs to be injected for writing or switching operations is also smaller. Therefore, this writing method enables device miniaturization and current reduction at the same time.

At the same time, pSTT-MRAM can fit well with the most advanced technology nodes in terms of scale, since the switching current required to reduce the size of the MTJ element will also decrease. Therefore, it is desirable to make pSTT-MRAM elements very small in size, with very good uniformity, and minimize the influence on the magnetic properties of MTJ, and the adopted preparation method can also achieve high yield, high precision, High reliability, low power consumption, and maintaining a temperature coefficient suitable for good data preservation. At the same time, the write operation in the non-volatile memory is based on the change of the resistance state, so it is necessary to control the damage and shorten the life of the MTJ memory device caused thereby. However, fabricating a small MTJ element may increase the fluctuation of the MTJ resistance, which will lead to large fluctuations in the write voltage or current of the pSTT-MRAM, which will impair the performance of the MRAM.

In the current MRAM manufacturing process, in order to achieve the requirements of MRAM circuit miniaturization, MTJ cells are usually fabricated directly on surface-polished CMOS through holes (VIA _x (x>=1)), that is, the so-called on-axis structure. In a CMOS circuit using a copper process, all through holes (VIA) and wires (M, Metal) are made of metal copper. However, since the size of the MTJ structural unit is smaller than that of the top opening of VIA _x (x>=1), when the magnetic tunnel junction and its bottom electrode are etched, in order to completely isolate the MTJ units, over-etching must be performed. , in over-etching, the area of copper VIA _x (x>=1) that is not covered by the magnetic tunnel junction and its bottom electrode will be partially etched, and its diffusion barrier (Ta/TaN) will also be damaged, This will form a diffusion channel of copper VIA _x (x>=1) to the low-k dielectric outside it, and the Cu atoms will diffuse into the low-k dielectric, which will inevitably affect the electrical properties of the magnetic random access memory, such as: Time-dependent dielectric breakdown (TDDB, TimeDependent Dielectric Breakdown) and electron mobility (EM, Electron Mobility), etc., cause damage.

In addition, during the over-etching process of the magnetic tunnel junction and its bottom electrode, copper atoms and their forming compounds will be sputtered to the sidewalls of the magnetic tunnel junction and the etched low-k material due to ion bombardment (Ion Bombardment). surface, thereby causing contamination and electrical shorting of the entire MRAM device.

SUMMARY OF THE INVENTION

The invention provides a manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring, which provides a manufacturing process and an alignment method of a magnetic random access memory device and its surrounding logic circuits between two layers of metals. In the storage area, a bottom electrode via (BEV, Bottom Electrode Via), a bottom electrode contact (BEC, Bottom Electrode Contact), and a magnetic tunnel junction structure are sequentially fabricated on the metal connection line (M _x (x>=1)). Cell (MTJ) and top electrode via (TEV, Top Electrode Via); BEV, BEC, MTJ and TEV are aligned in sequence; in the logic circuit area, top electrode via (TEV) and bottom electrode contact (BEC) are used to directly connect to each other. The connection method is realized, BEV, BEC and TEV are aligned in sequence; finally, a layer of metal connection (M _x+1 (x>=1)) is made on the top electrode through hole (TEV) to realize the magnetic random access memory logic area and Connections between storage areas.

The present invention includes, but is not limited to, the preparation of magnetic random access memory (MRAM), nor is it limited to any process sequence or process, as long as the prepared product or device is the same or similar to the method prepared by the following preferred process sequence or process, its specific technical scheme is as follows :

A manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring, comprising the following steps:

Step 1: provide a surface-polished CMOS substrate with metal wiring, and make bottom electrode through holes on the substrate, and then fill the bottom electrode through holes with metal;

Step 2: making bottom electrode contacts on bottom electrode vias;

Step 3: fabricating a magnetic tunnel junction structural unit on the bottom electrode contact;

Step 4: forming top electrode through holes and metal interconnects for connecting logic cells/memory cells on the magnetic tunnel junction structure unit.

Further, step 2 includes the following subdivision steps:

Step 2.1: deposit the bottom electrode contact metal; the bottom electrode contact metal is selected from one of Ta, TaN, Ti, TiN, W or WN; the thickness of the bottom electrode contact metal deposition is 20nm-80nm; chemical vapor deposition, physical One of vapor deposition, atomic layer deposition, or ion beam deposition to achieve bottom electrode contact metal deposition;

Step 2.2: Graphically define the bottom electrode contact pattern to align it with the bottom electrode through hole, etch the bottom electrode contact metal to form the bottom electrode contact, and remove residual impurities after etching; the etching uses reactive ion etching or ion beam etching process realization;

Step 2.3: Fill the bottom electrode contact dielectric in the void formed by etching, and planarize the top of the bottom electrode contact dielectric until the top of the bottom electrode contact is flush; the bottom electrode contact dielectric is SiO ₂ , SiON or a low dielectric constant dielectric, low A dielectric constant dielectric refers to a material with a lower dielectric constant than _SiO2 .

Further, in step 3, the magnetic tunnel junction structural unit includes a magnetic tunnel junction multilayer film and a hard mask. Preferably, a seed layer or etch barrier layer is deposited under the magnetic tunnel junction multilayer film.

Further, in step 4, two single damascene or one dual damascene process is used to realize the fabrication of the metal connection.

Beneficial effects of the present invention: Because a layer of bottom electrode contact (BEC) is added under the magnetic tunnel junction unit array, the direct connection between the copper in the rear section of the CMOS and the bottom of the magnetic tunnel junction array is effectively cut off, which is beneficial to the electrical performance and good performance of the device. rate increase.

Description of drawings

The accompanying drawings are schematic diagrams of various steps of a method for manufacturing a magnetic random access memory cell array and a peripheral circuit connection according to a preferred embodiment of the present invention. in:

1(a) to 1(c) are schematic diagrams of steps for making bottom electrode through-hole filling;

2(a) to 2(b) are schematic diagrams of steps for making bottom electrode contacts;

3(a) to 3(c) are schematic diagrams of steps for fabricating a magnetic tunnel junction structural unit;

4(a) to FIG. 4(d) are schematic diagrams of steps of two single damascene processes for fabricating metal interconnects;

FIG. 5 is a schematic diagram of the steps of making a metal connection by a dual damascene process;

Among them, the two dashed curves in Figure 4(d) and Figure 5 indicate that the left and right parts are actually far apart, and only for the convenience of display, the left and right parts are drawn together in the figure; in other figures, the left and right parts are actually The upper and lower curves are also separated. In order to make the figure concise, the two dashed curves are not marked.

DESCRIPTION OF REFERENCE NUMERALS: 100 - Surface-polished CMOS substrate with metal interconnects (M _x (x>=1)); 201 - Bottom Electrode Via (BEV) diffusion barrier; 202 - Bottom Electrode Via (BEV) Dielectric; 203 - Bottom Electrode Via (BEV); 204 - Bottom Electrode Via (BEV) Fill Diffusion Barrier; 205 - Bottom Electrode Via (BEV) Fill; 301 - Bottom Electrode Contact (BEC) Metal Layer; 302 - bottom electrode contact (BEC); 303 - bottom electrode contact (BEC) dielectric; 401 - magnetic tunnel junction (MTJ) multilayer including seed layer; 402 - top hard mask; 403 - dielectric capping layer; 501 - top electrode 502 - Top Electrode Via (TEV); 503 - Top Electrode Via (TEV) Fill Diffusion Barrier; 504 - Top Electrode Via (TEV) Fill; 601 - Metal Connection (M _{x +1} (x>=1)) etch barrier; 602-metal connection (M _x+1 (x>=1)) dielectric; 603-metal connection (M _x+1 (x>=1)) Diffusion Barrier; 604 - Metal Connection (M _x+1 (x>=1)).

Detailed ways

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the accompanying drawings of the present invention are all in a simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

The present invention provides a method for manufacturing a magnetic random access memory cell array and a peripheral circuit connection, which is provided between two layers of metal to perform the manufacturing process and alignment method of a magnetic random access memory device and its surrounding logic circuits; in the storage area, It is realized by making bottom electrode through holes (BEV), bottom electrode contacts (BEC), magnetic tunnel junction structure units (MTJ) and top electrode through holes (TEV) in sequence on the metal connection line (M _x ); in the logic circuit area, the top electrode through hole (TEV) and the bottom electrode contact ( _BEC ) are directly connected. The connection between the logical area and the storage area of the magnetic random access memory. In this way, the BEV, BEC, MTJ, and TEV are sequentially aligned in the storage area, and the BEV, BEC, and TEV are sequentially aligned in the storage area. The present invention includes, but is not limited to, the preparation of magnetic random access memory (MRAM), nor is it limited to any process sequence or process, as long as the prepared product or device is the same or similar to the method prepared by the following preferred process sequence or process, and the specific steps are as follows:

Step 1: Provide a surface-polished CMOS substrate 100 with metal interconnects (M _x (x>=1)), and make a bottom electrode via (BEV, Bottom Electrode Via) 203 thereon, and then use a standard single damascene (SD, SingleDamascene) process for filling of metal copper.

Further, the above-mentioned step 1 can be divided into the following forming steps:

Step 1.1: Deposit a diffusion barrier layer 201 and a bottom electrode through-hole dielectric 202 on the CMOS substrate 100, as shown in FIG. 1(a), wherein the diffusion barrier layer 201 can be used as a barrier for copper in the metal connection (M _x ). The diffusion protection layer of the bottom electrode through hole dielectric 202 can also be used as an etching barrier layer for etching the bottom electrode through hole 203. The thickness of the diffusion barrier layer 201 is 10 nm to 50 nm, and the forming material can be SiN, SiC or SiCN, etc.; The thickness of the electrode through-hole dielectric 202 is 60 nm˜200 nm, and the forming material may be SiO ₂ , SiON, low-k, or the like.

The low dielectric constant (low-k) dielectric refers to a material whose dielectric constant (k) is lower than that of silicon dioxide (k=3.9). Hydrogen Silsequioxane, HSQ, k=2.8～3.0), Methylsilsesquioxane containing Si-CH ₃ functional group (Methylsilsesquioxane, MSQ, k=2.5～2.7), comprehensive hydrosilicates (HSQ) and Hybrid Organic Siloxane Polymer (HOSP) films (k=2.5) and porous SiOCH films (k=2.3-2.7) synthesized with methyl silicates (MSQ) can even be used Organic polymer compounds such as Porous Silicate with ultra-low dielectric constant (k<2.0) and porous SiOCH film with dielectric constant (k) of 1.9.

Step 1.2: Graphically define the bottom electrode through hole (BEV) 203 pattern in the storage area and the logic area at the same time, and etch to form the bottom electrode through hole (BEV) 203, as shown in Figure 1(b), after etching, generally Residual polymer is removed using a dry process and/or a wet cleaning process.

Step 1.3: Fill the bottom electrode through hole (BEV) 203 with metal copper by electroplating, and use chemical mechanical polishing (CMP, Chemical Mechanical Planarization) to smooth it to form the bottom electrode through hole filling 205, as shown in FIG. 1(c). As shown, before copper electroplating, a Ti/TiN or Ta/TaN diffusion barrier layer 204 and a copper seed layer are usually deposited in advance.

Step 2: making a bottom electrode contact (BEC, Bottom Electrode Contact) 302; wherein, the bottom electrode contact (BEC) 302 can be Ta, TaN, Ti, TiN, W or WN, etc., and a layer of Ta or WN is usually grown thereon. The TaN etch hard mask layer (not shown).

Further, the above-mentioned step 2 can be divided into the following formation steps:

Step 2.1: depositing a bottom electrode contact (BEC) metal layer 301, as shown in FIG. 2(a), wherein the bottom electrode contact (BEC) metal layer 301 is 20 nm to 80 nm, and chemical vapor deposition (CVD, Chemical Vapor Deposition) can be used. ), Physical Vapor Deposition (PVD, Physical Vapor Deposition), Atomic Layer Deposition (ALD, Atomic Layer Deposition) or Ion Beam Deposition (IBD, Ion Beam Deposition).

Step 2.2: Graphically define the bottom electrode contact (BEC) 302 pattern to align it with the bottom electrode via (BEV) 203, and use an etching process to form the bottom electrode contact 302. The etching process can use reactive ion etching (RIE, Reactive Ion Etching) or ion beam etching (IBE, Ion Beam Etching) and other processes, after etching, a cleaning process is used to remove residual polymers and the like.

Among them, IBE mainly uses Ar, Kr or Xe as the ion source; RIE mainly uses Cl ₂ or CF ₄ as the main etching gas.

Step 2.3: The bottom electrode contact (BEC) dielectric 303 is filled and smoothed using a planarization process until the top of the bottom electrode contact (BEC) 302, as shown in Figure 2(b). The bottom electrode contact (BEC) dielectric 303 is made of materials such as SiO ₂ , SiON or low-k.

Step 3: In the storage area, a magnetic tunnel junction structure unit (MTJ) including a bottom seed layer and a top hard mask layer is fabricated.

Further, the above-mentioned step 3 can be divided into the following formation steps:

Step 3.1: On the ground bottom electrode contact (BEC) 302, a seed layer, a magnetic tunnel junction multilayer film 401 and a top hard mask 402 are sequentially formed, as shown in FIG. 3(a).

The total thickness of the magnetic tunnel junction (MTJ) multilayer film is 15nm to 40nm, which can be a Bottom Pinned structure consisting of a reference layer, a barrier layer and a memory layer stacked in sequence, or a memory layer, a barrier layer and a reference layer. Top Pinned structures stacked up in sequence.

Further, the reference layer has magnetic polarization invariance, which differs depending on whether it is an in-plane (iSTT-MRAM) or vertical (pSTT-MRAM) structure. The reference layer of in-plane type (iSTT-MRAM) generally has a (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB structure, and its preferred total thickness is 10-30 nm; the reference layer of vertical type (pSTT-MRAM) generally has TbCoFe Or [Co/Pt]/Co/Ru/[CoPt]/CoFeB superlattice multilayer film structure, usually a seed layer, such as Ta/Pt, is required below, and the total thickness of the reference layer is preferably 8-20 nm.

Further, the barrier layer is a non-magnetic metal oxide, preferably MgO, MgZnO or Al ₂ O ₃ , and its thickness is 0.5 nm˜3 nm.

Further, a structure of double-layer MgO can be adopted.

Further, the memory layer has variable magnetic polarization, depending on whether it is an in-plane (iSTT-MRAM) or vertical (pSTT-MRAM) structure. The memory layer of in-plane iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, and its preferred thickness is 2nm to 6nm, and the memory layer of vertical pSTT-MRAM is generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB/(Ta , W, Mo)/CoFeB, its preferred thickness is 0.8nm～2nm.

The thickness of the top hard mask 402 is 20 nm to 100 nm, and Ta, TaN, W or WN are selected to obtain better engraving profile in halogen plasma.

Step 3.2: Graphically define the magnetic tunnel junction pattern, and etch the top electrode, the magnetic tunnel junction multilayer film 401 and the bottom electrode, as shown in Figure 3(b);

In this process, a method of lithography-etching (LE, lithography-etching) or lithography-etching-lithography-etching twice (LELE, lithography-etching-lithography-etching) is used to complete the definition and top of the magnetic tunnel junction. A reactive ion (RIE) etch of the hard mask 402, along with a RIE process to remove residual polymer, allows the pattern to be transferred to the top of the magnetic tunnel junction.

The magnetic tunnel junction and the bottom electrode are etched by means of reactive ion etching (RIE, Reactive Ion Etching) and/or ion beam etching (IBE, Ion Beam Etching);

Among them, IBE mainly uses Ar, Kr or Xe as the ion source; for RIE, CF ₄ , CF ₃ H, Cl ₂ etc. are mainly used as the main etching gas for the hard mask, and CH ₃ OH, CH ₄ /Ar are mainly used , C ₂ H ₅ OH, CH ₃ OH/Ar or CO/NH ₃ etc. as the main etching gas for the magnetic tunnel junction multilayer film.

Step 3.3: deposit a dielectric cap layer 403 around the magnetic tunnel junction multilayer film 401 and the top hard mask 402 and cover the entire etched area, including the top hard mask layer; as shown in Figure 3(c) Wherein, the dielectric cover layer 403 material is SiC, SiN or SiCN etc., and its formation method can adopt chemical vapor deposition (CVD, Chemical VaporDeposition), atomic layer deposition (ALD, Atomic Layer Deposition) or ion beam deposition (IBD, IonBeam Deposition) ) and so on.

Step 4: Fabricate a top electrode via (TEV, Top Electrode Via) and a metal connection line (M _x+1 ) 604 for connecting logic cells/memory cells. In this step, two single damascene (SD, Single Damascene) or one double damascene (DD, Dual Damascene) processes can be used.

Implementation case 1: two single damascene (SD, Single Damascene) process, the steps are as follows:

Step 4.1.1: On the dielectric cover layer 403, a top electrode through hole dielectric 501 is deposited, and a planarization process is used to flatten the top electrode through hole (TEV) dielectric 501, as shown in FIG. 4(a); the top electrode through hole The (TEV) dielectric 501 is made of materials such as SiO ₂ , SiON or low-k, and has a thickness of 120 nm to 400 nm;

Step 4.1.2: Pattern definition and use an etching process to form a top electrode through hole (TEV) 502, in the logic area, connect it to the bottom electrode through hole filling 205, in the storage area, connect it to the top hard mask 402, Typically, a cleaning process is used to remove the polymer after etching, as shown in Figure 4(b);

Step 4.1.3: Fill metal to form the top electrode through hole filling 504, and use chemical mechanical polishing (CMP) to smooth it, as shown in FIG. 4(c); wherein, before electroplating (ECP, Electro Chemical Plating) copper, A Ti/TiN or Ta/TaN diffusion barrier layer 503 and a copper seed layer are deposited in advance.

Step 4.1.4: Deposit metal interconnect (M _x+1 ) dielectric 602, pattern and etch to form metal interconnect grooves connecting the logic area and storage area, electroplate copper into the interconnect grooves, and use chemical mechanical polishing Polished to form a metal connection line (M _x+1 ) 604 connecting the logic area and the storage area, as shown in FIG. 4(d); wherein, the thickness of the metal connection line (M _x+1 ) dielectric 602 is 50nm～ 300nm, its material is SiO ₂ , SiON or low-k, etc., usually before deposition, an etching barrier layer 601 with a thickness of several tens of nanometers is deposited, and its material is SiN, SiC or SiCN, etc.; before electroplating copper , a Ta/TaN diffusion barrier layer 603 and a copper seed layer are deposited in advance.

Implementation case 2: One-time dual damascene (DD, Dual Damascene) process, as shown in Figure 5; the steps are as follows:

Step 4.2.1: On the dielectric cover layer 403, deposit a top electrode through hole dielectric 501, and use a planarization process to flatten the top electrode through hole (TEV) dielectric 501, and deposit a metal connection (M _x+1 ) dielectric 602; The top electrode through-hole (TEV) dielectric 501 is made of SiO ₂ , SiON, or low-k material, and its thickness is 120 nm to 400 nm; the thickness of the metal connection (M _x+1 ) dielectric 602 is 50 nm to 300 nm, and its material is SiO _2. SiON or low-k, etc., usually before deposition, an etching barrier layer 601 with a thickness of several tens of nanometers is deposited, and its material is SiN, SiC or SiCN, etc.;

Step 4.2.2: Graphically define and use an etching process to form a top electrode through hole (TEV) 502 and a metal wiring groove connecting the logic area and the storage area. In the logic area, the top electrode through hole 502 is connected to the bottom electrode contact 302 , in the storage area, the top electrode via 502 is connected to the top hard mask 402, usually, a cleaning process is used to remove the polymer after etching;

Step 4.2.3: Electroplating filling metal to form top electrode through-hole filling 504 and metal connection (M _x+1 ) 604, and use chemical mechanical polishing to smooth; wherein, before copper electroplating, a layer of Ta/ TaN diffusion barrier layer 503 and copper seed layer.

The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make many modifications and changes according to the concept of the present invention without creative efforts. Therefore, all technical solutions that can be obtained by those skilled in the art through logical analysis, reasoning or limited experiments on the basis of the prior art according to the concept of the present invention shall fall within the protection scope determined by the claims.

Claims (10)

1. A method for manufacturing a magnetic random access memory cell array and a peripheral circuit connecting line is characterized by comprising the following steps:

step 1: providing a CMOS substrate with a polished surface and a metal connecting wire, manufacturing a bottom electrode through hole on the substrate, and then filling metal in the bottom electrode through hole;

step 2: making a bottom electrode contact on the bottom electrode through hole;

and step 3: manufacturing a magnetic tunnel junction structure unit on the bottom electrode contact;

and 4, step 4: manufacturing a top electrode through hole and a metal connecting line for realizing the connection of a logic unit/a storage unit on the magnetic tunnel junction structure unit;

wherein the step 1 comprises the following steps:

step 1.1: depositing a diffusion barrier layer and a bottom electrode through hole dielectric on the CMOS substrate, wherein the diffusion barrier layer can be used as a diffusion protection layer for blocking copper in a metal connecting line from being towards the bottom electrode through hole dielectric, and can also be used as an etching barrier layer for etching the bottom electrode through hole;

step 1.2: simultaneously defining a bottom electrode through hole pattern in a graphical manner in the storage area and the logic area, and etching to form a bottom electrode through hole;

step 1.3: and filling metal copper into the bottom electrode through hole by adopting an electroplating method, and polishing and grinding by adopting chemical machinery to form bottom electrode through hole filling.

2. The method of claim 1, wherein the step 2 comprises the following steps:

step 2.1: depositing a bottom electrode contact metal;

step 2.2: defining a bottom electrode contact pattern in a graphical mode to enable the bottom electrode contact pattern to be aligned with the bottom electrode through hole, etching the bottom electrode contact metal to form a bottom electrode contact, and removing residual impurities after etching;

step 2.3: and filling a bottom electrode contact dielectric in the etched gap, and flattening the top of the bottom electrode contact dielectric until the top of the bottom electrode contact dielectric is flush with the top of the bottom electrode contact.

3. The method as claimed in claim 2, wherein the bottom electrode contact metal is selected from Ta, TaN, Ti, TiN, W or WN.

4. The method as claimed in claim 2, wherein the bottom electrode contact metal is deposited to a thickness of 20nm to 80 nm.

5. The method of claim 2, wherein the bottom electrode contact metal is deposited by one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or ion beam deposition.

6. The method of claim 2, wherein the etching is performed by ion beam etching.

7. The method of claim 2, wherein the bottom electrode contact dielectric is SiO₂SiON or a low dielectric constant dielectric, which means a dielectric constant lower than SiO₂The material of (1).

8. The method as claimed in claim 1, wherein the step 3 of forming the MTJ structure unit comprises forming a MTJ multilayer film and a hard mask.

9. The method as claimed in claim 8, wherein a seed layer or an etch stop layer is deposited under the MTJ multilayer film.

10. The method of claim 1, wherein step 4 comprises performing two single damascene or one dual damascene processes to form the metal interconnects.

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