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CN109545744A - A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line - Google Patents

A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line Download PDF

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Publication number
CN109545744A
CN109545744A CN201710858217.XA CN201710858217A CN109545744A CN 109545744 A CN109545744 A CN 109545744A CN 201710858217 A CN201710858217 A CN 201710858217A CN 109545744 A CN109545744 A CN 109545744A
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bottom electrode
electrode contact
manufacturing
random access
cell array
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CN109545744B (en
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肖荣福
郭民
郭一民
陈峻
张云森
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Shanghai Ciyu Information Technologies Co Ltd
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Shanghai Ciyu Information Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

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  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

本发明提供了一种磁性随机存储器单元阵列及周边电路连线的制造方法，提供在两层金属之间进行磁性随机存储器件及其周围逻辑电路的制作工艺和对准方式。在存储区域，采用在金属连线上依次制作底电极通孔、底电极接触、磁性隧道结结构单元和顶电极通孔，并依次对齐；在逻辑电路区域，则采用顶电极通孔和底电极接触直接相连接的方式实现，顶电极通孔、底电极接触、底电极通孔依次对齐；最后，在顶电极通孔上制作一层金属连线以实现磁性随机存储器逻辑区域和存储区域之间的连接。由于在磁性隧道结单元阵列下面，增加了一层底电极接触，有效的隔断了CMOS后段铜和磁性隧道结阵列底部的直接连接，有利于器件电学性能和良率的提升。

The present invention provides a manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring, and provides a manufacturing process and an alignment method of a magnetic random access memory device and its surrounding logic circuit between two layers of metals. In the storage area, bottom electrode vias, bottom electrode contacts, magnetic tunnel junction structural units and top electrode vias are sequentially fabricated on the metal connection lines, and aligned in sequence; in the logic circuit area, top electrode vias and bottom electrodes are used The contact is directly connected, and the top electrode through hole, the bottom electrode contact, and the bottom electrode through hole are aligned in sequence; finally, a layer of metal wiring is made on the top electrode through hole to realize the magnetic random access memory between the logic area and the storage area. Connection. Because a layer of bottom electrode contact is added under the magnetic tunnel junction unit array, the direct connection between the copper in the rear section of the CMOS and the bottom of the magnetic tunnel junction array is effectively blocked, which is beneficial to the improvement of the electrical performance and yield of the device.

Description

A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line
Technical field
The present invention relates to a kind of magnetic RAM (MRAM) cell array and the manufacturing methods of peripheral circuit line, belong to In magnetic RAM (MRAM, Magnetic Radom Access Memory) manufacturing technology field.
Background technique
In recent years, using the MRAM of magnetic tunnel junction (MTJ, Magnetic Tunnel Junction) by it is believed that being Following solid state non-volatile memory body, it has the characteristics that high-speed read-write, large capacity and low energy consumption.Ferromagnetism MTJ is usual For sandwich structure, wherein having: Magnetic memory layer, it can change the direction of magnetization to record different data；It is located in the middle The tunnel barrier layer of insulation；Magnetic reference layer, positioned at the other side of tunnel barrier layer, its direction of magnetization is constant.
For information can be recorded in this magnetoresistive element, it is proposed that using based on spin momentum transfer or spin-transfer torque The write method of (STT, Spin Transfer Torque) switch technology, such MRAM are known as STT-MRAM.According to magnetic polarization The difference in direction, STT-MRAM is divided into STT-MRAM and vertical STT-MRAM (i.e. pSTT-MRAM), the latter in face again to be had preferably Performance.Method according to this, can be by providing spin polarized current to magnetoresistive element come the intensity of magnetization of inverting magnetization memory layer Direction.In addition, the reduction of the volume with Magnetic memory layer, writes or spin polarized current that conversion operation need to be injected is also smaller. Therefore, this write method can be achieved at the same time device miniaturization and reduce electric current.
Meanwhile can also reduce in view of switching electric current required when reducing MTJ element size, so the pSTT- in terms of scale MRAM can be very good mutually to agree with state-of-the-art technology node.Therefore, it is desirable to be that pSTT-MRAM element is made into minimum ruler It is very little, and there is extraordinary uniformity, and the influence to MTJ magnetism is minimized, used preparation method can also be real Existing high good and the bad rate, pinpoint accuracy, high reliability, low energy consumption, and remain adapted to the temperature coefficient that data well save.Meanwhile Write operation is changed based on resistance state in nonvolatile memory, thus to mtj memory device lifetime caused by needing to control thus Destruction and shortening.However, one small-sized MTJ element of preparation may will increase the fluctuation of MTJ resistance, so that pSTT-MRAM Biggish fluctuation can also be had therewith by writing voltage or electric current, can damage the performance of MRAM in this way.
In present MRAM manufacturing process, in order to realize the requirement of MRAM circuit micromation, usually in surface polishing CMOS through-hole (VIAx(x >=1)) on directly make MTJ cell, it may be assumed that so-called on-axis structure.Using copper wiring In cmos circuit, material used by all through-holes (VIA) and line (M, Metal) is all metallic copper.However, due to MTJ junction The size ratio VIA of structure unitx(x >=1) top opening size is small, when etching magnetic tunnel junction and its hearth electrode, is Make to separate completely between MTJ cell, it is necessary to carry out over etching, in over etching, not by magnetic tunnel junction and its hearth electrode The copper VIA of coveringxThe region of (x >=1) will be partially etched, while can also damage its diffusion barrier layer (Ta/TaN), in this way Copper VIA will be will formx(x >=1) to the dielectric diffusion admittance of low-k outside it, it is electric that Cu atom will be diffused into low-k In medium, this will certainly to the electric property of magnetic RAM, such as: time correlation dielectric breakdown (TDDB, Time Dependent Dielectric Breakdown) and electron mobility (EM, Electron Mobility) etc., it causes to damage.
In addition, during magnetic tunnel junction and its hearth electrode over etching, due to ion bombardment (Ion Bombardment), it will copper atom and its formation compound are splashed to the side wall of magnetic tunnel junction and the low-k being etched The surface of material, to be polluted to entire MRAM device and electric short circuit.
Summary of the invention
The manufacturing method of a kind of magnetic RAM cell array of the invention and peripheral circuit line, is provided at two layers The manufacture craft and alignment of magnetic RAM part and its surrounding logic circuit are carried out between metal.In storage region, Using in metal connecting line (Mx(x >=1)) on, successively make hearth electrode through-hole (BEV, Bottom Electrode Via), bottom electricity Pole contact (BEC, Bottom Electrode Contact), magnetic tunnel junction structure unit (MTJ) and top electrode through-hole (TEV, Top Electrode Via)；BEV, BEC, MTJ and TEV are successively aligned；In logic region, then top electrode through-hole is used (TEV) it contacts the mode that (BEC) is connected directly with hearth electrode and realizes that BEV, BEC and TEV are successively aligned；Finally, in top electrode One layer of metal connecting line (M is made on through-hole (TEV)x+1(x >=1)) to realize magnetic RAM logic region and storage region Between connection.
The present invention includes but is not limited solely to prepare magnetic RAM (MRAM), is also not necessarily limited to any process sequence or stream Journey, as long as the same or similar method that the product or device that are prepared and following selection process sequence or process are prepared, Its specific technical solution is as follows:
The manufacturing method of a kind of magnetic RAM cell array and peripheral circuit line, includes the following steps:
Step 1: the CMOS substrate with metal connecting line of surface polishing being provided, and makes hearth electrode through-hole in substrate, so Metal is filled in hearth electrode through-hole afterwards；
Step 2: hearth electrode contact is made on hearth electrode through-hole；
Step 3: making magnetic tunnel junction structure unit in hearth electrode contact；
Step 4: making top electrode through-hole on magnetic tunnel junction structure unit and be connected with realization logic unit/storage unit The metal connecting line connect.
Further, step 2 includes following subdivided step:
Step 2.1: depositions of bottom electrode contacts metal；Hearth electrode contacts metal and is selected among Ta, TaN, Ti, TiN, W or WN One kind；Hearth electrode contact metal deposit with a thickness of 20nm~80nm；Using chemical vapor deposition, physical vapour deposition (PVD), original Sublayer deposition or ion beam depositing one of mode realize hearth electrode contact metal deposition；
Step 2.2: graphic definition hearth electrode contact patterns are allowed to be aligned with hearth electrode through-hole, etching hearth electrode contact gold Category forms hearth electrode contact, removes remaining impurity after etching；Etching uses reactive ion etching or ion beam etch process It realizes；
Step 2.3: filling hearth electrode contacts dielectric in the gap that etching is formed, and planarization hearth electrode contacts dielectric Top is flushed until the top contacted with hearth electrode；It is SiO that hearth electrode, which contacts dielectric,2, SiON or low-dielectric constant dielectric medium, Low-dielectric constant dielectric medium refers to dielectric constant lower than SiO2Material.
Further, magnetic tunnel junction structure unit includes magnetic tunnel junction multilayer film and hard mask in step 3.It is preferred that Ground deposits one layer of seed layer or etching barrier layer under magnetic tunnel junction multilayer film.
Further, in step 4 using singly inlaying twice or dual-damascene technics realizes the production of metal connecting line.
Beneficial effects of the present invention: due to being contacted in magnetic tunneling junction cell array in the following, increasing one layer of hearth electrode (BEC), effectively separate being directly connected to for CMOS back segment copper and magnetic tunnel junction array bottom, be conducive to device electric property With the promotion of yield.
Detailed description of the invention
Attached drawing is a kind of magnetic random storage cell array according to the preferred embodiment of the invention and peripheral circuit line The schematic diagram of each step of manufacturing method.Wherein:
Fig. 1 (a) to Fig. 1 (c) is the step schematic diagram for making the filling of hearth electrode through-hole；
Fig. 2 (a) to Fig. 2 (b) is the step schematic diagram for making hearth electrode contact；
Fig. 3 (a) to Fig. 3 (c) is the step schematic diagram for making magnetic tunnel junction structure unit；
Fig. 4 (a) to Fig. 4 (d) is the step schematic diagram of the metal connecting line of single mosaic technology production twice；
Fig. 5 is the step schematic diagram of a dual-damascene technics production metal connecting line；
Wherein, two imaginary curves illustrate that left and right two parts are actually separated by very far in Fig. 4 (d) and Fig. 5, are intended merely to conveniently It shows, just handle or so two parts are drawn in together in figure；In other each figures, left and right two parts are actually also to be separated by, in order to make Figure is succinct, and two imaginary curves do not mark.
Description of symbols: the band metal connecting line (M of 100- surface polishingx(x >=1)) CMOS substrate；201- hearth electrode Through-hole (BEV) diffusion barrier layer；202- hearth electrode through-hole (BEV) dielectric；203- hearth electrode through-hole (BEV)；204- hearth electrode Through-hole (BEV) fills diffusion barrier layer；205- hearth electrode through-hole (BEV) filling；301- hearth electrode contacts (BEC) metal layer； 302- hearth electrode contacts (BEC)；303- hearth electrode contacts (BEC) dielectric；401- includes the magnetic tunnel junction (MTJ) of seed layer Multilayer film；402- pushes up hard mask；403- dielectric capping layers；501- top electrode through-hole (TEV) dielectric；502- top electrode through-hole (TEV)；503- top electrode through-hole (TEV) fills diffusion barrier layer；504- top electrode through-hole (TEV) filling；601- metal connecting line (Mx+1(x >=1)) etching barrier layer；602- metal connecting line (Mx+1(x >=1)) dielectric；603- metal connecting line (Mx+1(x >= 1)) diffusion barrier layer；604- metal connecting line (Mx+1(x >=1)).
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.It should be noted that attached drawing of the present invention is all made of simplified form and uses non-essence Quasi- ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The manufacturing method of a kind of magnetic RAM cell array provided by the invention and peripheral circuit line, provides Between double layer of metal, the manufacture craft and alignment of magnetic RAM part and its surrounding logic circuit are carried out；It is storing Region, using in metal connecting line (Mx) on successively make hearth electrode through-hole (BEV), hearth electrode contact (BEC), magnetic tunnel junction The mode of structure unit (MTJ) and top electrode through-hole (TEV) is realized；In logic region, then using top electrode through-hole (TEV) and The mode that hearth electrode contact (BEC) is connected directly is realized, finally, making one layer of metal connecting line on top electrode through-hole (TEV) (Mx+1) to realize the connection between magnetic RAM logic region and storage region.In this way, storage region realize BEV, BEC, MTJ and TEV are successively aligned, and realize that BEV, BEC and TEV are successively aligned in storage region.The present invention includes but is not limited solely to Magnetic RAM (MRAM) is prepared, any process sequence or process are also not necessarily limited to, as long as the product or device that are prepared The same or similar method being prepared with following selection process sequence or process, the specific steps of which are as follows:
Step 1: the band metal connecting line (M of surface polishing is providedx(x >=1)) CMOS substrate 100, and make bottom on it Then electrode through-hole (BEV, Bottom Electrode Via) 203 singly inlays (SD, Single using standard Damascene) technique carries out the filling of metallic copper.
Further, above-mentioned steps 1 can be divided into following forming step:
Step 1.1: deposit diffusion barriers 201 and hearth electrode via dielectric 202 in CMOS substrate 100, such as Fig. 1 (a) shown in, wherein diffusion barrier layer 201 both can be used as barrier metal line (Mx) in copper to hearth electrode via dielectric 202 Diffusion barrier, and can as hearth electrode through-hole 203 etch etching barrier layer, diffusion barrier layer 201 is with a thickness of 10nm ~50nm, forming material can be SiN, SiC or SiCN etc.；Hearth electrode via dielectric 202 with a thickness of 60nm~200nm, Forming material can be SiO2, SiON or low-k etc..
Wherein, low-k (low-k) dielectric refers to that dielectric constant (k) is lower than the material of silica (k=3.9) Material, in the specific implementation, low-k material can be hydrogeneous silicate (Hydrogen Silsequioxane, HSQ, k=2.8~ 3.0), contain Si-CH3The salt containing methane-siliconic acid (Methylsilsesquioxane, MSQ, k=2.5~2.7) of functional group, Hybrid organic siloxane polymer synthesized by comprehensive hydrogeneous silicates (HSQ) and salt containing methane-siliconic acid (MSQ) (Hybrid Organic Siloxane Polymer, HOSP) film (k=2.5), porous SiOCH film (k=2.3~ 2.7), it might even be possible to high using organics such as the porosity silicates (Porous Silicate) of ultralow dielectric (k < 2.0) The porous SiOCH film that molecular compound and dielectric constant (k) are 1.9.
Step 1.2: in storage region and logic region while 203 pattern of graphic definition hearth electrode through-hole (BEV), etching Hearth electrode through-hole (BEV) 203 is formed, as shown in Fig. 1 (b), after the etch, generally uses dry process and/or wet-cleaning Technique removes remaining polymer.
Step 1.3: metallic copper being filled to 203 the inside of hearth electrode through-hole (BEV) using electric plating method, and using chemical machine Tool polishing (CMP, Chemical Mechanical Planarization) polishes, and hearth electrode through-hole filling 205 is formed, such as Fig. 1 (c) shown in, wherein, all can previously deposited one layer of Ti/TiN or Ta/TaN diffusion barrier layer 204 and copper usually before electro-coppering Seed layer.
Step 2: production hearth electrode contacts (BEC, Bottom Electrode Contact) 302；Wherein, hearth electrode contacts (BEC) 302 Ta, TaN, Ti, TiN, W or WN etc. be can be, and usually grows one layer of Ta or TaN on it and etches hard mask layer (not shown).
Further, above-mentioned steps 2 can be divided into following forming step:
Step 2.1: depositions of bottom electrode contacts (BEC) metal layer 301, as shown in Fig. 2 (a), wherein depositions of bottom electrode contact (BEC) metal layer 301 is 20nm~80nm, can use chemical vapor deposition (CVD, Chemical Vapor Deposition), physical vapour deposition (PVD) (PVD, Physical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition) or the modes such as ion beam depositing (IBD, Ion Beam Deposition) realize.
Step 2.2: graphic definition hearth electrode contact (BEC) 302 pattern is allowed to be aligned with hearth electrode through-hole (BEV) 203, And hearth electrode contact 302 is formed using etching technics, etching technics can use reactive ion etching (RIE, Reactive Ion Etching) or the techniques such as ion beam etching (IBE, Ion Beam Etching) are realized, after the etch, using cleaning process Remove remaining polymer etc..
Wherein, IBE mainly uses Ar, Kr or Xe etc. as ion source；RIE mainly uses Cl2Or CF4Deng as main Etching gas.
Step 2.3: filling hearth electrode contacts (BEC) dielectric 303, and is polished using flatening process until hearth electrode connects 302 top (BEC) is touched, as shown in Fig. 2 (b).Wherein, hearth electrode contact (BEC) dielectric 303 is SiO2, SiON or low-k etc. Material.
Step 3: in storage region, making the magnetic tunnel junction structure including the seed layer of bottom and the hard mask layer at top Unit (MTJ).
Further, above-mentioned steps 3 can be divided into following forming step:
Step 3.1: on hearth electrode contact (BEC) 302 polished, sequentially forming seed layer, magnetic tunnel junction multilayer film 401 and top hard mask 402, as shown in Fig. 3 (a).
The overall thickness of magnetic tunnel junction (MTJ) multilayer film is 15nm~40nm, be can be by reference layer, barrier layer and memory The Bottom Pinned structure of layer being superimposed upwards in turn either folding upwards in turn by memory layer, barrier layer and reference layer The Top Pinned structure added.
Further, reference layer has magnetic polarization invariance, is face inner mold (iSTT-MRAM) or vertical (pSTT- according to it MRAM) structure is different.The reference layer of face inner mold (iSTT-MRAM) generally has (IrMn or PtMn)/CoFe/Ru/CoFe/ CoFeB structure, preferred overall thickness are 10~30nm；The reference layer of vertical-type (pSTT-MRAM) generally have TbCoFe or [Co/Pt]/Co/Ru/ [CoPt]/CoFeB superlattice multilayer film structure usually needs one layer of seed layer, such as Ta/Pt below, Its preferred reference layer overall thickness is 8~20nm.
Further, barrier layer is nonmagnetic metal oxide, preferably MgO, MgZnO or Al2O3, with a thickness of 0.5nm~ 3nm。
Further, the structure of bilayer MgO can be used.
Further, memory layer polarizes with variable magnetic, is face inner mold (iSTT-MRAM) or vertical (pSTT- according to it MRAM) structure is different.The memory layer of face inner mold iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, preferred thick Degree be 2nm~6nm, vertical-type pSTT-MRAM memory layer be generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB/ (Ta, W, Mo)/CoFeB, preferred thickness is 0.8nm~2nm.
Push up hard mask 402 with a thickness of 20nm~100nm, select Ta, TaN, W or WN etc. to obtain in halogen plasma-based It is more preferable to carve profile.
Step 3.2: graphic definition magnetic tunnel junction pattern, and to top electrode, magnetic tunnel junction multilayer film 401 and bottom electricity Pole performs etching, as shown in Fig. 3 (b)；
In the process, (LE, lithography-etching) or Twi-lithography two are once etched using a photoetching The method of secondary etching (LELE, lithography-etching-lithography-etching) is completed to magnetic tunnel junction Reactive ion (RIE) etching of definition and top hard mask 402, and remaining polymer is removed using RIE technique simultaneously, so that figure Case is transferred to the top of magnetic tunnel junction.
Using reactive ion etching (RIE, Reactive Ion Etching) and/or ion beam etching (IBE, Ion Beam Etching) method complete to the etching of magnetic tunnel junction and hearth electrode；
Wherein, IBE mainly uses Ar, Kr or Xe etc. as ion source；In terms of RIE, CF is mainly used4、CF3H、Cl2Deng As the main etching gas of hard mask, CH is mainly used3OH、CH4/Ar、C2H5OH、CH3OH/Ar or CO/NH3Deng as magnetic The main etching gas of property tunnel knot multilayer film.
Step 3.3: depositing one layer of dielectric capping layers 403 around magnetic tunnel junction multilayer film 401 and top hard mask 402 And cover the region being entirely etched, the hard mask layer including top；As shown in Fig. 3 (c)；Wherein, 403 material of dielectric capping layers Material is SiC, SiN or SiCN etc., and forming method can use chemical vapor deposition (CVD, Chemical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition) or ion beam depositing (IBD, Ion Beam Deposition) etc. modes realize.
Step 4: production top electrode through-hole (TEV, Top Electrode Via) and realization logic unit/storage unit phase Metal connecting line (the M of connectionx+1)604.In this step, can using singly inlay twice (SD, Single Damascene) or One time dual damascene (DD, Dual Damascene) technique is realized.
Case study on implementation one: (SD, Single Damascene) technique is singly inlayed twice, its step are as follows:
Step 4.1.1: on dielectric capping layers 403, top electrode via dielectric 501 is deposited, and use flat chemical industry Skill polishes top electrode through-hole (TEV) dielectric 501, as shown in Fig. 4 (a)；Top electrode through-hole (TEV) dielectric 501 is SiO2、 The materials such as SiON or low-k, with a thickness of 120nm~400nm；
Step 4.1.2: graphic definition simultaneously forms top electrode through-hole (TEV) 502 using etching technics, in logic region, It is allowed to be connected to hearth electrode through-hole filling 205, in storage region, is allowed to be connected to top hard mask 402, in general, after the etch Polymer is removed using cleaning process, as shown in Fig. 4 (b)；
Step 4.1.3: filling metal forms top electrode through-hole filling 504, and is polished using chemically mechanical polishing (CMP), As shown in Fig. 4 (c)；It wherein, all can be previously deposited usually before plating (ECP, Electro Chemical Plating) copper One layer of Ti/TiN or Ta/TaN diffusion barrier layer 503 and copper seed layer.
Step 4.1.4: deposited metal line (Mx+1) dielectric 602, graphic definition simultaneously etches to form connection logic region With the metal connecting line slot of storage region, electro-coppering is polished to Wire connection slot the inside, and using chemically mechanical polishing, is patrolled with forming connection Collect the metal connecting line (M in region and storage regionx+1) 604, as shown in Fig. 4 (d)；Wherein, metal connecting line (Mx+1) dielectric 602 With a thickness of 50nm~300nm, material SiO2, SiON or low-k etc., usually before the deposition, can all deposit a layer thickness For tens nanometers of etching barrier layer 601, material SiN, SiC or SiCN etc.；It, all can previously deposited one before electro-coppering Layer Ta/TaN diffusion barrier layer 603 and copper seed layer.
Case study on implementation two: disposable dual damascene (DD, Dual Damascene) technique, as shown in Figure 5；Its step is such as Under:
Step 4.2.1: on dielectric capping layers 403, top electrode via dielectric 501 is deposited, and use flat chemical industry Skill polishes top electrode through-hole (TEV) dielectric 501, deposited metal line (Mx+1) dielectric 602；Top electrode through-hole (TEV) electricity is situated between Matter 501 is SiO2, the materials such as SiON or low-k, with a thickness of 120nm~400nm；Metal connecting line (Mx+1) dielectric 602 thickness Degree is 50nm~300nm, material SiO2, SiON or low-k etc., usually before the deposition, can all deposit a layer thickness is Tens nanometers of etching barrier layer 601, material SiN, SiC or SiCN etc.；
Step 4.2.2: graphic definition simultaneously forms top electrode through-hole (TEV) 502 and connection logic area using etching technics The metal connecting line slot in domain and storage region makes top electrode through-hole 502 be connected to hearth electrode contact 302, is storing in logic region Region makes top electrode through-hole 502 be connected to top hard mask 402, in general, removing polymer using cleaning process after the etch；
Step 4.2.3: plating filling metal forms top electrode through-hole and fills 504 and metal connecting line (Mx+1) 604, and use Chemically mechanical polishing polishes；It wherein, all can 503 He of previously deposited one layer of Ta/TaN diffusion barrier layer usually before electro-coppering Copper seed layer.
The preferred embodiment of the present invention has been described in detail above.It should be appreciated that those skilled in the art without It needs creative work according to the present invention can conceive and makes many modifications and variations.Therefore, all technologies in the art Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea Technical solution, all should be within the scope of protection determined by the claims.

Claims (10)

1.一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，包括如下步骤：1. a manufacturing method of magnetic random access memory cell array and peripheral circuit connection, is characterized in that, comprises the steps: 步骤1：提供表面抛光的带金属连线的CMOS基底，并在所述基底上制作底电极通孔，然后在所述底电极通孔中填充金属；Step 1: providing a surface-polished CMOS substrate with metal connections, and making bottom electrode through holes on the substrate, and then filling the bottom electrode through holes with metal; 步骤2：在所述底电极通孔上制作底电极接触；Step 2: making a bottom electrode contact on the bottom electrode through hole; 步骤3：在所述底电极接触上制作磁性隧道结结构单元；Step 3: fabricating a magnetic tunnel junction structure unit on the bottom electrode contact; 步骤4：在所述磁性隧道结结构单元上制作顶电极通孔和实现逻辑单元/存储单元相连接的金属连线。Step 4: forming top electrode through holes and metal wirings for connecting logic cells/memory cells on the magnetic tunnel junction structure unit. 2.根据权利要求1所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，所述步骤2包括如下细分步骤：2. The manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring according to claim 1, wherein the step 2 comprises the following subdivision steps: 步骤2.1：沉积底电极接触金属；Step 2.1: deposit bottom electrode contact metal; 步骤2.2：图形化定义底电极接触图案使之与所述底电极通孔对齐，刻蚀所述底电极接触金属形成所述底电极接触，刻蚀之后除去残留的杂质；Step 2.2: Graphically define the bottom electrode contact pattern to align it with the bottom electrode through hole, etch the bottom electrode contact metal to form the bottom electrode contact, and remove residual impurities after etching; 步骤2.3：在刻蚀形成的空隙中填充底电极接触电介质，平坦化所述底电极接触电介质顶部直到与所述底电极接触的顶部齐平。Step 2.3: Fill the bottom electrode contact dielectric in the void formed by the etching, and planarize the top of the bottom electrode contact dielectric until the top of the bottom electrode contact is flush with the bottom electrode contact. 3.根据权利要求2所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，所述底电极接触金属选自Ta、TaN、Ti、TiN、W或WN之中的一种。3 . The method for manufacturing a magnetic random access memory cell array and peripheral circuit wiring according to claim 2 , wherein the bottom electrode contact metal is selected from among Ta, TaN, Ti, TiN, W or WN. 4 . a kind of. 4.根据权利要求2所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，所述底电极接触金属沉积的厚度为20nm～80nm。4 . The method for manufacturing a magnetic random access memory cell array and peripheral circuit wiring according to claim 2 , wherein the thickness of the bottom electrode contact metal deposition is 20 nm˜80 nm. 5 . 5.根据权利要求2所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，采用化学气相沉积、物理气相沉积、原子层沉积、或离子束沉积之中的一种方式实现所述底电极接触金属的沉积。5. The method for manufacturing a magnetic random access memory cell array and peripheral circuit wiring according to claim 2, wherein one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or ion beam deposition is used. In this way, the deposition of the bottom electrode contact metal is achieved. 6.根据权利要求2所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，所述刻蚀采用反应离子刻蚀或离子束刻蚀工艺实现。6 . The method for manufacturing a magnetic random access memory cell array and peripheral circuit connections according to claim 2 , wherein the etching is realized by reactive ion etching or ion beam etching. 7 . 7.根据权利要求2所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，所述底电极接触电介质为SiO2、SiON或低介电常数电介质，所述低介电常数电介质是指介电常数低于SiO2的材料。7 . The method for manufacturing a magnetic random access memory cell array and peripheral circuit wiring according to claim 2 , wherein the bottom electrode contact dielectric is SiO 2 , SiON or a low dielectric constant dielectric, and the low dielectric constant A dielectric constant dielectric refers to a material with a lower dielectric constant than SiO2 . 8.根据权利要求1所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，步骤3中所述磁性隧道结结构单元包括磁性隧道结多层膜和硬掩模。8 . The method for manufacturing a magnetic random access memory cell array and peripheral circuit connections according to claim 1 , wherein the magnetic tunnel junction structural unit in step 3 comprises a magnetic tunnel junction multilayer film and a hard mask. 9 . . 9.根据权利要求8所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，在所述磁性隧道结多层膜下沉积一层种子层或刻蚀阻挡层。9 . The method for manufacturing a magnetic random access memory cell array and peripheral circuit connections according to claim 8 , wherein a seed layer or an etching barrier layer is deposited under the magnetic tunnel junction multilayer film. 10 . 10.根据权利要求1所述的一种磁性随机存储器单元阵列及周边电路连线的制造方法，其特征在于，步骤4中采用两次单镶嵌或者一次双镶嵌工艺实现所述金属连线的制作。10 . The method for manufacturing a magnetic random access memory cell array and a peripheral circuit connection according to claim 1 , wherein in step 4, two single damascene or one dual damascene process is used to realize the fabrication of the metal connection. 11 . .
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