CN109713120A - A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line - Google Patents
A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line Download PDFInfo
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- CN109713120A CN109713120A CN201711011769.3A CN201711011769A CN109713120A CN 109713120 A CN109713120 A CN 109713120A CN 201711011769 A CN201711011769 A CN 201711011769A CN 109713120 A CN109713120 A CN 109713120A
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Abstract
The present invention provides a kind of magnetic RAM cell array and the manufacturing methods of peripheral circuit line, include the following steps: that (1) provides the CMOS substrate with metal connecting line of surface polishing, and hearth electrode through-hole is made in substrate, then metallic copper is filled in hearth electrode through-hole；(2) depositions of bottom electrode contact and magnetic tunnel junction multilayer film on hearth electrode through-hole, and magnetic tunnel junction memory unit array is made in storage region；The contact of logic region hearth electrode and false magnetic tunnel junction (dummy-MTJ) unit are made on logic region hearth electrode through-hole；(3) logic region top electrode through-hole is made, and makes the size of logic region top electrode through-hole greater than the size of false magnetic tunneling junction cell；(4) storage region top electrode through-hole is made, top electrode via metal is then filled in logic region top electrode through-hole and storage region top electrode through-hole；(5) metal connecting line of production connection logic region and storage region.
Description
Technical field
The present invention relates to a kind of magnetic RAM (MRAM) cell array and the manufacturing methods of peripheral circuit line, belong to
In magnetic RAM (MRAM, Magnetic Radom Access Memory) manufacturing technology field.
Background technique
In recent years, using the MRAM of magnetic tunnel junction (MTJ) by it is believed that be following solid state non-volatile memory body,
It has the characteristics that high-speed read-write, large capacity and low energy consumption.Ferromagnetism MTJ is usually sandwich structure, wherein the note that is magnetic
Recall layer, it can change the direction of magnetization to record different data；It is located in the middle the tunnel barrier layer of insulation；Magnetic reference
Layer, positioned at the other side of tunnel barrier layer, its direction of magnetization is constant.
For information can be recorded in this magnetoresistive element, it is proposed that using based on spin momentum transfer or spin-transfer torque
The write method of (STT, Spin Transfer Torque) switch technology, such MRAM are known as STT-MRAM.According to magnetic polarization
The difference in direction, STT-MRAM is divided into STT-MRAM and vertical STT-MRAM (i.e. pSTT-MRAM), the latter in face again to be had preferably
Performance.Method according to this, can be by providing spin polarized current to magnetoresistive element come the intensity of magnetization of inverting magnetization memory layer
Direction.In addition, the reduction of the volume with Magnetic memory layer, writes or spin polarized current that conversion operation need to be injected is also smaller.
Therefore, this write method can be achieved at the same time device miniaturization and reduce electric current.
Meanwhile can also reduce in view of switching electric current required when reducing MTJ element size, so the pSTT- in terms of scale
MRAM can be very good mutually to agree with state-of-the-art technology node.Therefore, it is desirable to be that pSTT-MRAM element is made into minimum ruler
It is very little, and there is extraordinary uniformity, and the influence to MTJ magnetism is minimized, used preparation method can also be real
Existing high good and the bad rate, pinpoint accuracy, high reliability, low energy consumption, and remain adapted to the temperature coefficient that data well save.Meanwhile
Write operation is changed based on resistance state in nonvolatile memory, thus to mtj memory device lifetime caused by needing to control thus
Destruction and shortening.However, one small-sized MTJ element of preparation may will increase the fluctuation of MTJ resistance, so that pSTT-MRAM
Biggish fluctuation can also be had therewith by writing voltage or electric current, can damage the performance of MRAM in this way.
In present MRAM manufacturing process, when making MTJ, it will usually CMOS through-hole (Via) and MTJ be selected to remember
The mode that unit is misaligned is recalled, to prevent the roughness due to through-hole surfaces from influencing the magnetoelectricity performance of MTJ, it may be assumed that so-called
Off-axis structure, the mode of this CMOS/MTJ circuit integration are highly detrimental to the micromation requirement of MRAM circuit, also unfavorable
In production microminiature magnetic storage requirement.
Recently, in order to realize the requirement of MRAM circuit micromation, usually in the CMOS through-hole (VIA of surface polishingx(x >=
1) MTJ cell is directly made on), it may be assumed that so-called on-axis structure.In the cmos circuit using copper wiring, all through-holes
(VIA) and material used by line (M, Metal) is all metallic copper.However, due to the size ratio VIA of mtj structure unitx
(x >=1) top opening size is small, when etching magnetic tunnel junction and its hearth electrode, in order to make between MTJ cell completely
Partition, it is necessary to over etching is carried out, in over etching, not by magnetic tunnel junction and its copper VIA of hearth electrode coveringx(x >=1)
Region will be partially etched, while can also damage its diffusion barrier layer (Ta/TaN), copper VIA will be will form in this wayx(x >=
1) the dielectric diffusion admittance of low-k outside it is arrived, Cu atom will be diffused into low-k dielectric, this will certainly be to magnetic
The electric property of property random access memory, such as: time correlation dielectric breakdown (TDDB, Time Dependent Dielectric
Breakdown) and electron mobility (EM, Electron Mobility) etc., cause to damage.
In addition, during magnetic tunnel junction and its hearth electrode over etching, due to ion bombardment (Ion
Bombardment), it will copper atom and its formation compound are splashed to the side wall of magnetic tunnel junction and the low-k being etched
The surface of material, to be polluted to entire MRAM device.
Summary of the invention
The manufacturing method of of the invention a kind of magnetic tunneling junction cell array and its peripheral circuit line, is provided in two layers of gold medal
Between category, the manufacture craft and alignment of magnetic RAM part and its surrounding logic circuit are carried out.In storage region,
Using in metal connecting line (Mx, Metalx(x >=1)) on, successively make hearth electrode through-hole (BEV, Bottom Electrode
Via), hearth electrode contact (BEC, Bottom Electrode Contact), magnetic tunnel junction structure unit (MTJ) and top electrode
Through-hole (TEV, Top Electrode Via)；BEV, BEC, MTJ and TEV are successively aligned；In logic region, then using top
The mode that electrode through-hole (TEV) and hearth electrode contact (BEC) are connected directly realizes that BEV, BEC and TEV are successively aligned；Finally,
One layer of metal connecting line (M is made on top electrode through-hole (TEV)x+1, x >=1) with realize magnetic RAM logic region and
Connection between storage region.
The present invention includes but is not limited solely to prepare magnetic RAM (MRAM), is also not necessarily limited to any process sequence or stream
Journey, as long as the same or similar method that the product or device that are prepared and following selection process sequence or process are prepared.
Specific technical solution is as follows:
The manufacturing method of a kind of magnetic RAM cell array and peripheral circuit line, includes the following steps:
Step 1: the CMOS substrate with metal connecting line of surface polishing being provided, and makes hearth electrode through-hole in substrate, so
Metallic copper is filled in hearth electrode through-hole afterwards；
Step 2: depositions of bottom electrode contact and magnetic tunnel junction multilayer film on hearth electrode through-hole, and made in storage region
Magnetic tunnel junction memory unit array；The contact of logic region hearth electrode and false magnetic tunnel are made on logic region hearth electrode through-hole
Road knot (dummy-MTJ) unit；
Step 3: production logic region top electrode through-hole, and the size of logic region top electrode through-hole is made to be greater than false magnetic tunnel
The size of road statement of account member；
Step 4: production storage region top electrode through-hole, then in logic region top electrode through-hole and storage region top electrode
Top electrode via metal is filled in through-hole；
Step 5: the metal connecting line of production connection logic region and storage region.
Further, step 2 includes following subdivided step:
Step 2.1: it is hard that hearth electrode contact metal layer, magnetic tunnel junction multilayer film and top are sequentially depositing on hearth electrode through-hole
Mask layer；
Step 2.2: graphic definition magnetic tunnel junction pattern, and to top hard mask layer, magnetic tunnel junction multilayer film and bottom
Electrode contact metal performs etching；
Step 2.3: hearth electrode after etching contacts to be filled out around metal, magnetic tunnel junction multilayer film and top hard mask layer
Fill magnetic tunnel junction dielectric capping layers.
Further, in step 2.3, the material of magnetic tunnel junction dielectric capping layers is selected from SiC, SiN or SiCN,
One be formed by among chemical vapor deposition, atomic layer deposition or ion beam depositing of magnetic tunnel junction dielectric capping layers
Kind mode is realized.
Further, in step 3, logic region top is completed using reactive ion etching and/or the method for ion beam etching
The etching of electrode through-hole, and the false magnetic tunneling junction cell of consumption as much as possible, so that the size of logic region top electrode through-hole
Greater than the size of false magnetic tunneling junction cell.Further, in step 3, ion beam etching mainly uses Ar, Kr or Xe to make
For ion source；Reactive ion etching mainly uses CF4、SF6、CH3OH、CH4/Ar、C2H5OH、CH3OH/Ar or CO/NH3As
Main etching gas.
Further, in step 4, before filling logic region top electrode through-hole and storage region top electrode through-hole, in advance
Deposit one layer of Ti/TiN or Ta/TaN diffusion barrier layer and copper seed layer.
Further, specific step is as follows for step 5: deposited metal line dielectric, and graphic definition simultaneously etches to be formed
The metal connecting line slot of logic region and storage region is connected, is filled in metallic copper to metal connecting line slot, metal connecting line is formed.More into
One step, metal connecting line is dielectric with a thickness of 50nm~300nm, and the dielectric material of metal connecting line is selected from SiO2, SiON or
Low-dielectric constant dielectric medium, low-dielectric constant dielectric medium refer to that dielectric constant is lower than the material of silica.Further, exist
Before deposited metal line dielectric, the metal connecting line etching barrier layer that a layer thickness is tens nanometers is first deposited, metal connecting line is carved
The material for losing barrier layer is selected from SiN, SiC or SiCN.
Above-mentioned manufacturing method can also have a reduced form, a kind of magnetic RAM cell array and peripheral circuit line
Manufacturing method, include the following steps:
Step 1: the CMOS substrate with metal connecting line of surface polishing being provided, and makes hearth electrode through-hole in substrate, so
Metallic copper is filled in hearth electrode through-hole afterwards；
Step 2: the contact of storage region hearth electrode and magnetic tunnel junction memory are made on the hearth electrode through-hole of storage region
Cell array；The contact of logic region hearth electrode and false magnetic tunnel junction (dummy- are made on the hearth electrode through-hole of logic region
MTJ) unit；
Step 3: production logic region top electrode through-hole and storage region top electrode through-hole, in logic region top electrode through-hole
It top electrode via metal and is polished with being filled in storage region top electrode through-hole；
Step 4: the metal connecting line of production connection logic region and storage region.
Beneficial effects of the present invention: due in magnetic tunnel junction in the following, increasing one layer of hearth electrode contact (BEC), effectively
Separated CMOS back segment copper and magnetic tunnel junction array, be conducive to the promotion of device electric property and yield.It is mono- in production MTJ
When member and hearth electrode contact, a lithography and etching technique is used, reduces the complexity and production of technique in this way
Cost.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily to the present invention by more complete understanding
And its adjoint advantage and feature is more easily to understand, in which:
Fig. 1 (a) to Fig. 1 (c) is the step schematic diagram for making the filling of hearth electrode through-hole；
Fig. 2 (a) to Fig. 2 (c) is the step schematic diagram for making hearth electrode contact and magnetic tunneling junction cell；
Fig. 3 (a) to Fig. 3 (b) is the step schematic diagram for making logic region top electrode through-hole；
Fig. 4 (a) to Fig. 4 (b) is the step schematic diagram for making top electrode through-hole；
Fig. 5 is the step schematic diagram for making metal connecting line；
Description of symbols: the band metal connecting line (M of 100- surface polishingxThe CMOS substrate of (x >=1), 201- hearth electrode
Through-hole (BEV) diffusion barrier layer, 202- hearth electrode through-hole (BEV) dielectric, 2031- hearth electrode through-hole (BEV) (storage region),
2032- hearth electrode through-hole (BEV) (logic region), 2041- hearth electrode through-hole (BEV) fill diffusion barrier layer (storage region),
2042- hearth electrode through-hole (BEV) fills diffusion barrier layer (logic region), and 2051- hearth electrode through-hole (BEV) fills (memory block
Domain), 2052- hearth electrode through-hole (BEV) fills (logic region), and 301- hearth electrode contacts (BEC) metal layer, and 302- includes seed
Magnetic tunnel junction (MTJ) multilayer film of layer, 303- push up hard mask layer, 304- magnetic tunnel junction dielectric capping layers, the top 401- electricity
Pole through-hole (TEV) dielectric, 4021- top electrode through-hole (TEV) (logic region), (memory block 4022- top electrode through-hole (TEV)
Domain), 4031- top electrode through-hole (TEV) fills diffusion barrier layer (logic region), 4032- top electrode through-hole (TEV) filling diffusion
Barrier layer (storage region), 4041- top electrode through-hole (TEV) fill (logic region), 4042- top electrode through-hole (TEV) filling
(storage region), 501- metal connecting line (Mx+1(x >=1) etching barrier layer, 502- metal connecting line (Mx+1(x >=1).
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.It should be noted that attached drawing of the present invention is all made of simplified form and uses non-essence
Quasi- ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
A kind of method of of the invention magnetic tunneling junction cell array and peripheral circuit connection, provide double layer of metal it
Between, carry out the manufacture craft and alignment of magnetic RAM part and its surrounding logic circuit.In storage region, use
In metal connecting line (Mx, Metalx(x >=1)) on, successively make hearth electrode through-hole (BEV, Bottom Electrode Via), bottom
Electrode contacts (BEC, Bottom Electrode Contact), magnetic tunnel junction structure unit (MTJ) and top electrode through-hole
(TEV, Top Electrode Via)；BEV, BEC, MTJ and TEV are successively aligned；In logic region, then top electrode is used
The mode that through-hole (TEV) and hearth electrode contact (BEC) are connected directly realizes that BEV, BEC and TEV are successively aligned；Finally, pushing up
One layer of metal connecting line (M is made on electrode through-hole (TEV)x+1, x >=1) to realize magnetic RAM logic region and storage
Connection between region.Due in magnetic tunnel junction in the following, increase one layer of hearth electrode contact (BEC), it is effective to separate
CMOS back segment copper and magnetic tunnel junction array directly then, it is therefore prevented that copper is directly exposed in etching gas in etching process
The risk being etched is conducive to the promotion of device electric property and yield.Due to being contacted in production MTJ cell and hearth electrode
When, a lithography and etching technique is used, reduces the complexity and cost of manufacture of technique in this way.The present invention include but
It is not limited solely to prepare magnetic RAM (MRAM), is also not necessarily limited to any process sequence or process, as long as the production being prepared
The same or similar method that product or device and following selection process sequence or process are prepared, the specific steps of which are as follows:
Step 1: the band metal connecting line (M of surface polishing is providedxThe CMOS substrate 100 of (x >=1), and bottom is made on it
Electrode through-hole (BEV, Bottom Electrode Via) 203, then, singly inlays (SD, Single using standard
Damascene) technique carries out the filling of metallic copper.
Further, step 1 can be divided into following forming step:
Step 1.1: depositions of bottom electrode through-hole diffusion barrier layer 201 and hearth electrode via dielectric 202, such as Fig. 1 (a) institute
Show, wherein hearth electrode through-hole diffusion barrier layer 201 both can be used as barrier metal line (Mx) in copper to hearth electrode through-hole electricity be situated between
The diffusion barrier of matter 202, and the etching barrier layer that can be etched as BEV, with a thickness of 10nm~50nm, forming material can
Think SiN, SiC or SiCN etc.；Hearth electrode via dielectric 202 with a thickness of 60nm~150nm, forming material can be
SiO2, SiON or low-k etc..
Wherein, low-k (low-k) dielectric refers to that dielectric constant (k) is lower than the material of silica (k=3.9)
Material, in the specific implementation, low-k material can be hydrogeneous silicate (Hydrogen Silsequioxane, HSQ, k=2.8~
3.0), containing Si-CH3The salt containing methane-siliconic acid (Methylsilsesquioxane, MSQ, k=2.5~2.7) of functional group,
Hybrid organic siloxane polymer (Hybrid synthesized by the comprehensive hydrogeneous silicates HSQ and MSQ of salt containing methane-siliconic acid
Organic Siloxane Polymer, HOSP) film (k=2.5), porous SiOCH film (k=2.3~2.7), or even can
Using organics high-molecular compounds such as the porosity silicates (Porous Silicate) of ultralow dielectric (k < 2.0)
And the porous SiOCH film that dielectric constant (k) is 1.9.
Step 1.2: in storage region and logic region while graphic definition hearth electrode through-hole (BEV) 2031, hearth electrode
2032 pattern of through-hole, etching form hearth electrode through-hole (BEV) 2031 and hearth electrode through-hole 2032, as shown in Fig. 1 (b), are etching
Later, remaining polymer is generally removed using dry process and/or wet clean process.
Step 1.3: 2032 the inside of filling metallic copper to hearth electrode through-hole (BEV) 2031 and hearth electrode through-hole, and useization
It learns mechanical polishing (CMP, Chemical Mechanical Planarization) to polish, forms hearth electrode through-hole filling 2051
2052 are filled with hearth electrode through-hole, as shown in Fig. 1 (c).It wherein, all can previously deposited one layer of Ti/ usually before electro-coppering
TiN or Ta/TaN diffusion barrier layer 2041, diffusion barrier layer 2042 and copper seed layer.
Step 2: on hearth electrode through-hole, depositions of bottom electrode contact and magnetic tunnel junction multilayer film, then in storage region,
It makes magnetic tunnel junction (MTJ) cell array and hearth electrode below contacts (BEC), in logic region, make false magnetic tunnel
Road knot (Dummy-MTJ) and following hearth electrode contact (BEC).
Further, step 2 can be divided into following forming step:
Step 2.1: on the hearth electrode through-hole (BEV) polished, being sequentially depositing hearth electrode contact (BEC) metal layer 301, magnetic
Property tunnel knot multilayer film 302 and top hard mask layer 303, as shown in Fig. 2 (a).
Wherein, depositions of bottom electrode contact (BEC) metal layer 301 is Ta, TaN, Ti, TiN, W or WN etc., and thickness range is
20nm~80nm can use chemical vapor deposition (CVD, Chemical Vapor Deposition), physical vapour deposition (PVD)
(PVD, Physical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition) or ion
The modes such as beam deposition (IBD, Ion Beam Deposition) are realized.
The overall thickness of magnetic tunnel junction (MTJ) multilayer film 302 be 15nm~40nm, can be by reference layer, barrier layer and
Remember layer the Bottom Pinned structure being superimposed upwards in turn, or from memory layer, barrier layer and reference layer successively to
The Top Pinned structure of upper superposition.
Further, reference layer has magnetic polarization invariance, is face inner mold (iSTT-MRAM) or vertical (pSTT- according to it
MRAM) structure is different.The reference layer of face inner mold (iSTT-MRAM) generally has (IrMn or PtMn)/CoFe/Ru/CoFe/
CoFeB structure, preferred overall thickness are 10~30nm；The reference layer of vertical-type (pSTT-MRAM) generally have TbCoFe or
[Co/Pt]/Co/Ru/ [CoPt]/CoFeBm superlattice multilayer film structure usually needs one layer of seed layer, such as Ta/Pt below,
Its preferred reference layer overall thickness is 8~20nm.
Further, barrier layer is nonmagnetic metal oxide, preferably MgO or Al2O3, with a thickness of 0.5nm~3nm.
Further, the structure of bilayer MgO can be used.
Further, memory layer polarizes with variable magnetic, is face inner mold (iSTT-MRAM) or vertical (pSTT- according to it
MRAM) institute is different again for structure.The memory layer of face inner mold iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, preferred thick
Degree be 2nm~6nm, vertical-type pSTT-MRAM memory layer be generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB (Ta, W,
Mo)/CoFeB, preferred thickness are 0.8nm~2nm.
Push up hard mask layer 303 with a thickness of 20nm~100nm, select Ta, TaN, W or WN etc. to obtain in halogen plasma-based
It obtains and more preferably carves profile.
Step 2.2: graphic definition magnetic tunnel junction pattern, and to top hard mask layer 303, magnetic tunnel junction multilayer film
302 and hearth electrode contact metal layer 301 perform etching, as shown in Fig. 2 (b).
In the process, (LE, lithography-etching) or Twi-lithography two are once etched using a photoetching
The method of secondary etching (LELE, lithography-etching-lithography-etching) is completed to magnetic tunnel junction
Reactive ion (RIE) etching of definition and top hard mask layer 303, and remaining polymer is removed using RIE technique simultaneously, so that
Pattern is transferred to the top of magnetic tunnel junction.
Using reactive ion etching (RIE, Reactive Ion Etching) and/or ion beam etching (IBE, Ion
Beam Etching) method complete the etching that (BEC) is contacted to magnetic tunnel junction (MTJ) and hearth electrode；Finally, in memory block
Domain forms magnetic tunnel junction (MTJ) array element and hearth electrode below contacts (BEC), in logic region, is formed false
Magnetic tunneling junction cell (Dummy-MTJ) unit and hearth electrode below contact (BEC).
Strict control lithography and etching technological parameter so that false magnetic tunneling junction cell (Dummy-MTJ) unit and its
The size of following hearth electrode contact (BEC) is more much smaller than subsequent top electrode through-hole 4021.
Wherein, IBE mainly uses Ar, Kr or Xe etc. as ion source；RIE mainly uses CH3OH、CH4/Ar、
C2H5OH、CH3OH/Ar or CO/NH3Deng as main etching gas.
Step 2.3: filling magnetic tunnel junction dielectric capping layers 304 contact (BEC) metal layer 301, magnetism in hearth electrode
Around tunnel knot multilayer film 302 and top hard mask layer 303, as shown in Fig. 2 (c)；Wherein, magnetic tunnel junction dielectric capping layers
304 materials are SiC, SiN or SiCN etc., and forming method can use chemical vapor deposition (CVD, Chemical Vapor
Deposition), atomic layer deposition (ALD, Atomic Layer Deposition) or ion beam depositing (IBD, Ion
Beam Deposition) etc. modes realize.
The subsequent step of above-mentioned steps is divided into two kinds of situations:
Case study on implementation one:
Step 3: in logic region, making shown in top electrode through-hole (TEV) 4021, Fig. 3 (a) and Fig. 3 (b).In this process
In, it is completed using the method that a photoetching once etches (LE, lithography-etching) to top electrode through-hole (TEV)
4021 definition and top electrode through-hole (TEV) dielectric reactive ion (RIE) etching.
Wherein, top electrode through-hole (TEV) dielectric 401 is SiO2, the materials such as SiON or low-k, with a thickness of 120nm~
400nm。
Using reactive ion etching (RIE, Reactive Ion Etching) and/or ion beam etching (IBE, Ion
Beam Etching) method complete complete logic region top electrode through-hole (TEV) etching；And the false magnetic of consumption as much as possible
Property tunneling junction cell (Dummy-MTJ).
Wherein, IBE mainly uses Ar, Kr or Xe etc. as ion source；RIE mainly uses CF4、SF6、CH3OH、CH4/
Ar、C2H5OH、CH3OH/Ar or CO/NH3Deng as main etching gas.
Strict control lithography and etching technological parameter, so as to be compared to logic region top electrode through-hole (TEV) size
The size of false magnetic tunnel junction (Dummy-MTJ) is much bigger.
Step 4: production storage region top electrode through-hole (TEV, Top Electrode Via) 4022, filling metal are formed
Top electrode through-hole (TEV) filling 4041 and top electrode through-hole filling 4042, and chemically mechanical polishing (CMP) technique is used to grind to it
It is flat, as shown in Fig. 4 (a) and Fig. 4 (b).
Wherein, metal filling usually is carried out in plating (ECP, Electro Chemical Plating) copper mode, at this
It before all can previously deposited one layer of Ti/TiN or Ta/TaN diffusion barrier layer 4031, diffusion barrier layer 4032 and copper seed layer.
Step 5: deposited metal line (Mx+1) dielectric, graphic definition, which simultaneously etches to be formed, connects logic region and storage
The metal connecting line slot in region, electro-coppering is polished to Wire connection slot the inside, and using chemically mechanical polishing, to form connection logic region
With the metal connecting line (M of storage regionx+1) 502, as shown in Figure 5；Wherein, metal connecting line (Mx+1) it is dielectric with a thickness of 50nm~
300nm, material SiO2, SiON or low-k etc., usually before the deposition, can all deposit a layer thickness is tens nanometers
Etching barrier layer 501, material SiN, SiC or SiCN etc.；Before electro-coppering, all can previously deposited one layer of Ti/TiN or
Ta/TaN diffusion barrier layer and copper seed layer.
Case study on implementation two:
Step 3: in logic region and storage region, while making top electrode through-hole (TEV) 4021 and top electrode through-hole
4022.In the process, it is completed using the method that a photoetching once etches (LE, lithography-etching) to top electricity
The definition of pole through-hole (TEV) 4021 and top electrode through-hole (TEV) dielectric reactive ion (RIE) etching.
Wherein, top electrode through-hole (TEV) dielectric 401 is SiO2, the materials such as SiON or low-k, with a thickness of 120nm~
400nm。
Using reactive ion etching (RIE, Reactive Ion Etching) and/or ion beam etching (IBE, Ion
Beam Etching) method complete complete logic region top electrode through-hole (TEV) etching；And the false magnetic of consumption as much as possible
Property tunneling junction cell (Dummy-MTJ).
Wherein, IBE mainly uses Ar, Kr or Xe etc. as ion source；RIE mainly uses CF4、SF6、CH3OH、CH4/
Ar、C2H5OH、CH3OH/Ar or CO/NH3Deng as main etching gas.
Strict control lithography and etching technological parameter, so as to be compared to logic region top electrode through-hole (TEV) size
The size of false magnetic tunnel junction (Dummy-MTJ) is much bigger.
Finally, filling top electrode through-hole (TEV) metal, forms top electrode through-hole filling 4041 and top electrode through-hole (TEV)
Filling 4042, and chemically mechanical polishing (CMP) technique is used to polish to it.
Wherein, metal filling usually is carried out in plating (ECP, Electro Chemical Plating) copper mode, at this
It before all can previously deposited one layer of Ti/TiN or Ta/TaN diffusion barrier layer 4031, diffusion barrier layer 4032 and copper seed layer.
Step 4: with step 5 in case study on implementation one.
The preferred embodiment of the present invention has been described in detail above.It should be appreciated that those skilled in the art without
It needs creative work according to the present invention can conceive and makes many modifications and variations.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical solution, all should be within the scope of protection determined by the claims.
Claims (10)
1. the manufacturing method of a kind of magnetic RAM cell array and peripheral circuit line, which is characterized in that including as follows
Step:
Step 1: the CMOS substrate with metal connecting line of surface polishing being provided, and makes hearth electrode through-hole on the substrate, so
Metallic copper is filled in the hearth electrode through-hole afterwards；
Step 2: depositions of bottom electrode contact and magnetic tunnel junction multilayer film on the hearth electrode through-hole, and made in storage region
Magnetic tunnel junction memory unit array；The contact of logic region hearth electrode and vacation are made on the hearth electrode through-hole of logic region
Magnetic tunneling junction cell；
Step 3: production logic region top electrode through-hole, and the size of the logic region top electrode through-hole is made to be greater than the false magnetic
The size of property tunneling junction cell；
Step 4: production storage region top electrode through-hole, then in the logic region top electrode through-hole and the storage region top
Top electrode via metal is filled in electrode through-hole；
Step 5: production connects the metal connecting line of the logic region and the storage region.
2. the manufacturing method of a kind of magnetic RAM cell array according to claim 1 and peripheral circuit line,
It is characterized in that, step 2 includes following subdivided step:
Step 2.1: on the hearth electrode through-hole, being sequentially depositing hearth electrode contact metal layer, magnetic tunnel junction multilayer film and top
Hard mask layer；
Step 2.2: graphic definition magnetic tunnel junction pattern, and to the top hard mask layer, the magnetic tunnel junction multilayer film
It is performed etching with the hearth electrode contact metal layer；
Step 2.3: the hearth electrode contact metal layer, the magnetic tunnel junction multilayer film and the top hard mask after etching
Magnetic tunnel junction dielectric capping layers are filled around layer.
3. the manufacturing method of a kind of magnetic RAM cell array according to claim 2 and peripheral circuit line,
It is characterized in that, the material of the magnetic tunnel junction dielectric capping layers is selected from SiC, SiN or SiCN, described in step 2.3
One be formed by among chemical vapor deposition, atomic layer deposition or ion beam depositing of magnetic tunnel junction dielectric capping layers
Kind mode is realized.
4. the manufacturing method of a kind of magnetic RAM cell array according to claim 1 and peripheral circuit line,
It is characterized in that, completing the logic region top electricity using reactive ion etching and/or the method for ion beam etching in step 3
The etching of pole through-hole, and the consumption as much as possible false magnetic tunneling junction cell, so that the logic region top electrode through-hole
Size be greater than the size of the false magnetic tunneling junction cell.
5. the manufacturing method of a kind of magnetic RAM cell array according to claim 4 and peripheral circuit line,
It is characterized in that, the ion beam etching mainly uses Ar, Kr or Xe as ion source in step 3；The reactive ion is carved
Erosion mainly uses CF4、SF6、CH3OH、CH4/Ar、C2H5OH、CH3OH/Ar or CO/NH3As main etching gas.
6. the manufacturing method of a kind of magnetic RAM cell array according to claim 1 and peripheral circuit line,
It is characterized in that, in step 4, before filling the logic region top electrode through-hole and the storage region top electrode through-hole, thing
First deposit one layer of Ti/TiN or Ta/TaN diffusion barrier layer and copper seed layer.
7. the manufacturing method of a kind of magnetic RAM cell array according to claim 1 and peripheral circuit line,
It is characterized in that, specific step is as follows for step 5: deposited metal line dielectric, graphic definition simultaneously etch to form connection institute
The metal connecting line slot of logic region and the storage region is stated, fills in metallic copper to the metal connecting line slot, forms the gold
Belong to line.
8. the manufacturing method of a kind of magnetic RAM cell array according to claim 7 and peripheral circuit line,
It is characterized in that, the metal connecting line is dielectric with a thickness of 50nm~300nm, the dielectric material of metal connecting line is selected from
SiO2, SiON or low-dielectric constant dielectric medium, the low-dielectric constant dielectric medium refers to that dielectric constant is lower than the material of silica
Material.
9. the manufacturing method of a kind of magnetic RAM cell array according to claim 8 and peripheral circuit line,
It is characterized in that, first depositing the metal connecting line that a layer thickness is tens nanometers before depositing the metal connecting line dielectric and etching
The material on barrier layer, the metal connecting line etching barrier layer is selected from SiN, SiC or SiCN.
10. the manufacturing method of a kind of magnetic RAM cell array and peripheral circuit line, which is characterized in that including as follows
Step:
Step 1: the CMOS substrate with metal connecting line of surface polishing being provided, and makes hearth electrode through-hole on the substrate, so
Metallic copper is filled in the hearth electrode through-hole afterwards；
Step 2: the contact of storage region hearth electrode and magnetic tunnel junction memory are made on the hearth electrode through-hole of storage region
Cell array；The contact of logic region hearth electrode and the false magnetic tunnel statement of account are made on the hearth electrode through-hole of logic region
Member；
Step 3: production logic region top electrode through-hole and storage region top electrode through-hole, in the logic region top electrode through-hole
It top electrode via metal and is polished with being filled in the storage region top electrode through-hole；
Step 4: production connects the metal connecting line of the logic region and the storage region.
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| CN111987216A (en) * | 2019-05-23 | 2020-11-24 | 上海磁宇信息科技有限公司 | Preparation method of pseudo-magnetic tunnel junction unit for replacing through hole |
| CN112635658A (en) * | 2019-09-24 | 2021-04-09 | 浙江驰拓科技有限公司 | Method for preparing magnetic random access memory |
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