CN109462402B - Mixed type assembly line ADC structure - Google Patents

Abstract

The invention discloses a mixed type assembly line ADC structure, which comprises 1 traditional 4-bit MDAC, 1 zero-crossing comparator, 5 mixed time domain quantizers and 1 digital calibration module; the MDAC output end is connected with the zero crossing comparator, the output end of the zero crossing comparator is sequentially connected with 5 mixed time domain quantizers, the output ends of the 5 mixed time domain quantizers are respectively connected with the input end of the digital calibration module, and the output end of the digital calibration module is in two-way connection with the MDAC input end. The 1 st-stage MDAC (multiplying digital-to-analog converter) inputs a voltage signal, performs voltage-time conversion through a zero-crossing comparator, outputs a time pulse signal, and adopts a time domain quantizer at the later stage. Designing a mixed time domain quantizer that uses 1 capacitor DAC instead of the DAC in the time domain can reduce clock jitter errors.

Description

Hybrid Pipeline ADC Architecture

technical field

The invention belongs to the technical field of pipeline analog-to-digital converters, in particular to a novel hybrid pipeline ADC structure.

Background technique

The rapid development of modern communication systems puts forward higher requirements for the performance of ADCs. In wireless communications, ADCs with high linearity and high dynamic range are often required to provide a sufficiently high spurious-free dynamic range to signal-to-noise harmonic distortion ratio. The improvement of the speed of the communication system makes the amount of data that needs to be processed in a unit time continue to increase, which puts forward higher requirements for the speed of the ADC. The rapid development of personal communication systems and various portable consumer electronic products requires further reduction in the power consumption of ADCs.

The pipeline ADC adopts the residual amplifier with high gain and the multi-sub-stage series working mode, so it has the characteristics of high precision and high speed, and has become a research focus in the field of converters. The residual amplifier in the traditional pipeline sub-stage has the characteristics of high gain and high linearity, which can enable the ADC to obtain high precision and small nonlinear error. However, the traditional headroom amplifier composed of op amps and switched capacitors is difficult to design with complicated circuits, and will generate large power consumption. Especially at low supply voltages, it is more difficult for a headroom amplifier to achieve a compromise between low power consumption and high accuracy.

The time domain-based analog-to-digital conversion technology was proposed in 2008, and this technology was used in pipeline ADCs in 2014. This technology combines the time domain-based converter with the traditional pipeline structure, absorbing the advantages of both structures , to achieve high-precision and high-speed analog-to-digital conversion with low power consumption. However, as a new ADC structure, the pipeline ADC based on time domain needs to solve two key problems: 1. When realizing high-precision analog-to-digital conversion, there are many sub-stages in the pipeline, which is not easy to further reduce power consumption. 2. The first stage MDAC (multiplier digital-to-analog converter) of pipeline ADC based on time domain usually adopts closed-loop high-performance amplifier to realize inter-stage residual amplifier, which can obtain more accurate gain and smaller nonlinear error, but , which will result in higher power consumption. However, if a headroom amplifier with a relatively simple open-loop gain and low open-loop gain is used, the finite open-loop gain and nonlinear error will cause the headroom curve to deviate from the ideal characteristics, thereby affecting the conversion accuracy.

SUMMARY OF THE INVENTION

The purpose of the present invention is to propose a novel hybrid pipeline ADC structure, which will have both the characteristics and advantages of the time domain and voltage domain converters, and meet the parameter requirements of high precision and low power consumption.

In order to achieve the above object, the concrete technical scheme adopted by the present invention is:

A hybrid pipeline ADC structure includes a traditional 4-bit MDAC (multiplier digital-to-analog converter), a zero-crossing comparator, five hybrid time-domain quantizers, and a digital calibration module. Other auxiliary modules include voltage and current reference, clock module, digital output module, etc.

The MDAC output terminal is connected with the zero-crossing comparator, and the zero-crossing comparator output terminal is sequentially connected with 5 mixed time domain quantizers, and the output ends of the 5 mixed time domain quantizers are respectively connected with the input end of the digital calibration module, The output end of the digital calibration module is bidirectionally connected with the MDAC input end.

The structure of the present invention adopts the MDAC multiplier digital-to-analog converter in the voltage domain in the first stage of the pipeline, and adopts the time domain quantizer in the latter stage. The first-stage MDAC (multiplier digital-to-analog converter) inputs a voltage signal, and the output of the first-stage MDAC performs voltage-time conversion through a zero-crossing comparator, so that the output of the first-stage MDAC is a time pulse signal, and the latter stage Time domain quantizers work in the time domain. Among them, the voltage-time conversion process requires 3 clock phases, and the sampling and feedback capacitors are discharged at the same time. During voltage-time conversion, the _{output TO} is linear and not affected by amplifier parameters. The latter stage adopts 5 mixed time domain quantizers, which can reduce the clock jitter error, and after the zero-crossing moment, the amplified time margin output is transmitted to the next stage. The time-domain quantizer of the latter stage uses a capacitor DAC to replace the time-domain DAC, which can reduce the clock jitter error.

The invention has a reasonable design and has good practical application and promotion value.

Description of drawings

Figure 1 shows the structure of the novel hybrid pipeline ADC.

Figure 2 shows the voltage-time conversion process in the novel hybrid pipeline ADC structure.

Figure 3 shows the hybrid time-domain quantizer in the novel hybrid pipeline ADC structure.

FIG. 4 shows the working process of the hybrid time domain quantizer in the novel hybrid pipeline ADC structure.

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

A hybrid pipeline ADC structure, as shown in Figure 1, includes a traditional 4-bit MDAC, a zero-crossing comparator, five hybrid time-domain quantizers, and a digital calibration module. Other auxiliary modules include voltage and current reference, clock module, digital output module, etc. Among them, the MDAC output terminal is connected to the zero-crossing comparator, the output terminal of the zero-crossing comparator is connected to five mixed time domain quantizers in turn, and the output terminals of the five mixed time domain quantizers are respectively connected to the input terminal of the digital calibration module. The module output is bidirectionally connected to the MDAC input.

The traditional pipeline has many sub-stages, and it is not easy to further reduce power consumption. This structure replaces the traditional pipeline sub-stage with a converter sub-stage based on the time domain in the subsequent stages of the pipeline except the first stage, which can reduce the power consumption of the ADC without reducing the accuracy. The structure of the time quantizer is designed, and the mixed time domain quantizer is used to reduce the clock jitter error.

The signal input to the mixed pipeline ADC first passes through the sample-and-hold circuit, and then is input to the first-stage MDAC (multiplier digital-to-analog converter), and the input MDAC is a voltage signal. The MDAC can amplify the input voltage signal, and then perform voltage-time conversion through the zero-crossing comparator, so that the signal input to the subsequent stage is a time domain signal. The signal input to the time quantizer 1 is the amplified time domain signal, which is an analog signal. The time quantizer 1 can perform AD conversion on the input analog signal, and can generate a 2.5-bit digital output. The analog signal that has not been converted is the same as the input signal. The analog signal of the time quantizer 1 is subjected to residual amplification by the comparator, and is used as the input of the subsequent stage. The signal input to the time quantizer 2 is the time domain analog signal after margin amplification, and the same working process as the time quantizer 1 is performed again. The digital output of each time quantizer passes the digital signal output by the digital calibration module, and then obtains the complete digital signal after the conversion of the total input analog signal.

FIG. 2 is a voltage-time conversion process in the structure. This conversion process requires 3 clock phases, and the sampling and feedback capacitors are discharged at the same time. Since there is no charge on the two capacitors, the output in the time domain at zero crossings is always linear, provided that the linearity of the current source satisfies the requirements, regardless of the non-ideal characteristics of the amplifier. The output in the time domain is independent of the amplifier parameters at the zero-crossing moment of the discharge time phase, so in this voltage-time conversion process, the _{output TO} is linear and not affected by the amplifier parameters. During zero-crossing detection, the output signal in the time domain has nothing to do with the amplifier's error, so a low-gain nonlinear amplifier can be used in the voltage-time conversion process.

Figure 3 is a hybrid time-domain quantizer. The charge subtraction of the quantizer is done with a capacitor DAC. The linearity of the DAC in this structure is only determined by the matching of the capacitors, which is relatively easy to implement. Errors in the time domain, such as time jitter and delay unit mismatch, can only affect the linearity of the sub-TDC, but have no effect on the margin between stages.

Figure 4 shows the working process of the hybrid time-domain quantizer. First, all capacitors are reset to the positive reference voltage. During the charging phase, the capacitor is charged by the current input based on time. At this moment, the sub-TDC quantizes the temporal input and produces the corresponding one-hot encoded output. At the next clock phase, the charge (representing headroom) stored on the capacitor is discharged through the current source I and headroom amplification. After the zero-crossing moment, the amplified time margin input is transmitted to the next stage.

It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, several improvements and applications can also be made, and these improvements and applications are also regarded as the protection scope of the present invention.

Claims (2)

1. a hybrid pipeline ADC structure is characterized in that: comprise 1 traditional 4-bit MDAC, 1 zero-crossing comparator, 5 mixed time domain quantizers, 1 digital calibration module; The MDAC output terminal is connected with the zero-crossing comparator, and the zero-crossing comparator output terminal is sequentially connected with 5 mixed time domain quantizers, and the output ends of the 5 mixed time domain quantizers are respectively connected with the input end of the digital calibration module, The digital calibration module output end is bidirectionally connected with the MDAC input end; The voltage-time conversion process in the zero-crossing comparator adopts three clock phases, and the sampling and feedback capacitors are discharged at the same time; The signal input to the mixed pipeline ADC first passes through the sample-and-hold circuit, and then is input to the first-stage MDAC, and the voltage signal input to the MDAC is a voltage signal; the MDAC amplifies the input voltage signal, and then performs voltage-time conversion through the zero-crossing comparator, so that after the input The signal of the first stage is a time domain signal; the signal input to the time quantizer 1 is an amplified time domain signal, which is an analog signal. The time quantizer 1 performs AD conversion on the input analog signal to generate a 2.5-bit digital output, which is not The converted analog signal and the analog signal of the input time quantizer 1 are subjected to margin amplification through the comparator as the input of the subsequent stage; the signal input to the time quantizer 2 is the time domain analog signal after the margin amplification, and the time domain analog signal is again performed with the time domain. The same working process of the quantizer 1; the digital output of each time quantizer passes the digital signal output by the digital calibration module, and then obtains the complete digital signal after the conversion of the total input analog signal. 2 . The hybrid pipeline ADC structure according to claim 1 , wherein the time domain quantizer adopts one capacitive DAC to replace the time domain DAC. 3 .

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