CN113114248A

CN113114248A - Self-calibration pipeline ADC

Info

Publication number: CN113114248A
Application number: CN202110509817.1A
Authority: CN
Inventors: 陈功; 郭函; 曾庆林; 谢鹏; 李蠡; 董倩宇
Original assignee: Chengdu University of Information Technology
Current assignee: Chengdu University of Information Technology
Priority date: 2021-05-11
Filing date: 2021-05-11
Publication date: 2021-07-13

Abstract

The invention discloses a self-calibration assembly line ADC, which performs coarse quantization on an input signal through a first sub ADC, wherein a quantization result is coded into a control signal by a first switch logic control module to control a first MDAC, so that the differential amplification of a subtraction result of the input signal and the coarse quantization result is realized, and the differential amplification is transmitted to a post-stage circuit; the second sub-ADC, the second switch logic control module, the second MDAC, the third sub-ADC, the third switch logic control module and the third MDAC follow the process, and quantization and difference amplification are performed step by step in a pipeline mode until the fourth sub-ADC performs end quantization; meanwhile, the first self-calibration module, the second self-calibration module and the third self-calibration module calibrate the quantization codes of the sub-ADCs according to the quantization coding result of the low-speed ADC, so that high-speed and high-precision pipelined analog-to-digital conversion is realized.

Description

Self-calibration pipeline ADC

Technical Field

The invention relates to the field of integrated circuits, in particular to a self-calibration assembly line.

Background

The technology of integrated circuits has been rapidly developed in the past 40 years, and as the minimum channel length of transistors is reduced, digital integrated circuits have higher and higher integration level, lower and lower power consumption and higher speed. The development of Digital circuits has replaced more analog signal processing, but signals in nature are mostly continuous, so analog-to-Digital converters (ADCs) play an important role in today's electronic systems.

There are many ADC architectures available today, including FLASH architectures, SAR architectures, oversampling architectures, and pipeline architectures. Compared with ADCs with other structures, the pipelined ADC can meet the requirements of high speed and high precision at the same time, and is an important research direction in the field of integrated circuits at present.

However, the existing pipeline ADC technology has the non-negligible defect. Due to the nonlinear characteristic of an analog electronic circuit and mismatch errors of an integrated circuit process, such as capacitance mismatch errors, when the pipeline ADC is designed at high speed and high resolution, the real effective digit of the pipeline ADC has a large difference from the resolution digit during design, and the quantization precision of the pipeline ADC is seriously influenced.

Disclosure of Invention

Aiming at the defects in the prior art, the self-calibration pipeline ADC provided by the invention solves the problems that when the high-speed high-resolution design is carried out on the existing pipeline ADC, the real effective digit has a large difference with the resolution digit of a designer, and the quantization precision is not high.

In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a self-calibrating pipelined ADC comprising: the buffer A1, the buffer A2, the buffer A3, the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC, the third gain digital-to-analog converter MDAC, the first sub-ADC, the second sub-ADC, the third sub-ADC, the fourth sub-ADC, the first switch logic control module, the second switch logic control module, the third switch logic control module, the first self-calibration module, the second self-calibration module, the third self-calibration module, the low-speed ADC, the inverter U1, the inverter U2, the inverter U3, the inverter U4, the inverter U5, the inverter U6, the inverter U7, the inverter U8, the inverter U9 and the inverter U10;

the positive phase input end of the buffer A1 is respectively connected with the Vin end of the first sub-ADC and the Vin end of the low-speed ADC and serves as the input end Vin of the self-calibration pipeline ADC; the inverting input end of the buffer A1 is respectively connected with the output end of the buffer A1 and the vin end of the first gain digital-to-analog converter MDAC; the s 1-s 15 ends of the first gain digital-to-analog converter MDAC are connected with the output end of the first switch logic control module, and the CLKS ends of the first gain digital-to-analog converter MDAC are respectively connected with the clka end of the second gain digital-to-analog converter MDAC and the CLKS end of the third gain digital-to-analog converter MDAC and serve as a sampling phase clock signal end CLKS of the self-calibration pipeline ADC;

the CLKA end of the first gain digital-to-analog converter MDAC is respectively connected with the clks end of the second gain digital-to-analog converter MDAC and the CLKA end of the third gain digital-to-analog converter MDAC and is used as an amplification phase clock signal end CLKA of the self-calibration pipeline ADC; the Vrefp end of the first gain digital-to-analog converter MDAC is respectively connected with the Vrefp end of the second gain digital-to-analog converter MDAC, the Vrefp end of the third gain digital-to-analog converter MDAC, the Vrefp end of the first sub-ADC, the Vrefp end of the second sub-ADC, the Vrefp end of the third sub-ADC, the Vrefp end of the fourth sub-ADC and the Vrefp end of the low-speed ADC, and is used as a reference voltage end Vrefp of the self-calibration pipeline ADC; the vcm end of the first gain digital-to-analog converter MDAC is respectively connected with the vcm end of the second gain digital-to-analog converter MDAC and the vcm end of the third gain digital-to-analog converter MDAC and serves as a common mode level end vcm of the self-calibration assembly line ADC; the vrefn end of the first gain digital-to-analog converter MDAC is respectively connected with the vrefn end of the second gain digital-to-analog converter MDAC, the vrefn end of the third gain digital-to-analog converter MDAC, the vrefn end of the first sub-ADC, the vrefn end of the second sub-ADC, the vrefn end of the third sub-ADC, the vrefn end of the fourth sub-ADC and the vrefn end of the low-speed ADC, and is used as a reference voltage end vrefn of the self-calibration pipeline ADC; an aout end of the first gain digital-to-analog converter MDAC is respectively connected with a non-inverting input end of the buffer A2 and a vin end of the second sub-ADC;

the vin end of the second gain digital-to-analog converter MDAC is connected to the inverting input end of the buffer a2 and the output end of the buffer a2, respectively, s 1-s 15 ends of the second gain digital-to-analog converter MDAC are connected to the output end of the second switch logic control module, and aout ends of the second gain digital-to-analog converter MDAC are connected to the non-inverting input end of the buffer A3 and the vin end of the third sub-ADC, respectively;

the dout [4:0] end of the first sub-ADC is respectively connected with the input end of the first switch logic control module and the d1[4:0] end of the first self-calibration module, and the CLK ends of the first sub-ADC are respectively connected with the input end of the inverter U1, the input end of the inverter U4, the input end of the inverter U5, the input end of the inverter U7, the input end of the inverter U8 and the CLK end of the third sub-ADC and serve as a comparator clock signal end CLK1 of the self-calibration pipeline ADC; the clk end of the second sub-ADC is connected with the output end of the inverter U4, and the dout [4:0] end of the second sub-ADC is respectively connected with the input end of the second switch logic control module and the d2[4:0] end of the first self-calibration module; the dout [15:0] end of the low-speed ADC is respectively connected with the d3[15:0] end of the first self-calibration module, the d3[15:0] end of the second self-calibration module and the d3[15:0] end of the third self-calibration module, and the CLK end of the low-speed ADC is used as a low-speed ADC clock signal end CLK2 of the self-calibration pipeline ADC;

the clk end of the first self-calibration module is connected with the output end of the inverter U3, and the dout [8:0] end of the first self-calibration module is connected with the d1[8:0] end of the second self-calibration module; the input end of the inverter U2 is connected with the output end of the inverter U1, and the output end of the inverter U2 is connected with the input end of the inverter U3; the d2[4:0] end of the second self-calibration module is respectively connected with the dout [4:0] end of the third sub-ADC and the input end of the third switch logic control module, the clk end of the second self-calibration module is connected with the output end of the inverter U6, and the dout [12:0] end of the second self-calibration module is connected with the d1[12:0] end of the third self-calibration module; the input end of the inverter U6 is connected with the output end of the inverter U5; the output end of the buffer A3 is respectively connected with the inverting input end of the buffer A3 and the vin end of the third gain digital-to-analog converter MDAC; ends s 1-s 15 of the third gain digital-to-analog converter MDAC are connected with the output end of the third switch logic control module, and an aout end of the third gain digital-to-analog converter MDAC is connected with a vin end of the fourth sub-ADC; the clk end of the fourth sub-ADC is connected with the output end of the inverter U7, and the dout [3:0] end of the fourth sub-ADC is connected with the d2[3:0] end of the third self-calibration module; the dout [4:0] end of the third sub-ADC is connected with the input end of the third switch logic control module; the input end of the inverter U9 is connected with the output end of the inverter U8, and the output end of the inverter U9 is connected with the input end of the inverter U10; the clk end of the third self-calibration module is connected with the output end of the inverter U10, and the Dout [15:0] end of the third self-calibration module is used as the output end Dout3[15:0] of the self-calibration pipeline ADC.

The beneficial effects of the above further scheme are: the sampling phase clock signal end CLKS and the amplification phase clock signal end CLKA of the invention need to be accessed into a two-phase non-overlapping clock commonly used in the research direction of a digital-analog hybrid integrated circuit in the field of integrated circuits, and in the embodiment, the clock frequency is 20 MHz; the clock signal end CLK1 of the comparator is also 20MHz, and the signal rising edge of the comparator appears in the middle of the high level of the CLKS clock signal, so that the built-in comparators of each sub ADC can perform quantization coding on the voltage when the output of each gain digital-to-analog converter MDAC is stable; the frequency of a clock signal end CLK2 of the low-speed ADC is 500kHz, the low-speed ADC is a 16-bit resolution ADC, a high-precision sigma-delta modulation ADC scheme is adopted, the scheme can realize the low-power-consumption low-speed ADC with extremely high precision, and the ADC is used as a reference ADC to calibrate the self-assembly line ADC, and the self-calibration of the self-calibration assembly line ADC can be performed in parallel with normal quantization coding, and the calibration work is performed only when the ADC is powered on, namely the low-speed ADC is not in a normally open state; after self-calibration, the pipelined ADC can maintain the high-speed and high-precision characteristics of 20 MHz.

Further, the first sub-ADC, the second sub-ADC and the third sub-ADC have the same structure, and each of the first sub-ADC, the second sub-ADC and the third sub-ADC includes: 31 resistors from the resistor R101 to the resistor R131, 30 dynamic comparators from the dynamic comparator A101 to the dynamic comparator A130 and a first thermometer code decoder;

the inverting input end of the dynamic comparator A101 is respectively connected with one end of the resistor R101 and one end of the resistor R102; the other end of the resistor R101 is used as a vrefn end of the first sub-ADC, the second sub-ADC or the third sub-ADC; the inverting input end of the dynamic comparator Ai is respectively connected with the other end of the resistor Ri and one end of the resistor Ri +1, wherein i is an integer, and the integer is taken as [102,130 ]; the other end of the resistor R131 is used as a vrefp end of the first sub ADC, the second sub ADC or the third sub ADC;

the positive phase input end of the dynamic comparator a101 is respectively connected to the positive phase input end of the dynamic comparator a102 to the positive phase input end of the dynamic comparator a130, and serves as a vin end of the first sub-ADC, the second sub-ADC or the third sub-ADC; the clk end of the dynamic comparator a101 is respectively connected with the clk end of the dynamic comparator a102 to the clk end of the dynamic comparator a130, and is used as the clk end of the first sub-ADC, the second sub-ADC or the third sub-ADC; the output end of each dynamic comparator is correspondingly connected with 30 input ends of the first thermometer code decoder one by one; the output end of the first thermometer code decoder is used as the dout [4:0] end of the first sub-ADC, the second sub-ADC or the third sub-ADC.

Further, the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC, and the third gain digital-to-analog converter MDAC have the same structure, and each of the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC, and the third gain digital-to-analog converter MDAC includes: 15 selectors from the selector U201 to the selector U2015, 34 CMOS complementary switches from the CMOS complementary switch K201 to the CMOS complementary switch K234, 16 capacitors from the capacitor C201 to the capacitor C216 and an operational amplifier A201;

the 0 th selection end of the selector U201 is respectively connected with the 0 th selection ends of the remaining 14 selectors, and serves as a vrefp end of the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC or the third gain digital-to-analog converter MDAC; the 1 st selection end of the selector U201 is respectively connected with the 1 st selection ends of the remaining 14 selectors and serves as a vcm end of the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC or the third gain digital-to-analog converter MDAC; the 2 nd selection end of the selector U201 is respectively connected with the 2 nd selection ends of the remaining 14 selectors, and serves as a vrefn end of the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC or the third gain digital-to-analog converter MDAC;

the first connecting end of the CMOS complementary switch K201 is connected with the output end of the selector U201, and the second connecting end of the CMOS complementary switch K201 is connected with the second connecting end of the CMOS complementary switch K202 and one end of the capacitor C201 respectively; a first connecting end of the CMOS complementary switch Kn is connected with an output end of the selector Un-j, a second connecting end of the CMOS complementary switch Kn is respectively connected with a second connecting end of a CMOS complementary switch Kn +1 and one end of a capacitor Cn-j, wherein n is an odd number, the odd number in [203,229] is taken in sequence, j is an integer, and when n is 203, j is 1; when n is 205, j is 2; when n is 207, j is 3; when n is 209, j is 4; when n is 211, j is 5; when n is 213, j is 6; when n is 215, j is 7; when n is 217, j is 8; when n is 219, j is 9; when n is 221, j is 10; when n is 223, j is 11; when n is 225, j is 12; when n is 227, j is 13; when n is 229, j is 14;

the first connection end of the CMOS complementary switch K202 is connected with the first connection end of the CMOS complementary switch K204, the first connection end of the CMOS complementary switch K206, the first connection end of the CMOS complementary switch K208, the first connection end of the CMOS complementary switch K210, the first connection end of the CMOS complementary switch K212, the first connection end of the CMOS complementary switch K214, the first connection end of the CMOS complementary switch K216, the first connection end of the CMOS complementary switch K218, the first connection end of the CMOS complementary switch K220, the first connection end of the CMOS complementary switch K222, the first connection end of the CMOS complementary switch K224, the first connection end of the CMOS complementary switch K226, the first connection end of the CMOS complementary switch K228, the first connection end of the CMOS complementary switch K230, and the first connection end of the CMOS complementary switch K231, and serves as the vin end of the first gain digital-to-analog converter MDAC, the second gain digital converter MDAC, or the third gain digital converter MDAC;

the clks end of the CMOS complementary switch K202 is connected to the clks end of the CMOS complementary switch K204, the clks end of the CMOS complementary switch K206, the clks end of the CMOS complementary switch K208, the clks end of the CMOS complementary switch K210, the clks end of the CMOS complementary switch K212, the clks end of the CMOS complementary switch K214, the clks end of the CMOS complementary switch K216, the clks end of the CMOS complementary switch K218, the clks end of the CMOS complementary switch K220, the clks end of the CMOS complementary switch K222, the clks end of the CMOS complementary switch K224, the clks end of the CMOS complementary switch K226, the clks end of the CMOS complementary switch K228, the clks end of the CMOS complementary switch K230, the clks end of the CMOS complementary switch K231, and the clks end of the CMOS complementary switch K232, respectively, and is used as the clks end of the first digital-to-analog converter MDAC, the second digital-to-analog gain converter or the third digital to-analog converter MDAC;

the clka end of the CMOS complementary switch K201 is connected with the clka end of the CMOS complementary switch K203, the clka end of the CMOS complementary switch K205, the clka end of the CMOS complementary switch K207, the clka end of the CMOS complementary switch K209, the clka end of the CMOS complementary switch K211, the clka end of the CMOS complementary switch K213, the clka end of the CMOS complementary switch K215, the clka end of the CMOS complementary switch K217, the clka end of the CMOS complementary switch K219, the clka end of the CMOS complementary switch K221, the clka end of the CMOS complementary switch K223, the clka end of the CMOS complementary switch K225, the clka end of the CMOS complementary switch K227, the clka end of the CMOS complementary switch K229, the clka end of the CMOS complementary switch K233 and the clka end of the CMOS complementary switch K234, and is used as the clka first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter or the clka end of the third gain converter MDAC, respectively;

the other end of the capacitor C201 is connected with the other end of the capacitor C202, the other end of the capacitor C203, the other end of the capacitor C204, the other end of the capacitor C205, the other end of the capacitor C206, the other end of the capacitor C207, the other end of the capacitor C208, the other end of the capacitor C209, the other end of the capacitor C210, the other end of the capacitor C211, the other end of the capacitor C212, the other end of the capacitor C213, the other end of the capacitor C214, the other end of the capacitor C215, one end of the capacitor C216, the second connection end of the CMOS complementary switch K231, the non-inverting input end of the operational amplifier a201 and the first connection end of the CMOS complementary;

the inverting input end of the operational amplifier a201 is connected to the second connection end of the CMOS complementary switch K232 and the first connection end of the CMOS complementary switch K234, respectively, and serves as a vcm end of the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC, or the third gain digital-to-analog converter MDAC; the positive output end of the operational amplifier A201 is connected with the second connecting end of the CMOS complementary switch K234, and the negative output end of the operational amplifier A is connected with the first connecting end of the CMOS complementary switch K233 and is used as the aout end of the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC or the third gain digital-to-analog converter MDAC; the second connecting end of the CMOS complementary switch K233 is connected with the other end of the capacitor C216;

the control terminal s1 of the selector U201, the control terminal s2 of the selector U202, the control terminal s3 of the selector U203, the control terminal s4 of the selector U204, the control terminal s5 of the selector U205, the control terminal s6 of the selector U206, the control terminal s7 of the selector U207, the control terminal s8 of the selector U208, the control terminal s9 of the selector U209, the control terminal s10 of the selector U210, the control terminal s11 of the selector U211, the control terminal s12 of the selector U212, the control terminal s13 of the selector U213, the control terminal s14 of the selector U214, and the control terminal s15 of the selector U215 serve as the terminals s1 to s15 of the first, second, or third digital-to-analog converters MDAC.

Further, the fourth sub ADC includes: 16 resistors from the resistor R301 to the resistor R316, 15 dynamic comparators from the dynamic comparator A301 to the dynamic comparator A15 and a second thermometer code decoder;

the inverting input end of the dynamic comparator A301 is respectively connected with one end of the resistor R301 and one end of the resistor R302; the other end of the resistor R101 is used as a vrefn end of the fourth sub-ADC; the inverting input end of the dynamic comparator Am is respectively connected with the other end of the resistor Rm and one end of the resistor Rm +1, wherein m is an integer and is taken throughout [302,315 ]; the other end of the resistor R316 is used as a vrefp end of the fourth sub-ADC; the positive phase input end of the dynamic comparator a301 is respectively connected to the positive phase input end of the dynamic comparator a302 to the positive phase input end of the dynamic comparator a315, and serves as a vin end of the fourth sub-ADC; the clk end of the dynamic comparator a301 is connected to the clk end of the dynamic comparator a302 to the clk end of the dynamic comparator a315, and serves as the clk end of the fourth sub-ADC; the output end of each dynamic comparator is correspondingly connected with the 15 input ends of the second thermometer code decoder one by one; and the output end of the second thermometer code decoder is used as the dout [4:0] end of the fourth sub-ADC.

Further, the structure of the buffer a1, the buffer a2 and the buffer A3 are the same, and each of them includes: a PMOS tube M401, a PMOS tube M402, an NMOS tube M403, an NMOS tube M404, an NMOS tube M405, an NMOS tube M406, a PMOS tube M409, a PMOS tube M410, a PMOS tube M411, a PMOS tube M412, a PMOS tube M413, an NMOS tube M414, an NMOS tube M415, a PMOS tube M416, an NMOS tube M417, a PMOS tube M418, a PMOS tube M419, an NMOS tube M420, an NMOS tube M421, an NMOS tube M422, a PMOS tube M423, an NMOS tube M424, a grounding resistor R401, a resistor R402, a current source M407, a current source M408, a capacitor C401, a capacitor C402, a resistor R403 and a resistor R404;

the source electrode of the PMOS transistor M401 is respectively connected with the source electrode of the PMOS transistor M411, the source electrode of the PMOS transistor M412, the source electrode of the PMOS transistor M423, one end of the resistor R402 and one end of the current source M408, and the drain electrode of the PMOS transistor M401 is respectively connected with the gate electrode of the PMOS transistor M401 and the source electrode of the PMOS transistor M402; the drain electrode of the PMOS tube M402 is respectively connected with the grid electrode of the PMOS tube M402, the grounding resistor R401, the grid electrode of the PMOS tube M418 and the grid electrode of the PMOS tube M413; the drain electrode of the NMOS tube M403 is respectively connected with the other end of the resistor R402, the grid electrode of the NMOS tube M403, the grid electrode of the NMOS tube M420 and the grid electrode of the NMOS tube M415, and the source electrode of the NMOS tube M403 is respectively connected with the drain electrode of the NMOS tube M404 and the grid electrode of the NMOS tube M404; the source electrode of the NMOS tube M404 is grounded;

the grid electrode of the NMOS tube M405 is connected with the grid electrode of the PMOS tube M409, the drain electrode of the NMOS tube M405 is respectively connected with the drain electrode of the PMOS tube M411, the grid electrode of the PMOS tube M412, the grid electrode of the NMOS tube M414, the grid electrode of the NMOS tube M417, the source electrode of the PMOS tube M413 and the drain electrode of the NMOS tube M414, and the source electrode of the NMOS tube M406 is respectively connected with the source electrode of the NMOS tube M407 and one end of a current source M407; the other end of the current source M407 is grounded; the drain of the NMOS tube M406 is respectively connected with the drain of the NMOS tube M417, the source of the PMOS tube M418, the drain of the PMOS tube M412 and the gate of the PMOS tube M423; the grid electrode of the PMOS tube M410 is connected with the grid electrode of the NMOS tube M406, the source electrode of the PMOS tube M410 is respectively connected with the other end of the current source M408 and the source electrode of the PMOS tube M409, and the drain electrode of the PMOS tube M419, the source electrode of the NMOS tube M420, the drain electrode of the NMOS tube M422 and the grid electrode of the NMOS tube M424 are respectively connected;

the drain electrode of the PMOS tube M409 is respectively connected with the source electrode of the NMOS tube M415, the drain electrode of the PMOS tube M416, the drain electrode of the NMOS tube M421, the gate electrode of the NMOS tube M422, the gate electrode of the PMOS tube M416 and the gate electrode of the PMOS tube M419; the source electrode of the NMOS tube M421 is grounded; the source electrode of the NMOS tube M422 is grounded; the source electrode of the NMOS tube M414 is connected with the drain electrode of the NMOS tube M415; the drain electrode of the PMOS tube M413 is connected with the source electrode of the PMOS tube M416; the source electrode of the PMOS tube M419 is respectively connected with the drain electrode of the PMOS tube M418 and one end of the capacitor C401; the source electrode of the NMOS tube M417 is respectively connected with the drain electrode of the NMOS tube M420 and one end of the capacitor C402; one end of the resistor R403 is connected with the other end of the capacitor C401; the other end of the capacitor C402 is connected with one end of a resistor R404; the drain of the PMOS tube M423 is respectively connected with the other end of the resistor R403, the other end of the resistor R404 and the drain of the NMOS tube M424, and serves as the output end of the buffer A1, the buffer A2 or the buffer A3; the source of the NMOS transistor M424 is grounded.

The beneficial effects of the above further scheme are: the NMOS transistors M405 and M406 and the PMOS transistors M409 and M410 are structurally designed so that each buffer can realize rail-to-rail input; the 8 MOS tubes M413, M414, M415, M416, M417, M418, M419 and M420 adopt a cross-coupled connection mode, and self-regulation and control of quiescent current are carried out in a self-adaptive manner through mutual feedback, so that the buffer circuit not only works in an AB type bias state, but also is insensitive to power supply voltage, and accurate voltage following can be realized; m423 and M424 form a push-pull structure, and rail-to-rail output is realized. The respective buffers of the present invention have good voltage following capability.

Furthermore, the first thermometer code decoder and the second thermometer code decoder both belong to a combinational logic digital circuit module, an output end of the first thermometer code decoder outputs a 5-bit binary number, an output end of the second thermometer code decoder outputs a 4-bit binary number, and output binary numbers of the first thermometer code decoder and the second thermometer code decoder are the total number of high level values input by respective input ends.

Furthermore, the first switch logic control module, the second switch logic control module and the third switch logic control module all belong to a combinational logic digital circuit module, the input ends of the first switch logic control module, the second switch logic control module and the third switch logic control module are all 5-bit binary number input ports din, and the output ends of the first switch logic control module, the second switch logic control module and the third switch logic control module all comprise 15 2-bit binary number output ends from s1 to s 15; the input-output relationship among the first switch logic control module, the second switch logic control module and the third switch logic control module is represented by decimal:

when din is 0, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 2, s9 is 2, s10 is 2, s11 is 2, s12 is 2, s13 is 2, s14 is 2, s15 is 2;

when din is 1, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 2, s9 is 2, s10 is 2, s11 is 2, s12 is 2, s13 is 2, s14 is 2, s15 is 1;

when din is 2, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 2, s9 is 2, s10 is 2, s11 is 2, s12 is 2, s13 is 2, s14 is 1, s15 is 1;

when din is 3, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 2, s9 is 2, s10 is 2, s11 is 2, s12 is 2, s13 is 1, s14 is 1, s15 is 1;

when din is 4, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 2, s9 is 2, s10 is 2, s11 is 2, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 5, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 2, s9 is 2, s10 is 2, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 6, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 2, s9 is 2, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 7, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 2, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 8, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 2, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 9, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 2, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 10, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 2, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 11, s1 is 2, s2 is 2, s3 is 2, s4 is 2, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 12, s1 is 2, s2 is 2, s3 is 2, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 13, s1 is 2, s2 is 2, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 14, s1 is 2, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 15, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 1;

when din is 16, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 1, s15 is 0;

when din is 17, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 1, s14 is 0, s15 is 0;

when din is 18, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 1, s13 is 0, s14 is 0, s15 is 0;

when din is 19, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 1, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 20, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 1, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 21, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 1, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 22, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 1, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 23, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 1, s8 is 0, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 24, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 1, s7 is 0, s8 is 0, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 25, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 1, s6 is 0, s7 is 0, s8 is 0, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 26, s1 is 1, s2 is 1, s3 is 1, s4 is 1, s5 is 0, s6 is 0, s7 is 0, s8 is 0, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 27, s1 is 1, s2 is 1, s3 is 1, s4 is 0, s5 is 0, s6 is 0, s7 is 0, s8 is 0, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 28, s1 is 1, s2 is 1, s3 is 0, s4 is 0, s5 is 0, s6 is 0, s7 is 0, s8 is 0, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 29, s1 is 1, s2 is 0, s3 is 0, s4 is 0, s5 is 0, s6 is 0, s7 is 0, s8 is 0, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, s15 is 0;

when din is 30, s1 is 0, s2 is 0, s3 is 0, s4 is 0, s5 is 0, s6 is 0, s7 is 0, s8 is 0, s9 is 0, s10 is 0, s11 is 0, s12 is 0, s13 is 0, s14 is 0, and s15 is 0.

Further, the first self-calibration module, the second self-calibration module and the third self-calibration module all belong to sequential logic digital circuit modules, and input/output port signals of the sequential logic digital circuit modules all follow the following formula:

wherein a is the input signal value at the end d1, and the end d1 is the first self-calibration module d1[4:0]]End, second self-calibration Module d1[8:0]]Terminal or third self-calibration module d1[12:0]]A terminal; b is the input signal value at the end d2, and the end d2 is the first self-calibration module d2[4:0]]End, second self-calibration Module d2[4:0]]Terminal or third self-calibration module d2[3:0]]A terminal;

a three-dimensional column vector consisting of a, b and a numerical value 1; d_kIs d3[15: 0)]Value of the input signal, y_kIs the output terminal dout value, i.e. the first self-calibration module dout [8:0]]Terminal and second self-calibration module dout [12:0]]Terminal or first self-calibration Module dout [15:0]]A terminal; w is a_k ^TIs a weight vector w_kThe transpose operation of (a) weight vector w_kIs a three-dimensional column vector; weight vector w of first self-calibration module, second self-calibration module and third self-calibration module_kAre iteratively updated when the rising edge of the clock signal received by each clk terminal occurs according to the following formula:

w_k+1is a weight vector w_kIteratively updated vectors; μ is the iteration step.

The invention has the beneficial effects that: the input signal is subjected to coarse quantization through the first sub ADC, and a quantization result of the input signal is coded into a control signal by the first switch logic control module to control the first MDAC, so that the difference amplification of the subtraction result of the input signal and the coarse quantization result is realized, and the difference amplification is transmitted to a post-stage circuit; the second sub-ADC, the second switch logic control module, the second MDAC, the third sub-ADC, the third switch logic control module and the third MDAC follow the process, and quantization and difference amplification are performed step by step in a pipeline mode until the fourth sub-ADC performs end quantization; meanwhile, the first self-calibration module, the second self-calibration module and the third self-calibration module calibrate the quantization codes of the sub-ADCs according to the quantization coding result of the low-speed ADC, so that high-speed and high-precision pipelined analog-to-digital conversion is realized.

Drawings

FIG. 1 is a top level schematic diagram of a self-calibrating pipelined ADC;

fig. 2 is a circuit diagram of a first sub-ADC, a second sub-ADC and a third sub-ADC;

FIG. 3 is a circuit diagram of a first MDAC, a second MDAC, and a third MDAC;

FIG. 4 is a fourth sub-ADC circuit diagram;

FIG. 5 is a circuit diagram of a buffer;

FIG. 6 is a graph of self-calibrating pipelined ADC dynamics when an 0.91796MHz signal is input;

FIG. 7 is a graph of self-calibrating pipelined ADC dynamics when an 9.58984MHz signal is input.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.

In one embodiment of the invention, as shown in fig. 1, a self-calibrating pipelined ADC having 16-bit resolution, comprises: the buffer A1, the buffer A2, the buffer A3, the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC, the third gain digital-to-analog converter MDAC, the first sub-ADC, the second sub-ADC, the third sub-ADC, the fourth sub-ADC, the first switch logic control module, the second switch logic control module, the third switch logic control module, the first self-calibration module, the second self-calibration module, the third self-calibration module, the low-speed ADC, the inverter U1, the inverter U2, the inverter U3, the inverter U4, the inverter U5, the inverter U6, the inverter U7, the inverter U8, the inverter U9 and the inverter U10;

The invention carries out coarse quantization on an input signal through a first sub ADC, and a quantization result is coded into a control signal by a first switch logic control module to control a first gain digital-to-analog converter (MDAC) so as to amplify the difference value of a subtraction result of the input signal and the coarse quantization result and transmit the difference value to a post-stage circuit; the second sub-ADC, the second switch logic control module, the second gain digital-to-analog converter MDAC, the third sub-ADC, the third switch logic control module and the third gain digital-to-analog converter MDAC follow the process, and the quantization and difference amplification are performed step by step in a pipeline mode until the fourth sub-ADC performs end quantization; meanwhile, the first self-calibration module, the second self-calibration module and the third self-calibration module calibrate the quantization codes of the sub-ADCs according to the quantization coding result of the low-speed ADC, so that high-speed and high-precision pipelined analog-to-digital conversion is realized.

As shown in fig. 2, the first sub-ADC, the second sub-ADC and the third sub-ADC have the same structure, and each of the first sub-ADC, the second sub-ADC and the third sub-ADC includes: 31 resistors from the resistor R101 to the resistor R131, 30 dynamic comparators from the dynamic comparator A101 to the dynamic comparator A130 and a first thermometer code decoder;

In the present embodiment, each dynamic comparator uses a conventional dynamic comparator in the field of high-speed integrated circuits.

As shown in fig. 3, the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC, and the third gain digital-to-analog converter MDAC have the same structure, and each of the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC, and the third gain digital-to-analog converter MDAC: 15 selectors from the selector U201 to the selector U2015, 34 CMOS complementary switches from the CMOS complementary switch K201 to the CMOS complementary switch K234, 16 capacitors from the capacitor C201 to the capacitor C216 and an operational amplifier A201;

It should be noted that in the pipelined ADC circuit structure proposed by the present invention, the operational amplifier a201 needs to use a high-speed operational amplifier with a fast conversion rate and a gain-bandwidth product of not less than 1.25GHz, and in this embodiment, a three-stage collate RMRIC operational amplifier scheme proposed by seido university of western electronic technology in "16 bit 100MSPS pipelined ADC key circuit and digital calibration technical research" master paper is adopted.

The first switch logic control module, the second switch logic control module and the third switch logic control module belong to a combinational logic digital circuit module, the input ends of the first switch logic control module, the second switch logic control module and the third switch logic control module are all 5-bit binary number input ports din, and the output ends of the first switch logic control module, the second switch logic control module and the third switch logic control module respectively comprise 15 2-bit binary number output ends from s1 to s 15; the input-output relationship among the first switch logic control module, the second switch logic control module and the third switch logic control module is represented by decimal:

Under the logic mechanism, each gain digital-to-analog converter MDAC can realize subtraction amplification under the control of each switch logic control module: each selector plays a role in selecting and connecting a high reference voltage vrefp, a common mode level vcm and a low reference voltage vrefn, and the selection mode is controlled by the quantization codes of the sub-ADCs converted by each switch logic control module.

In this embodiment, vrefp is 3.25V, vcm is 1.65V, and vrefn is 0.05V, thereby realizing a quantization range of 0.05V to 3.25V.

As shown in fig. 4, the fourth sub ADC includes: 16 resistors from the resistor R301 to the resistor R316, 15 dynamic comparators from the dynamic comparator A301 to the dynamic comparator A15 and a second thermometer code decoder;

The first thermometer code decoder and the second thermometer code decoder both belong to a combinational logic digital circuit module, the output end of the first thermometer code decoder outputs 5-bit binary numbers, the output end of the second thermometer code decoder outputs 4-bit binary numbers, and the output binary numbers of the first thermometer code decoder and the second thermometer code decoder are the total number of input high level values of the respective input ends.

As shown in fig. 5, the structures of the buffer a1, the buffer a2 and the buffer A3 are the same, and each of them includes: a PMOS tube M401, a PMOS tube M402, an NMOS tube M403, an NMOS tube M404, an NMOS tube M405, an NMOS tube M406, a PMOS tube M409, a PMOS tube M410, a PMOS tube M411, a PMOS tube M412, a PMOS tube M413, an NMOS tube M414, an NMOS tube M415, a PMOS tube M416, an NMOS tube M417, a PMOS tube M418, a PMOS tube M419, an NMOS tube M420, an NMOS tube M421, an NMOS tube M422, a PMOS tube M423, an NMOS tube M424, a grounding resistor R401, a resistor R402, a current source M407, a current source M408, a capacitor C401, a capacitor C402, a resistor R403 and a resistor R404;

The first self-calibration module, the second self-calibration module and the third self-calibration module all belong to sequential logic digital circuit modules, and signals of input and output ports of the sequential logic digital circuit modules all follow the following formula:

The specific circuit structure and the switch capacitor control mode of the gain digital-to-analog converter MDAC ensure that the input and the output of the gain digital-to-analog converter MDAC have specific expression forms, and the iterative design of machine learning needs to be carried out by specifically considering the transfer function of the operational amplifier A201 limited gain error and the capacitor mismatch error. The formulas (1) and (2) are iteration formulas designed according to the specific circuit structure of the gain digital-to-analog converter MDAC and by considering the error, have specificity and are specially suitable for the design; weight vector w for adaptive machine learning training through three self-calibration modules_kAs a transfer function, the method replaces the data summarization method that the prior pipeline ADC in the field combines the coding results of all the sub-ADCs in a staggered addition mode, and uses the low-speed high-precision ADC as a reference standard for error convergence to summarize the quantitative coding results of all the sub-ADCs of the pipeline ADC so as to realize high precision; the speed of the pipeline ADC depends on the speeds of the gain digital-to-analog converter MDAC and the sub-ADC, and the clock source uses 20MHz frequency, so the self-calibration pipeline ADC has the speed of 20MSPS (Million Samples per second) and has the characteristics of high speed and high precision.

The dynamic characteristics of the self-calibration pipeline ADC of the present embodiment are shown in fig. 6 and 7, and when 0.91796MHz signals are input, the spurious-free dynamic range SFDR is 97.8dB, the signal-to-noise-distortion ratio SNDR is 92.3dB, and the effective number ENOB is 15.04 bit; when 9.58984MHz signal is input, the spurious free dynamic range SFDR is 97.4dB, the signal-to-noise-distortion ratio SNDR is 91.9dB, and the effective bit number ENOB is 14.97 bit.

TABLE 1 dynamic behavior of self-calibrating pipelined ADCs

The overall results are shown in Table 2, which show that the properties are excellent.

TABLE 2 pipelined ADC performance summary

Claims

1. A self-calibrating pipelined ADC, comprising: the buffer A1, the buffer A2, the buffer A3, the first gain digital-to-analog converter MDAC, the second gain digital-to-analog converter MDAC, the third gain digital-to-analog converter MDAC, the first sub-ADC, the second sub-ADC, the third sub-ADC, the fourth sub-ADC, the first switch logic control module, the second switch logic control module, the third switch logic control module, the first self-calibration module, the second self-calibration module, the third self-calibration module, the low-speed ADC, the inverter U1, the inverter U2, the inverter U3, the inverter U4, the inverter U5, the inverter U6, the inverter U7, the inverter U8, the inverter U9 and the inverter U10;

the first sub ADC is used for carrying out coarse quantization coding on an input signal to obtain a quantization result; the first switch logic control module is used for coding a control signal according to a quantization result and controlling the first gain digital-to-analog converter (MDAC) to obtain a difference value between the amplified quantization result and an input signal;

the second sub-ADC, the second switch logic control module, the second gain digital-to-analog converter MDAC, the third sub-ADC, the third switch logic control module and the third gain digital-to-analog converter MDAC are used for carrying out step-by-step quantization and amplification in a pipeline mode according to the amplified quantization result and the difference value of the input signal until the fourth sub-ADC carries out terminal quantization coding; the first self-calibration module, the second self-calibration module and the third self-calibration module are used for calibrating quantization codes of each sub-ADC according to the quantization coding result of the low-speed ADC, so that high-speed and high-precision pipelined analog-to-digital conversion is realized;

the buffer A1, the buffer A2 and the buffer A3 are used for carrying out impedance matching, front-stage and rear-stage isolation and voltage following on signals in a pipelined analog-to-digital conversion process for realizing high speed and high precision; the inverter U1, the inverter U2, the inverter U3, the inverter U4, the inverter U5, the inverter U6, the inverter U7, the inverter U8, the inverter U9 and the inverter U10 are used for inverting and delaying signals in a pipelined analog-to-digital conversion process for realizing high speed and high precision.

2. The self-calibrating pipelined ADC of claim 1, wherein the non-inverting input of the buffer a1 is connected to the Vin terminal of the first sub-ADC and the Vin terminal of the low-speed ADC, respectively, and serves as the input Vin of the self-calibrating pipelined ADC; the inverting input end of the buffer A1 is respectively connected with the output end of the buffer A1 and the vin end of the first gain digital-to-analog converter MDAC; the s 1-s 15 ends of the first gain digital-to-analog converter MDAC are connected with the output end of the first switch logic control module, and the CLKS ends of the first gain digital-to-analog converter MDAC are respectively connected with the clka end of the second gain digital-to-analog converter MDAC and the CLKS end of the third gain digital-to-analog converter MDAC and serve as a sampling phase clock signal end CLKS of the self-calibration pipeline ADC;

3. The self-calibrating pipelined ADC of claim 2, wherein the first, second and third sub-ADCs are structurally identical and each comprise: 31 resistors from the resistor R101 to the resistor R131, 30 dynamic comparators from the dynamic comparator A101 to the dynamic comparator A130 and a first thermometer code decoder;

4. The self-calibrating pipelined ADC of claim 2, wherein the first, second and third gain digital-to-analog converters MDAC, MDAC and MDAC are structurally identical, each comprising: 15 selectors from the selector U201 to the selector U2015, 34 CMOS complementary switches from the CMOS complementary switch K201 to the CMOS complementary switch K234, 16 capacitors from the capacitor C201 to the capacitor C216 and an operational amplifier A201;

5. The self-calibrating pipelined ADC of claim 3, wherein the fourth sub-ADC comprises: 16 resistors from the resistor R301 to the resistor R316, 15 dynamic comparators from the dynamic comparator A301 to the dynamic comparator A15 and a second thermometer code decoder;

6. The self-calibrating pipelined ADC of claim 2, wherein said buffer a1, buffer a2, and buffer A3 are all identical in structure and comprise: a PMOS tube M401, a PMOS tube M402, an NMOS tube M403, an NMOS tube M404, an NMOS tube M405, an NMOS tube M406, a PMOS tube M409, a PMOS tube M410, a PMOS tube M411, a PMOS tube M412, a PMOS tube M413, an NMOS tube M414, an NMOS tube M415, a PMOS tube M416, an NMOS tube M417, a PMOS tube M418, a PMOS tube M419, an NMOS tube M420, an NMOS tube M421, an NMOS tube M422, a PMOS tube M423, an NMOS tube M424, a grounding resistor R401, a resistor R402, a current source M407, a current source M408, a capacitor C401, a capacitor C402, a resistor R403 and a resistor R404;

7. The self-calibrating pipelined ADC of claim 5 wherein said first thermometer code decoder and said second thermometer code decoder are both comprised of combinational logic digital circuit blocks, wherein an output of said first thermometer code decoder outputs a 5 bit binary number and an output of said second thermometer code decoder outputs a 4bit binary number, and wherein the output binary numbers of said first thermometer code decoder and said second thermometer code decoder are both the total number of high values input to their respective inputs.

8. The self-calibration pipelined ADC of claim 1, wherein the first, second and third switch logic control modules are all combinational logic digital circuit modules, and have input terminals that are all 5-bit binary input ports din and output terminals that include 15 2-bit binary output terminals from s1 to s 15; the input-output relationship among the first switch logic control module, the second switch logic control module and the third switch logic control module is represented by decimal:

9. The self-calibrating pipelined ADC of claim 1, wherein the first self-calibrating module, the second self-calibrating module and the third self-calibrating module belong to sequential logic digital circuit modules, and the input-output port signals of the modules all follow the following formula: