CN110880937B - N bit analog-to-digital converter based on progressive approximation architecture - Google Patents
N bit analog-to-digital converter based on progressive approximation architecture Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides an n-bit analog-to-digital converter of a progressive approximation architecture, which comprises an i+1-order sub-ADC, an i-order sub-DAC, a sample hold circuit, a clock management circuit, a power management circuit and an output control circuit, wherein i is any positive integer; the input analog signals to be tested enter all sub-ADCs simultaneously after passing through a sample hold circuit, and are compared simultaneously, the reference voltage of each sub-ADC is provided by the sub-DAC of the previous stage, the digital signal output of the sub-ADC is also transmitted to the sub-DAC of the current stage, the reference voltages of the sub-ADC and the sub-DAC of the next stage are guided, and the output value with lower bit weight is obtained by reducing the reference voltages step by step. The analog-to-digital converter does not perform any analog operation on the analog signal to be tested, meanwhile, a large-scale circuit which has an exponential relation with the resolution is split into a multi-order small-scale circuit, and the whole scale of the circuit is reduced.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an n-bit analog-to-digital converter of a progressive approximation architecture.
Background
The analog-digital converter is used as a very important data converter and is responsible for converting analog signals into digital signals, so that the analog-digital converter is widely applied to the fields of electronics, communication, medical treatment, internet of things and the like, and particularly, most of output signals of the sensor are converted by the analog-digital converter and then enter a post-digital system for further processing, so that the analog-digital converter still has a very large application prospect in the future.
Since the last century, scientific research and technicians in each country have designed many analog-to-digital converter architectures, and in recent years, as the frequency of analog signals to be measured is higher and higher, the sampling rate requirement of the analog-to-digital converter is higher and higher, and even a radio frequency ADC is used to directly convert radio frequency signals, so that a ADC (Analogto Digital Converter) architecture is required to adapt to higher sampling speed as much as possible while maintaining resolution.
In the existing architecture of the high-speed analog-to-digital converter, the number of comparators used by the Flash architecture is in an exponential relation with the resolution, the circuit scale of the Flash analog-to-digital converter with higher resolution is very large, and the production cost and the power consumption are also very large; the pipeline architecture can effectively reduce the scale of a circuit, but analog quantity is subjected to analog operation when an analog signal to be detected is processed, errors generated in the operation process affect final output, and the longer the pipeline is, the larger the errors are; the folding architecture has the disadvantage that the analog signal is simulated when the analog signal to be measured is processed, like the pipeline architecture.
Disclosure of Invention
The invention aims at: aiming at the problems existing in the prior art, an n-bit analog-to-digital converter based on a progressive approximation architecture is provided, an input analog signal to be detected enters all sub-ADC (Analogto Digital Converter) simultaneously after passing through a sample-hold circuit, and is compared simultaneously, the reference voltage of each sub-ADC is provided by the sub-DAC of the last order, the digital signal output of the sub-ADC is also transmitted to the sub-DAC of the first order, the reference voltages of the sub-ADC and the sub-DAC of the next order are guided, and the output value with lower bit weight is obtained by reducing the reference voltages step by step. The analog-to-digital converter does not perform any analog operation on the analog signal to be tested, meanwhile, a large-scale circuit which has an exponential relation with the resolution is split into a multi-order small-scale circuit, and the whole scale of the circuit is reduced.
The invention aims at realizing the following technical scheme:
the n-bit analog-to-digital converter of the progressive approximation architecture comprises an i+1-order sub-ADC, an i-order sub-DAC, a sample hold circuit, a clock management circuit, a power management circuit and an output control circuit, wherein i is any positive integer; the clock management circuit provides working time sequences of the sub-ADC, the sub-DAC, the output control circuit and the sample hold circuit; the power management circuit provides overall power supply and initial reference voltage; the sampling hold circuit processes the input analog signals to be tested and then directly sends the processed analog signals into all sub-ADCs, and digital signals output by the sub-ADCs of each order are integrated by the output control circuit and then output in parallel; the digital code converted by the kth-order sub-ADC guides the kth-order sub-DAC to generate upper and lower limit voltages of a quantization interval where an input analog signal is located, wherein k is more than or equal to 0 and less than or equal to i-1; the upper and lower limit voltages generated by the kth sub-DAC are used as reference voltages of the kth+1-order sub-ADC and the sub-DAC, the kth+1-order sub-ADC is guided to conduct further quantization, and the kth+1-order sub-DAC is guided to provide the upper and lower limit voltages of the kth+2-order sub-ADC and the sub-DAC.
Further, the sum n of the resolution of each step of the sub-ADC of the analog-to-digital converter.
Further, each order resolution of the sub-DAC of the analog-to-digital converter is the same as that of the same order sub-ADC.
Further, the sub-ADC architecture is a Flash architecture.
Further, the sub-ADC comprises a divider resistor network, a comparator and an encoder; the voltage at two ends of the voltage dividing resistor network is provided by a previous-stage sub-DAC, and if the voltage dividing resistor network is the 0 th-stage voltage dividing resistor network, the voltage is divided by resistors and is generated by a reference voltage source; the comparator output is encoded by the encoder and then output to the output control circuit as the digital result after the conversion of the segment.
Further, if the resolution of the kth sub-ADC is kkbit, p equivalent voltage dividing resistors are required, and p=2 kk And p-1 comparators.
Further, the sub-DAC is a dual output voltage DAC.
Further, the sub-DAC comprises a divider resistor network, a double-pole single-throw electronic switch, a decoder and a precision amplifier; the two ends of one side of each double-pole single-throw electronic switch are connected with two ends of a corresponding voltage dividing resistor, the upper ends of all switches in the other side are connected to the same node, isolated by a precision amplifier and output as an output upper limit voltage, the lower ends of all switches are connected to the same node, isolated by the precision amplifier and output as an output lower limit voltage, digital signals output by the sub-ADC of the present stage are decoded by a decoder and then control the on-off of different double-pole single-throw electronic switches, the output upper limit voltage and the output lower limit voltage are used as reference voltages to be transmitted to the sub-ADC and the sub-DAC of the next stage, and the voltages at the two ends of a voltage dividing resistor network of the sub-DAC of the present stage are provided by the sub-DAC of the previous stage, and if the sub-DAC of the present stage 0 th stage is generated by resistor voltage dividing and reference voltage source.
Further, if the resolution of the kth-stage sub-DAC is kkbit, q equivalent voltage dividing resistors and q double-pole single-throw electronic switches are required, where q=2 kk 。
Compared with the prior art, the invention has the following advantages:
1. the input analog signals to be detected are directly input into the sub-ADCs of all steps, the whole system does not perform any analog operation on the input analog signals to be detected, so that errors caused by analog operation (such as subtracters and the like) are avoided, the sub-ADCs are of a Flash architecture, the conversion speed is high, the sub-ADCs of all steps almost work simultaneously, and the digital signals are output in parallel, so that a higher sampling rate can be realized.
2. According to the n-bit analog-to-digital converter of the progressive approximation architecture, the current-stage sub-ADC is used for guiding the current-stage sub-DAC to generate two voltages adjacent in coding, and the voltages serve as reference voltages for guiding the next-stage sub-ADC and sub-DAC to work, so that the comparison range is gradually reduced, and the resolution is gradually improved.
3. The resolution ratio of each stage of sub-ADC and sub-DAC is not high, and meanwhile, an input analog signal to be detected is directly input into each stage of sub-ADC, so that the whole system only needs one sample hold circuit, and the scale of the whole circuit is smaller.
4. The clock signal only needs to control the sampling hold circuit and the output logic circuit, so that the time sequence control is simpler, and the clock signal has less interference to the whole system;
5. the resolutions of the sub-ADC and the sub-DAC of each order are not necessarily the same, the order of the whole system is not limited, and the sum of the resolutions of each order is only required to be the target n bit, so that the method has strong flexibility in design, and the orders and the resolutions of different combinations can be used according to the speed, the precision and the circuit scale.
Drawings
FIG. 1 is a system block diagram of the present invention;
FIG. 2 is a circuit diagram of the sub-ADC;
fig. 3 is a circuit diagram of the sub-DAC.
Identification description: 1-sub-ADC; 2-sub-DAC; 3-a sample-and-hold circuit; 4-a clock management circuit; 5-a power management circuit; 6-an output control circuit; 7-equivalent voltage dividing resistance; 8-a comparator; 9-an encoder; 10-equivalent voltage dividing resistor; 11-double pole single throw electronic switch; 12-a precision amplifier; 13-decoder.
In addition, for the sake of brevity, the digital signal lines between the sub-ADC 1 and the sub-DAC 2 and the output logic circuit 6, the output signal lines of the encoder 9, the input signal lines of the decoder 13 are all represented in the form of buses, and specific bit numbers are represented in the figure.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples.
Examples
Referring to fig. 1, the n-bit analog-to-digital converter based on the progressive approximation architecture of the invention is composed of an i+1-order sub-ADC, an i-order sub-DAC, a sample hold circuit, a clock management circuit, a power management circuit and an output control circuit, wherein an input analog signal to be detected directly enters all sub-ADCs after being sampled by the sample hold circuit, the sub-ADCs are Flash type analog-to-digital converters, and the sub-DACs are dual-output voltage type digital-to-analog converters.
Referring to fig. 1, the resolution of each sub-ADC and sub-DAC of the n-bit analog-to-digital converter based on the successive approximation architecture of the present invention is not necessarily the same, but the resolution of the same sub-ADC and sub-DAC is the same, and the sum of the resolutions of all sub-ADCs is the resolution of the whole system, and meanwhile, the system has no fixed requirement on the specific order and the resolution of each order, only the sum of the sub-ADCs of each order is the resolution of the whole system, so the present invention can be flexibly configured according to the requirements of speed, precision and circuit scale in design. Taking 14 bits as an example (n=14), it may be designed as 2 steps (each step is 7 bits), 3 steps (each step resolution may be 4 bits, 6 bits, or 5 bits, 4 bits), 4 steps (each step resolution may be 4 bits, 3 bits, etc.), or 7 steps (each step is 2 bits), but the higher the step number, the lower the speed, the smaller the circuit scale.
Referring to fig. 1, the lower the order, the higher the sub-ADC data conversion bit weight, the thicker the quantization, the lower the bit weight, and the finer the quantization.
Referring to FIG. 1, according to the n-bit analog-to-digital converter based on the successive approximation architecture, digital codes converted by a kth (0.ltoreq.k.ltoreq.i-1) sub-ADC guide the kth sub-DAC to generate upper and lower limit voltages of a quantization interval where an input analog signal is located, the upper and lower limit voltages generated by the kth sub-DAC serve as reference voltages of the (k+1) th sub-ADC and the sub-DAC, guide the (k+1) th sub-ADC to further quantize, and guide the (k+1) th sub-DAC to provide upper and lower limit voltages of the (k+2) th sub-ADC and the sub-DAC, so that measurement resolution is gradually increased.
Referring to fig. 1, the reference voltages of the 0 th order sub-ADC and sub-DAC of the n bit analog-to-digital converter based on the successive approximation architecture of the present invention are the measurement range of the whole system, and may be generated by a voltage dividing resistor or a reference voltage source, and may be negative.
Referring to fig. 1, the n-bit analog-to-digital converter based on the successive approximation architecture of the present invention is that the ith sub-ADC is the final quantization ADC, so the ith sub-DAC is not present.
Referring to fig. 1, the output control circuit 6 collects the output digital signals of all sub-ADCs 1 in one sampling period under the control of the clock signal, registers the digital signals and outputs the digital signals in parallel.
Referring to fig. 1, the prior art researches and related circuit structures of the sample-and-hold circuit 3, the clock management circuit 4, the power management circuit 5 and the output control circuit 6 of the n-bit analog-to-digital converter based on the successive approximation architecture of the present invention are quite perfect, and are not described herein.
Referring to fig. 2, the n bit analog-to-digital converter based on a progressive approximation architecture of the present invention, the sub-ADC is a Flash architecture ADC, and the single sub-ADC includes interfaces including: reference voltage inputs ref+ and ref-, analog signal output ain to be tested, digital signal output dout, and power interface. Each stage of comparison voltage is generated by a voltage dividing resistor network, and if the resolution of the kth-stage sub-ADC is kkbit, p equivalent voltage dividing resistors 7 (p=2 are needed kk ) And p-1 comparators 8, the upper and lower limit reference voltages of input are set at two ends of the voltage dividing resistor network, can be provided by the reference voltage source (0 th order) or the last-order sub-DAC (1 st order and later), the digital result after the comparator output is encoded by the encoder 9 and converted into the digital result is output to the digital signal output control circuit 6, and is simultaneously sent to the current-order sub-DAC (the ith order is not sent). The design of the encoder circuit is well established and will not be described in detail herein.
Referring to fig. 3, the n-bit analog-to-digital converter based on a successive approximation architecture of the present invention, the sub-DAC is a dual-output voltage type DAC, and a single sub-DAC includes interfaces including: reference voltages ref+ and ref-, digital signal input datain, double-circuitThe outputs Out + and Out-are pressed. Each stage of reference voltage is generated by a voltage dividing resistor network, if the resolution of the kth-stage sub-DAC is kkbit, q equivalent voltage dividing resistors 10 and q double-pole single-throw electronic switches 11 are needed (q=2) kk ) The two ends of the resistor voltage dividing network are input upper and lower limit reference voltages, the input reference voltages can be provided by a reference voltage source (0 th order) or a sub-DAC of the last order (1 st order and later), the input digital signals are decoded by a decoder 13 and then are controlled to be closed by each double-pole single-throw switch, one side of each double-pole single-throw switch is two ends of a corresponding voltage dividing resistor, the other side of each double-pole single-throw switch is a public output end, the output upper ends of all the double-pole single-throw switches are the same circuit node, the lower ends of all the double-pole single-throw switches are the same circuit node, and signals of the two nodes are isolated by two precision amplifiers 12 with gain of 1 and then output. The circuit designs of the precision amplifier 12 and the decoder 13 are quite well established, and will not be described in detail herein.
To sum up: the n bit analog-to-digital converter based on the progressive approximation architecture has the advantages of high sampling speed, high resolution, small circuit scale and high design flexibility, and the measured input analog quantity is gradually approximated by gradually reducing the reference voltage of each step, so that the fine quantization requirement is realized.
The foregoing description of the preferred embodiment of the invention is not intended to be limiting, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (5)
1. The n-bit analog-to-digital converter of the progressive approximation architecture is characterized by comprising an i+1-order sub-ADC, an i-order sub-DAC, a sample hold circuit, a clock management circuit, a power management circuit and an output control circuit, wherein i is any positive integer; the clock management circuit provides working time sequences of the sub-ADC, the sub-DAC, the output control circuit and the sample hold circuit; the power management circuit provides overall power supply and initial reference voltage; the sampling hold circuit processes the input analog signals to be tested and then directly sends the processed analog signals into all sub-ADCs, and digital signals output by the sub-ADCs of each order are integrated by the output control circuit and then output in parallel; the digital code converted by the kth-order sub-ADC guides the kth-order sub-DAC to generate upper and lower limit voltages of a quantization interval where an input analog signal is located, wherein k is more than or equal to 0 and less than or equal to i-1; the upper limit voltage and the lower limit voltage generated by the kth sub-DAC are used as reference voltages of the kth+1-order sub-ADC and the sub-DAC, the kth+1-order sub-ADC is guided to conduct further quantization, and meanwhile the kth+1-order sub-DAC is guided to provide the upper limit voltage and the lower limit voltage of the kth+2-order sub-ADC and the sub-DAC; the sub-ADC architecture is a Flash architecture; the sub-ADC comprises a divider resistor network, a comparator and an encoder; the voltage at two ends of the voltage dividing resistor network is provided by a previous-stage sub-DAC, and if the voltage dividing resistor network is the 0 th-stage voltage dividing resistor network, the voltage is divided by resistors and is generated by a reference voltage source; the comparator output is encoded by the encoder and then is output to the output control circuit as a digital result after the conversion of the section; the sub-DAC is a dual-output voltage DAC; the sub-DAC comprises a divider resistor network, a double-pole single-throw electronic switch, a decoder and a precision amplifier; the two ends of one side of each double-pole single-throw electronic switch are connected with two ends of a corresponding voltage dividing resistor, the upper ends of all switches in the other side are connected to the same node, isolated by a precision amplifier and output as an output upper limit voltage, the lower ends of all switches are connected to the same node, isolated by the precision amplifier and output as an output lower limit voltage, digital signals output by the sub-ADC of the present stage are decoded by a decoder and then control the on-off of different double-pole single-throw electronic switches, the output upper limit voltage and the output lower limit voltage are used as reference voltages to be transmitted to the sub-ADC and the sub-DAC of the next stage, and the voltages at the two ends of a voltage dividing resistor network of the sub-DAC of the present stage are provided by the sub-DAC of the previous stage, and if the sub-DAC of the present stage 0 th stage is generated by resistor voltage dividing and reference voltage source.
2. The successive approximation architecture n-bit analog-to-digital converter of claim 1, wherein the sum of sub-ADC resolution levels of the analog-to-digital converter is n.
3. The successive approximation architecture n-bit analog-to-digital converter of claim 2, wherein each sub-DAC stage resolution of the analog-to-digital converter is the same as a same-stage sub-ADC.
4. The successive approximation architecture n-bit analog-to-digital converter of claim 1, wherein if the resolution of the kth order sub-ADC is kk bit, then p equivalent divider resistors are required, p = 2 kk And p-1 comparators.
5. The successive approximation architecture n-bit analog-to-digital converter of claim 1, wherein the resolution of the kth order sub-DAC is kkbit, then q equivalent voltage dividing resistors and q double pole single throw electronic switches are required, where q = 2 kk 。
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