CN104184478B - Complementary cascade phase inverter and increment Sigma Delta analog to digital conversion circuits - Google Patents

Abstract

The invention provides a complementary cascode inverter and an incremental Sigma-Delta analog-to-digital conversion circuit. Consists of a second-order ΣΔ modulator (101), a downsampling filter (102), a clock signal generating circuit (103) and a low-voltage-high voltage converter (104), the switch with a reset terminal in the second-order ΣΔ modulator (101) The capacitive integrator includes a complementary cascode inverter, the complementary cascode inverter includes a first PMOS1 transistor and a first NMOS1 transistor, and a second PMOS1 transistor is connected in series between the first PMOS1 transistor and the first NMOS1 transistor. The NMOS2 transistor and the second PMOS2 transistor, the second NMOS2 transistor is on top, the gate terminal of the second NMOS2 transistor is connected to the power supply voltage VDD, the second PMOS2 transistor is on the bottom, and the gate terminal of the second PMOS2 transistor is grounded to GND. The ADC of the invention has the characteristics of extremely low power consumption and can work under low power supply voltage, and is suitable for the fields of portable instruments, measurement and the like.

Description

Complementary cascode inverter and incremental Sigma-Delta analog-to-digital conversion circuit

technical field

The invention relates to a low-voltage and low-power incremental ΣΔ analog-to-digital converter.

Background technique

Sigma-Delta (ΣΔ) analog-to-digital converter (ADC) is widely used in communication and multimedia fields due to its simple structure, low power consumption, high precision and no need for device matching. However, the traditional ΣΔ structure is not suitable for instrumentation and measurement applications, where very high accuracy and linearity are required, and very low offset and gain errors are required in addition to high dynamic range and signal-to-noise ratio. Traditional ΣΔ ADCs only focus on dynamic characteristics such as signal-to-noise ratio and effective bits. Incremental ΣΔ ADCs are ideal for instrumentation and measurement applications because they provide low offset, low gain error, point-to-point, high-precision analog-to-digital conversion with relatively short conversion times.

In areas such as instrumentation and measurement, power consumption is a key circuit design consideration. At present, with the continuous reduction of device feature size in CMOS technology, the power supply voltage is also reduced proportionally, and the power consumption is also getting lower and lower. However, because the threshold voltage of MOS devices cannot be scaled down, the design of low-voltage analog circuits in ultra-deep submicron CMOS technology encounters great challenges, especially low-voltage and low-power operational amplifiers become the design bottleneck of low-voltage analog circuits.

Currently available techniques are: 1. Use body-driven or digitally assisted op amps, however, body-driven op amps have poor noise performance and limited bandwidth due to low transconductance; digitally assisted op amps require additional digital calibration circuits, And consume excess power consumption. Second, convert the circuit into a comparator-based, time-domain-based and charge-domain-based working mode, and omit the operational amplifier. However, comparator-based circuits are also limited by low supply voltages; the accuracy of time signals in time-domain-based circuits is severely disturbed by device matching and clock jitter; charge-domain-based circuits require special processes and higher supply voltages.

In recent years, a new way to solve this problem has been proposed: the inverter-based switched capacitor integrator. This method uses a simple inverter in a Class-AB or Class-C structure instead of an operational amplifier, which greatly reduces system power consumption and circuit complexity. However, there are two important problems in this method: the gain and bandwidth are severely limited; since the inverter has no virtual ground, self-establishment is required, resulting in extremely strong process sensitivity of the DC operating point and the AC characteristics of the inverter.

Contents of the invention

The object of the present invention is to provide a complementary cascode inverter with high gain, high bandwidth and low process sensitivity. The purpose of the present invention is also to provide a low-voltage, low-power incremental Sigma-Delta analog-to-digital conversion circuit based on complementary cascode inverters.

The complementary cascode inverter of the present invention includes a first PMOS1 transistor and a first NMOS1 transistor, a second NMOS2 transistor and a second PMOS2 transistor are connected in series between the first PMOS1 transistor and the first NMOS1 transistor, and the second NMOS2 transistor is On the top, the gate terminal of the second NMOS2 transistor is connected to the power supply voltage VDD, on the bottom of the second PMOS2 transistor, the gate terminal of the second PMOS2 transistor is grounded to GND.

The incremental Sigma-Delta analog-to-digital conversion circuit based on complementary cascode inverters of the present invention is composed of a second-order ΣΔ modulator 101, a down-sampling filter 102, a clock signal generation circuit 103 and a low-voltage-high voltage converter 104, The second-order ΣΔ modulator 101 converts the input DC voltage into a 1-bit digital quantity containing high-frequency quantization noise, the down-sampling filter 102 converts the 1-bit digital quantity into an N-bit digital output, and the clock signal generation circuit 103 generates the circuit required for operation All the clock control signals, some of the clock signals are converted into the high-voltage clock signal required by the modulator circuit through the low-voltage-high-voltage converter 104; the switched capacitor integrator with reset terminal in the second-order ΣΔ modulator 101 includes a complementary cascode inverter Phase device, the complementary cascode inverter includes a first PMOS1 transistor and a first NMOS1 transistor, a second NMOS2 transistor and a second PMOS2 transistor are connected in series between the first PMOS1 transistor and the first NMOS1 transistor, and the second NMOS2 transistor The transistor is on top, the gate terminal of the second NMOS2 transistor is connected to the power supply voltage VDD, the second PMOS2 transistor is on the bottom, and the gate terminal of the second PMOS2 transistor is grounded to GND.

The incremental Sigma-Delta analog-to-digital conversion circuit based on the complementary cascode inverter of the present invention may also include:

1. The second-order ΣΔ modulator 101 includes first and second summing circuits 101-1, 101-3, first and second switched capacitor integrators 101-2, 101-4 with reset terminals, and 1-bit comparison device 101-5 and the first and second 1-bit digital-to-analog converters 101-6, 101-7, the input voltage VIN and the output of the first 1-bit digital-to-analog converter 101-6 are in the first summation circuit 101-1 Carry out the summation operation in, the result of operation is input in the first switched capacitor integrator 101-2 with the reset terminal, the output of the switched capacitor integrator 101-2 with the reset terminal is connected with another second 1-bit digital-to-analog converter 101-2 The output of 7 is summed in the second summation circuit 101-3, and the result of the operation is input into the second switched capacitor integrator 101-4 with a reset terminal, and the output of the second switched capacitor integrator 101-4 with a reset terminal is Sent in the 1-bit comparator 101-5; The first and the second switched capacitor integrator 101-2 with the reset terminal, 101-4 are sampled by the first to the sixth switches S1, S2, S3, S4, S5, S6 Capacitor C _S , integral capacitor C _I , associated double-sampling capacitor C _C and complementary cascode inverters.

2. The downsampling filter 102 is made up of a ripple counter 102-1 and an accumulator 102-2, the accumulator 102-2 is made up of a full adder and a D flip-flop, and the 1bit digital value of the second-order ΣΔ modulator 101 The output is sent to the ripple counter 102-1, and the high level of the 1bit digital output is counted by the ripple counter 102-1, and the output of the ripple counter 102-1 is sent to the accumulator 102-2, and the output of the accumulator 102-2 The output is an N-bit digital output; the ripple counter 102-1 and the accumulator 102-2 are triggered on the rising and falling edges of the clock respectively.

In order to overcome the shortcomings of the existing ΣΔ ADC, the present invention provides a low-voltage and low-power incremental ΣΔ ADC. The ADC features extremely low power consumption and low power supply voltage, making it suitable for use in portable instrumentation and measurement.

The second-order ΣΔ modulator 101 is used to convert the input DC voltage into a 1-bit digital quantity containing high-frequency quantization noise, the down-sampling filter 102 converts the 1-bit digital quantity into an N-bit digital output, and the clock signal generation circuit 103 generates the circuit. All required clock control signals, part of the clock signals are converted into high voltage clock signals required by the modulator circuit through the low voltage-high voltage converter 104.

The incremental second-order ΣΔ modulator part 101 in the present invention is similar to the traditional ΣΔ modulator, including summation circuits 101-1, 101-3, switched capacitor integrators 101-2, 101-4 with reset terminals, and 1-bit comparison 101-5 and 1-bit digital-to-analog converter 101-6, 101-7, the input voltage VIN and the output of 1-bit digital-to-analog converter 101-6 are summed in the summation circuit 101-1, and the operation result is input In the switched capacitor integrator 101-2 with the reset terminal, the output of the integrator and the output of another 1-bit digital-to-analog converter 101-7 are summed in the summation circuit 101-3, and the result of the operation is input to the band In the switched capacitor integrator 101-4 at the reset end, the output of the integrator is sent to the 1-bit comparator 101-5, and the output of the comparator is a 1-bit digital quantity containing high-frequency quantization noise. The switched capacitor integrators 101-2 and 101-4 with reset terminals reset the integrating capacitor before each conversion.

The innovation of the present invention is that in the design of the switched capacitor integrators 101-2 and 101-4 with a reset terminal, a cascode inverter with a complementary structure is used instead of an operational amplifier. Switched capacitor integrators 101-2 and 101-4 with reset terminals are composed of switches S1, S2, S3, S4, S5, S6, sampling capacitor C _S , integrating capacitor C _I , related double sampling capacitor C _C and complementary cascode Composition of inverters. The complementary cascode inverter is to connect the NMOS2 transistor and the PMOS2 transistor in series between the simple inverter PMOS1 and NMOS1, where the NMOS2 transistor is on the top, and its gate terminal is connected to the power supply voltage VDD, and the PMOS2 transistor is on the bottom, and its gate terminal is grounded. GND. The process sensitivity of the performance of the inverter is reduced by utilizing the complementarity of the process sensitivity of the PMOS transistor and the NMOS transistor. In addition, the parasitic capacitance between the input and output of the complementary cascode inverter is isolated by the increased NMOS transistor and PMOS transistor, and the cascode structure has greater gain, so it has better settling accuracy. In the present invention, a correlated double-sampled switched capacitor integrator is also used to eliminate the offset of the inverter and establish a virtual point for the inverter to work.

The reset function after each conversion of the incremental ΣΔ ADC makes the design of the down-sampling digital filter greatly simplified, and the combination of comb filter + finite impulse response filter + vertical correction filter is not required. However, it is only necessary to count the high level of each conversion, and then accumulate to complete the down-sampling filter function. The down-sampling filter part 102 in the present invention is composed of a ripple counter 102-1 and an accumulator 102-2. Wherein the accumulator 102-2 is composed of a full adder and a D flip-flop. The 1-bit digital output of the second-order ΣΔ modulator part 101 is sent to the ripple counter 102-1, and the high level of the 1-bit digital output is counted by the ripple counter 102-1, and its output is sent to the accumulator 102-2, and the accumulator The output of 102-2 is the digital output of N-bit. In order to reduce the power consumption of the circuit, the ripple counter 102-1 and the accumulator 102-2 are triggered on the rising and falling edges of the clock respectively. Moreover, the digital filter involved in the present invention is specially processed in terms of timing, so that the power consumption of the filter is further reduced.

Description of drawings

FIG. 1 is a block diagram of the incremental ΣΔ ADC system of the present invention.

Figure 2 is a block diagram of a second-order delta ΣΔ modulator.

Figure 3-1 is a schematic diagram of an inverter-based switched capacitor integrator with a reset terminal.

Figure 3-2 is a circuit diagram of a complementary cascode inverter.

Figure 4 is a block diagram of the digital filter system.

detailed description

The specific implementation manners of the present invention will be described below in conjunction with the accompanying drawings.

The present invention is composed of a second-order delta ΣΔ modulator section 101 , a downsampling filter section 102 , a clock signal generation circuit 103 , and a low voltage-high voltage converter 104 . The second-order incremental ΣΔ modulator 101 converts the input DC voltage into a 1-bit digital quantity containing high-frequency quantization noise, and the 1-bit digital quantity is input to the down-sampling filter 102, and converted into an N-bit digital output, and the clock signal is generated A part of the clock signal generated by the circuit 103 is sent to the second-order delta ΣΔ modulator 101 through the low-voltage-high-voltage converter 104 , and the other part is sent to the down-sampling filter unit 102 .

The second-order delta ΣΔ modulator part 101 is the core circuit of the whole system, which determines the conversion speed and precision of the ADC. The second-order incremental ΣΔ modulator section 101 consists of summation circuits 101-1, 101-3, switched capacitor integrators with reset terminals 101-2, 101-4, 1-bit comparator 101-5 and 1-bit digital-to-analog converter 101-6, 101-7 composition. The input voltage VIN and the output of the 1-digit digital-to-analog converter 101-6 are summed in the summation circuit 101-1, and the operation result is input into the switched capacitor integrator 101-2 with a reset terminal, and the output of the integrator is the same as The output of another 1-bit digital-to-analog converter 101-7 is summed in the summation circuit 101-3, and the result of the operation is input to the switched capacitor integrator 101-4 with a reset terminal, and the output of the integrator is input to 1 bit In the comparator 101-5, the output of the comparator is a 1-bit digital quantity.

In the design of switched capacitor integrators 101-2 and 101-4 with reset terminals, cascode inverters with complementary structures are used instead of operational amplifiers. Switched capacitor integrators 101-2 and 101-4 with reset terminals are composed of switches S1, S2, S3, S4, S5, S6, sampling capacitor C _S , integrating capacitor C _I , related double sampling capacitor C _C and complementary cascode Composition of inverters.

The traditional integrator adopts the switched capacitor form based on the operational amplifier, and the inverter is used as the amplifier in the present invention, but since the inverter has only one input terminal, it cannot provide a virtual point. In closed-loop operation, the input to the inverter can be expressed as:

Here, A represents the DC gain of the inverter, and V _CI represents the voltage across the integrating capacitor C _I. Therefore, the input of the inverter is approximately the offset voltage of the inverter. The charge transferred during the feedback phase is C _S (V _I -V _OFF ), and the offset voltage is very sensitive to device size, threshold voltage, power supply voltage and process, which will cause errors in the integration establishment. Also, since the gain and bandwidth of a simple inverter are severely limited by the supply voltage, the integral settling is very imprecise.

In order to solve the above problems of the integrator, the present invention makes two modifications to the traditional integrator: 1. Introduce correlated double sampling to establish a virtual point and eliminate the offset; 2. Use a complementary cascode CMOS inverter.

FIG. 3-1 is a circuit of the switched capacitor integrator 101-2 with a reset terminal used in the second-order delta ΣΔ modulator part 101 in the present invention. In the sampling phase, the negative plate of the sampling capacitor C _S is connected to the input signal, the positive plate is grounded, the input signal is sampled to the sampling capacitor C _S , and the input and output terminals of the inverter are shorted to form a unit gain buffer form. The positive plate of the capacitor C _C is connected to the input of the inverter, and the negative plate is grounded, so the offset voltage V _OFF of the inverter is sampled to the capacitor C _C. At the beginning of the integration clock phase, the negative plate of the sampling capacitor CS is grounded, the positive plate is connected to the negative plate of _CC and the positive plate of the integrating capacitor _{C I} , the positive plate of _CC is connected to the input terminal of the inverter, and the negative plate of C _I The board is connected to the output terminal of the inverter. Therefore, the voltage at the V _G node becomes the input sampling voltage V _I , and the V _X node becomes V _OFF -V _I . When the closed loop is formed, since the negative feedback is formed through the capacitor _{C I} , the V _X node is V _OFF , and since CC maintains V _OFF , V _G is forced to become the signal ground, so V _G can be regarded as a virtual point, and the capacitor C _S The charge on is transferred to C _I. Both the sampling phase and the feedback phase _CC maintain the inverter offset voltage, so the offset voltage is eliminated. The relationship between input and output is:

C _S v _I (n+1/2)+C _I v _O (n)＝C _I v _O (n+1) (2)

The inverter shown in Figure 3-1 uses a complementary cascode inverter, and its circuit is shown in Figure 3-2. PMOS1 and NMOS1 form a simple inverter, and NMOS2 and PMOS2 are connected in series between PMOS1 and NMOS1, wherein NMOS2 is located between PMOS1 and PMOS2. The process sensitivity of the performance of the inverter is reduced by utilizing the complementarity of the process sensitivity of the PMOS transistor and the NMOS transistor. The cascode structure increases the output impedance, improves the gain of the inverter, and improves the signal establishment accuracy. Due to the increase of the gain, the inverter can work in the Class-AB structure, which improves the system bandwidth.

FIG. 4 is a structure diagram of the down-sampling filter unit 102 in the present invention, which is composed of a ripple counter 102-1 and an accumulator 102-2, wherein the accumulator is composed of a full adder and a D flip-flop. The 1-bit digital output of the second-order ΣΔ modulator part 101 is input to the ripple counter 102-1, and the high level of the 1-bit digital output is counted by the ripple counter 102-1, and its output is input to the accumulator 102-2, and the accumulator The output of 102-2 is the digital output of N-bit.

The input signal of the incremental ΣΔ ADC is generally a DC signal, so the calculation of the noise is different from that of the traditional ΣΔ ADC. To achieve the target accuracy, it can be calculated through a digital filter. For second-order modulators, the digital filter can be cascaded with two integrators.

The output of the second order modulator can be expressed as:

Y(z)＝z ^-1 X(z)+(1-z ^-1 ) ² E(z) (3)

Where Y represents the output of the modulator, X represents the input of the modulator, and E represents the quantization noise. The output of the digital filter after two integrations is expressed as:

The time-domain output of the digital filter can be expressed as:

If the quantization noise is finite, then:

So to achieve N-bit resolution, LSB=X _max /2 ^N , then

N=log ₂ n(n+1)-1bit (9)

Among them, n is the number of operations of the digital filter, that is, the oversampling multiple. Before each conversion, the ripple counter and accumulator are cleared, and the N-bit digital output is output after 2 ^(N+1) /2 cycles. The present invention performs two special processes on the timing of the digital filter. First, the ripple counter and the accumulator are triggered on the rising edge and falling edge of the clock respectively, so that the first level signal can be established for at least half a clock cycle, allowing the circuit to use an extremely weak current to establish a voltage signal, effectively Reduced power consumption. Second, the sampling clock is increased by one more than the oversampling multiple. If the oversampling multiple is n times, in fact, each sample is quantized n+1 times. This is because in the accumulator, each rising edge of the clock accumulates the value of the adder The result is passed to the D flip-flop, so the result in the D flip-flop after n+1 clocks is exactly the result of the previous n operations, so that the subsequent SRAM only needs to read from the D flip-flop, if there are only n Clock, then the SRAM needs to read from the adder, obviously the data retention and driving capabilities of the adder are far inferior to the D flip-flop.

The clock signal generating circuit 103 utilizes the input clock signal CLK to generate bidirectional non-overlapping clocks φ ₁ and φ ₂ , and falling edge delay signals φ _1d and φ _2d of φ ₁ and φ ₂ , and these four clock signals are delivered to the low voltage-high voltage The converter 104 converts the high level of the clock signal into a higher voltage, and then sends it to the second-order ΣΔ modulator as a control signal of the switch, so as to reduce the on-resistance of the switch.

Claims (2)

1. a kind of increment Sigma-Delta analog to digital conversion circuits based on complementary cascade phase inverter, modulated by second order Σ Δs Device (101), desampling fir filter (102), clock signal generating circuit (103) and low pressure-high-voltage converter (104) are formed, and two The DC voltage of input is converted into the 1bit digital quantities comprising High-frequency quantization noise, down-sampled filter by rank sigma Delta modulator (101) 1bit digital quantities are converted into N-bit numeral outputs, clock signal generating circuit (103) generative circuit work institute by ripple device (102) All clock control signals needed, section clock signal are converted into modulator circuit demand through low pressure-high-voltage converter (104) High voltage clock signal；It is characterized in that：The switched-capacitor integrator with reset terminal in second order sigma Delta modulator (101) is included mutually Cascade phase inverter is mended, the complementary cascade phase inverter includes the first PMOS and the first NMOS tube, in the first PMOS The source for the second NMOS tube and the second PMOS, the drain terminal of the second NMOS tube and the first PMOS of being connected between pipe and the first NMOS tube End is connected, and the source of the second PMOS is connected with the drain terminal of the first NMOS tube, the source of the second NMOS tube and the second PMOS Drain terminal is connected, and the grid end of the second NMOS tube meets supply voltage VDD, the second gate pmos end ground connection GND；

The desampling fir filter (102) is made up of ripple counter (102-1) and accumulator (102-2), the accumulator (102-2) is made up of full adder and d type flip flop, and the 1bit numeral outputs of second order sigma Delta modulator (101) are sent to ripple counter (102-1), the high level of 1bit numeral outputs is counted by ripple counter (102-1), ripple counter (102-1) Output is sent to accumulator (102-2), and the output of accumulator (102-2) is N-bit numeral output；Ripple counter (102- 1) triggered respectively in the rising edge and trailing edge of clock with accumulator (102-2).

2. the increment Sigma-Delta analog to digital conversion circuits according to claim 1 based on complementary cascade phase inverter, It is characterized in that：The second order sigma Delta modulator (101) includes first and second summing circuit (101-1,101-3), and first and Two switched-capacitor integrators (101-2,101-4) with reset terminal, 1 bit comparator (101-5) and first and second 1 digit mould turn The output of parallel operation (101-6,101-7), input voltage VIN and the one 1 digit weighted-voltage D/A converter (101-6) is in the first summing circuit Summation operation is carried out in (101-1), operation result is input in the switched-capacitor integrator (101-2) of first band reset terminal, the The output of one switched-capacitor integrator (101-2) with reset terminal is with the output of the 2nd 1 digit weighted-voltage D/A converter (101-7) second Summation operation is carried out in summing circuit (101-3), operation result is input to the second switched-capacitor integrator (101- with reset terminal 4) in, the output of the second switched-capacitor integrator (101-4) with reset terminal is sent in 1 bit comparator (101-5)；First and Two switched-capacitor integrators (101-2,101-4) with reset terminal are adopted by the first to the 6th switch (S1, S2, S3, S4, S5, S6) Sample electric capacity (C_S), integrating capacitor (C_I), correlated-double-sampling electric capacity (C_C) and complementary cascade phase inverter composition.