CN109216425A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN109216425A CN109216425A CN201811119472.3A CN201811119472A CN109216425A CN 109216425 A CN109216425 A CN 109216425A CN 201811119472 A CN201811119472 A CN 201811119472A CN 109216425 A CN109216425 A CN 109216425A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area, wherein the display area comprises a first display area and a second display area; the pixel display device comprises a plurality of reset wires and a plurality of pixels, wherein the reset wires comprise a first reset wire and a second reset wire, the first reset wire is positioned in a first display area, and the second reset wire is positioned in a second display area; the number of the pixels electrically connected with one first reset wire is a, the number of the pixels electrically connected with one second reset wire is b, wherein a and b are integers, and a is more than 0 and less than b; and one first reset wire is electrically connected with at least one capacitance compensation structure. The invention can improve the problem of uneven display and improve the display effect.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the continuous development of display technology, not only is the requirement for the display function of the display device higher and higher, but also the requirement for the shape is gradually increased in order to better adapt to the overall structure and the use requirement of the display device, so that the special-shaped display panel is generated. A conventional display panel has a rectangular shape, a display area is also substantially rectangular, a non-rectangular display panel is a non-rectangular display panel, and a non-rectangular display area is also non-rectangular, for example, a display area is circular or a display panel with a notch in the display area.
In the irregular display panel, the display panel is in an irregular shape, the signal lines are arranged in a different way from the conventional display panel, and the signal lines are arranged to adapt to the shape of the display panel, so that the number of pixels electrically connected to different signal lines in a display area of the display panel is different, and the display panel displays an area with different brightness, and the display brightness is not uniform.
Therefore, it is an urgent need in the art to provide a display panel and a display device that can improve the display non-uniformity and improve the display effect.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display device, which solve the technical problems of improving the display non-uniformity and improving the display effect.
In order to solve the above technical problem, a first aspect of the present invention provides a display panel including:
the display device comprises a display area and a non-display area surrounding the display area, wherein the display area comprises a first display area and a second display area;
the pixel display device comprises a plurality of reset wires and a plurality of pixels, wherein the reset wires comprise a first reset wire and a second reset wire, the first reset wire is positioned in a first display area, and the second reset wire is positioned in a second display area; the number of the pixels electrically connected with one first reset wire is a, the number of the pixels electrically connected with one second reset wire is b, wherein a and b are integers, and a is more than 0 and less than b;
and one first reset wire is electrically connected with at least one capacitance compensation structure.
Based on the same inventive concept, in a second aspect, the invention provides a display device including any one of the display panels proposed by the invention.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
according to the display panel provided by the invention, the capacitance compensation structure is arranged in the display panel, one first reset wire is electrically connected with at least one capacitance compensation structure, the capacitance compensation structure can increase the load on the first reset wire to compensate the load difference caused by different numbers of electrically connected pixels, and the loads on the first reset wire and the second reset wire are ensured to be approximately the same, so that the electric potentials of the light-emitting control nodes in the pixel driving circuits respectively electrically connected with the first reset wire and the second reset wire are approximately the same, further the light-emitting brightness of the pixels respectively electrically connected with the first reset wire and the second reset wire is ensured to be approximately the same, the problem of uneven display is solved, and the display effect is improved.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic diagram of an alternative implementation of a display panel according to an embodiment of the present invention;
FIG. 2 is a first schematic diagram of a pixel driving circuit in a display panel according to an embodiment of the present invention;
FIG. 3 is a second schematic diagram of a pixel driving circuit in a display panel according to an embodiment of the present invention;
FIG. 4 is a timing diagram of the pixel driving circuit of FIG. 3;
FIG. 5 is a schematic diagram of an alternative embodiment of a display panel according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a film layer of an alternative embodiment of a display panel according to an embodiment of the invention;
FIG. 7 is a schematic diagram of another alternative embodiment of a display panel according to an embodiment of the invention;
FIG. 8 is a partial schematic view of another alternative embodiment of a display panel according to an embodiment of the present invention;
FIG. 9 is a partial schematic view of another alternative embodiment of a display panel according to an embodiment of the invention;
FIG. 10 is a partial schematic view of another alternative embodiment of a display panel according to an embodiment of the invention;
FIG. 11 is a partial schematic view of another alternative embodiment of a display panel according to an embodiment of the invention;
FIG. 12 is a partial schematic view of another alternative embodiment of a display panel according to an embodiment of the present invention;
fig. 13 is a schematic view of a display device according to an embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a schematic diagram of an alternative implementation of a display panel according to an embodiment of the present invention. As shown in fig. 1, the display panel includes a display area AA and a non-display area BA surrounding the display area AA, the display area AA including a first display area AA1 and a second display area AA 2; reset trace FX includes a first reset trace FX1 and a second reset trace FX2, where first reset trace FX1 is located in first display area AA1, and second reset trace FX2 is located in second display area AA 2; the number of pixels sp electrically connected to one first reset trace FX1 is a, and the number of pixels sp electrically connected to one second reset trace FX2 is b, where a and b are integers, and 0 < a < b. A plurality of first reset traces FX1 may be included in the display panel, and the number of pixels sp electrically connected to each first reset trace FX1 may be the same or different. The display panel further includes a capacitance compensation structure BC, and one first reset trace FX1 is electrically connected to at least one capacitance compensation structure BC, that is, one first reset trace FX1 may also be electrically connected to a plurality of capacitance compensation structures according to the influence of factors such as the size of a capacitance to be compensated or the position of the capacitance compensation structure.
It should be noted that the shape of the display panel in fig. 1 is only schematically shown, and the display panel provided by the present invention may also be a display panel having a display area with a rounded corner, or a display panel having a display area with a notch. In short, as long as the display area has reset traces with different numbers of electrically connected pixels, the scheme provided by the invention can be adopted to perform capacitance compensation on the reset traces.
The reset trace provides a reset signal for the pixels in the display panel. The display panel includes a pixel driving circuit for driving the pixels to emit light. In the pixel driving circuit provided with the reset wire, the reset wire is generally used for resetting the pixel electrode, the pixel driving circuit further comprises a light-emitting control node, and the reset wire is also used for initializing the light-emitting control node.
Pixels in the same row in the display panel are all provided with signals by the same reset wiring, when the reset wiring resets the pixel electrode, current can flow on the reset wiring (namely certain current loss can exist), and when the number of pixels electrically connected with the reset wiring is small, the current flowing on the reset wiring is small, the voltage drop is small, namely the voltage drop generated by resetting the pixel electrode on the first reset wiring is small. Then in the pixel electrically connected to the first reset trace: after the first reset wiring initializes the light emitting control node, the potential of the light emitting control node is low, so that the potential of the light emitting control node in the pixel connected with the first reset wiring is different from the potential of the light emitting control node in the pixel adjacent to the second reset wiring. That is, when no design change is made, the brightness of the pixel electrically connected to the first reset trace and the brightness of the pixel electrically connected to the second reset trace are different from each other, which affects the display effect.
According to the display panel provided by the invention, the capacitance compensation structure is arranged in the display panel, one first reset wire is electrically connected with at least one capacitance compensation structure, the capacitance compensation structure can increase the load on the first reset wire to compensate the load difference caused by different numbers of electrically connected pixels, and the loads on the first reset wire and the second reset wire are ensured to be approximately the same, so that the electric potentials of the light-emitting control nodes in the pixel driving circuits respectively electrically connected with the first reset wire and the second reset wire are approximately the same, further the light-emitting brightness of the pixels respectively electrically connected with the first reset wire and the second reset wire is ensured to be approximately the same, the problem of uneven display is solved, and the display effect is improved.
The display panel provided by the invention also comprises a pixel driving circuit, wherein one pixel driving circuit can drive one light-emitting diode to emit light, and one pixel comprises at least one light-emitting diode. Fig. 2 is a first schematic diagram of a pixel driving circuit in a display panel according to an embodiment of the present invention. As shown in fig. 2, the pixel driving circuit includes: a light emission control unit 11, a data unit 12, an initialization unit 13, a driving unit 14, and a first node N1; wherein the initialization unit 13, the driving unit 14 and the data unit 12 are all connected to a first node N1; an initialization unit 13, configured to initialize the first node N1 based on a received reset signal (optionally, provided by a reset signal terminal S1), and reset the anode of the light emitting diode LI based on the received reset signal, wherein the reset trace FX may be electrically connected to the reset signal terminal S1, so as to provide the reset signal to the initialization unit 13; a light emitting control unit 11 for transmitting the received light emitting signal (optionally, provided by the light emitting signal terminal S2) to the light emitting diode LI, thereby controlling the light emitting diode LI to emit light; a data unit 12 for transmitting the received data signal (optionally provided by the data signal terminal S3) to the first node N1; and the driving unit 14 is used for controlling the driving unit 14 to be turned on according to the potential of the first node N1, so that the light emitting signal is transmitted to the light emitting diode LI. The first node N1 is a light-emitting control node.
In the process of driving the pixel to emit light, the initialization unit 13 resets the anode of the light emitting diode LI according to receiving the reset signal, and simultaneously the initialization unit 13 initializes the first node N1 according to receiving the reset signal; then, in the data writing phase, the data unit 12 receives the data signal and transmits the data signal to the first node N1, i.e. charges the first node N1; in the pixel lighting phase, the first node N1 discharges to control the driving unit 14 to be turned on, so that the lighting control unit 11 transmits a lighting signal to the light emitting diode LI to control the light emitting diode LI to light.
The structural block diagram of the pixel driving circuit corresponding to fig. 2 only illustrates the general structure of the pixel driving circuit, and the reset trace is connected to the initialization unit. In the following, only one specific pixel driving circuit is exemplified.
Fig. 3 is a second schematic diagram of a pixel driving circuit in a display panel according to an embodiment of the invention. Fig. 4 is a timing diagram corresponding to the pixel driving circuit in fig. 3. As shown in fig. 3, the pixel driving circuit further includes a second node N2, a third node N3, and a fourth node N4;
the initialization unit 13 includes a first transistor T1 and a second transistor T2, a control terminal of the first transistor T1 is electrically connected to a first control signal terminal C1, a first terminal of the first transistor T1 is electrically connected to a reset signal terminal S1, a second terminal of the first transistor T1 is electrically connected to a first node N1, a control terminal of the second transistor T2 is electrically connected to a fourth control signal terminal C4, a first terminal of the second transistor T2 is electrically connected to a reset signal terminal S1, and a second terminal of the second transistor T2 is electrically connected to a fourth node N4.
The data unit 12 includes a third transistor T3 and a fourth transistor T4, a control terminal of the third transistor T3 is electrically connected to the second control signal terminal C2, a first terminal of the third transistor T3 is electrically connected to the data signal terminal S3, a second terminal of the third transistor T3 is electrically connected to the second node N2, a control terminal of the fourth transistor T4 is electrically connected to the second control signal terminal C2, a first terminal of the fourth transistor T4 is electrically connected to the first node N1, and a second terminal of the fourth transistor T4 is electrically connected to the third node N3.
The light emission control unit 11 includes a fifth transistor T5, a sixth transistor T6, and a capacitor CQ, a control terminal of the fifth transistor T5 is electrically connected to a third control signal terminal C3, a first terminal of the fifth transistor T5 is electrically connected to a light emission signal terminal S2, a second terminal of the fifth transistor T5 is electrically connected to a second node N2, a control terminal of the sixth transistor T6 is electrically connected to a third control signal terminal C3, a first terminal of the sixth transistor T6 is electrically connected to a third node N3, a second terminal of the sixth transistor T6 is electrically connected to a fourth node N4, a first electrode of the capacitor CQ is electrically connected to the light emission signal terminal S2, and a second electrode of the capacitor CQ is electrically connected to the first node N1.
The driving unit 14 includes a seventh transistor T7, a control terminal of the seventh transistor T7 is electrically connected to the first node N1, a first terminal of the seventh transistor T7 is electrically connected to the second node N2, and a second terminal of the seventh transistor T7 is electrically connected to the third node N3.
The fourth node N4 is electrically connected to the anode of the light emitting diode LI.
In the pixel driving circuit, the two transistors of the initialization unit 13 are respectively connected to two control signal terminals, namely, the first control signal terminal C1 and the fourth control signal terminal C4, wherein the first control signal terminal C1 and the fourth control signal terminal C4 may provide the same signal or different signals, that is, the initialization unit may reset the plate of the light emitting diode and initialize the first node at the same time or at different times. Alternatively, the fourth control signal terminal C4 and the second control signal terminal C2 may provide the same signal, that is, the plate of the light emitting diode LI is reset at the same time during the data writing phase.
Refer to the timing diagram shown in fig. 4. The working phases of the pixel driving circuit can be divided into: an initialization phase t1, a data writing phase t2 and a pixel light emission phase t 3. At initialization stage t 1: the first control signal terminal C1 provides an active level signal at this stage, the first transistor T1 and the second transistor T2 are turned on (in case that the fourth control signal terminal C4 and the first control signal terminal C1 provide the same signal), the reset signal provided by the reset signal terminal S1 initializes the first node N, and the reset signal resets the fourth node N4. At the data writing stage t 2: the second control signal terminal C2 provides an active level signal, the third transistor T3 and the fourth transistor T4 are turned on, and the seventh transistor is also turned on, and transmits a data signal to the first node N1 through the data signal terminal S3, and charges the capacitor CQ. In the pixel lighting period t 3: the third control signal terminal C3 provides an active level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, the capacitor CQ is discharged, the seventh transistor T7 is turned on, and the light emitting signal terminal S2 transmits the light emitting signal to the fourth node N4.
In the schematic timing diagram of fig. 4, taking the reset signal terminal S1 providing an active low signal as an example, the reset signal terminal S1 is electrically connected to the reset trace. When the number of the electrically connected pixels in the reset traces is small, that is, the first reset trace of the present invention, because the number of the electrically connected pixels is small, the current lost when the first reset trace transmits a signal to the reset signal terminal to reset the fourth node is small, and the voltage drop generated on the first reset trace is small, the potential of the first node is lower after the first reset trace transmits a signal to the reset signal terminal to initialize the first node. According to the invention, the capacitance compensation structure is arranged, one first reset wire is electrically connected with at least one capacitance compensation structure, the capacitance compensation structure can increase the load on the first reset wire, and the loads on the first reset wire and the second reset wire are ensured to be approximately the same, so that the electric potential of a first node in a pixel driving circuit electrically connected with the first reset wire and the second reset wire is approximately the same, further the luminous brightness of pixels electrically connected with the first reset wire and the second reset wire is ensured to be approximately the same, the problem of uneven display is solved, and the display effect is improved.
In the embodiment of fig. 4, all the transistors in the pixel driving circuit are p-type transistors. Optionally, all the transistors in the pixel driving circuit may be n-type transistors, and at this time, the connection relationship of the transistors in the pixel driving circuit is not changed, and only the input signals of the control terminals need to be adaptively adjusted.
The display panel provided by the invention can be an organic light-emitting display panel, the display panel comprises a plurality of organic light-emitting diodes, one pixel comprises at least one organic light-emitting diode, a plurality of power lines are arranged in the display panel, the power lines provide light-emitting signals for the organic light-emitting diodes, constant voltage signals are generally introduced into the power lines, and the power lines comprise an anode power line and a cathode power line. In one implementation, fig. 5 is a schematic diagram of an alternative implementation of the display panel according to the embodiment of the present invention. Fig. 6 is a schematic diagram of a film layer of an alternative embodiment of a display panel according to an embodiment of the invention. As shown in fig. 5, the display panel includes a positive power line ZX, and the extending direction of the positive power line ZX intersects the extending direction of the reset trace FX. The capacitance compensation structure BC includes a first capacitance section BC1 and a second capacitance section BC2, where the first capacitance section BC1 and the second capacitance section BC2 have portions overlapping each other in an insulating manner, and a capacitance is formed in a region overlapping each other in an insulating manner. First reset trace FX1 is electrically connected to first capacitor BC 1. Optionally, the positive power supply line ZX is electrically connected to the second capacitor BC 2. In this embodiment, the capacitance compensation structure BC can increase the load on the first reset trace FX1, so that the load on the first reset trace FX1 is substantially the same as the load on the second reset trace FX2, thereby improving the problem of display non-uniformity. In general, as shown in fig. 5, the positive power line ZX is closer to the data line D in the display panel, a varying signal is transmitted on the data line D, and a signal jumping on the data line D may generate crosstalk with the adjacent positive power line ZX. In the invention, the capacitance compensation structure BC can also increase the capacitance load on the positive power line ZX, thereby ensuring that the signal on the positive power line ZX is more stable, avoiding the interference of the signal on the data line D on the positive power line ZX, and ensuring the performance reliability of the display panel.
With continued reference to fig. 6, the display panel includes an array substrate 101, the array substrate 101 includes a plurality of thin film transistors T, and various traces in the display panel are also located in the array substrate 101. The thin film transistor T includes an active layer T1, a gate electrode T2, a source electrode T3, and a drain electrode T4, fig. 6 is only schematically illustrated as a top gate structure, and the thin film transistor in the display panel provided by the present invention may also be a bottom gate structure. In general, the positive power line ZX in the display panel is fabricated in the same layer as the source T3 and the drain T4 of the tft T, the reset trace is typically fabricated on a capacitor metal layer, and the capacitor metal layer is used to fabricate one plate of the pixel capacitor, so the first reset trace FX1 is located on the capacitor metal layer. In the present invention, the first reset trace FX1 is electrically connected to the first capacitor portion BC1, and the positive power line ZX can be electrically connected to the second capacitor portion BC2 (the position of the electrical connection is not shown). Fig. 6 shows a case where the first capacitor BC1 and the first reset wiring are fabricated in the same layer, and the second capacitor BC2 and the positive power supply line ZX are fabricated in the same layer. The embodiment can manufacture the capacitance compensation structure without adding a new process, realizes the compensation of the capacitance load of the first reset wire, and is simple and easy to implement.
Optionally, the first capacitor portion and the first reset trace may be disposed in different layers, and the first capacitor portion may reuse an original film layer in the display panel during manufacturing, or add a new film layer to manufacture the first capacitor portion, and then electrically connect the first capacitor portion and the first reset trace through a process of manufacturing a via hole. The same second capacitor part and the positive power line can also be arranged in different layers, the second capacitor part can also multiplex the original film layer in the display panel during manufacturing, or a new film layer is added to manufacture the second capacitor part, and then the second capacitor part and the positive power line are electrically connected through a process of manufacturing a through hole.
Fig. 7 is a schematic diagram of another alternative implementation of the display panel according to the embodiment of the present invention. As shown in fig. 7, the non-display area BA includes a display gap area BA1, the display area AA further includes a third display area AA3, the reset trace FX includes a third reset trace FX3, and the third reset trace FX3 is located in the third display area AA 3; the number of pixels sp electrically connected with one third reset trace FX3 is c, wherein c is an integer and 0 < c < b, that is, the number of pixels sp electrically connected with one third reset trace FX3 is smaller than the number of pixels sp electrically connected with one second reset trace FX 2; a third reset trace FX3 is electrically connected to at least one capacitance compensation structure BC; in the first direction e, the first display area AA1 and the third display area AA3 are respectively located at both sides of the display notch area BA 1; the second display area AA2 is adjacent to the first display area AA1, the display cutout area BA1 and the third display area AA3, respectively, in the second direction f, and the first direction e intersects the second direction f.
It should be noted that various parameters (size, number of pixels, etc.) in the first display area AA1 and the third display area AA3 located at both sides of the display cutout area BA1 may be identical, or various parameters in the first display area AA1 and the third display area AA3 may be different.
In the embodiment corresponding to fig. 7, the gap area BA1 may be formed by cutting off each film layer of the display panel, so that a gap is formed at the position, or the display panel may be formed only at the position without providing pixels, but various substrate supporting structures of the display panel still remain.
In this embodiment, the first display area and the second display area are respectively located at two sides of the display notch area, and the capacitance compensation structure can increase the load on the first reset wire by arranging the first reset wire to be electrically connected with the at least one capacitance compensation structure. Set up the third and reset to walk line and at least one capacitance compensation structure electricity and be connected, capacitance compensation structure can increase the third and reset to walk the load on the line to guarantee that the load on the line is walked to first resetting and the third resets and walk the load on the line all with the second and reset and walk the load on the line roughly the same, guarantee promptly that each resets in the display area and walk the load on the line roughly the same, thereby guarantee that the luminance of each pixel in the display area is roughly the same, improve and show the inequality problem.
In some optional embodiments, the display panel provided by the invention further includes a reset trace connection portion, and the reset trace connection portion is located in the display notch area; the first reset wire is electrically connected with the at least one third reset wire through the reset wire connecting part. That is, one first reset wire can be connected with one third reset wire through the reset wire connecting part, or one first reset wire can be connected with two or more third reset wires through the reset wire connecting part. The first reset wire routing part and the third reset wire routing part which are connected together can be electrically connected with the same capacitance compensation structure to compensate the capacitance, so that the number of the capacitance compensation structures is saved, and the space occupied by the capacitance compensation structure in the display panel is saved.
In one embodiment, only one first reset trace is connected to one third reset trace through a reset trace connection, which is schematically represented. Fig. 8 is a partial schematic view of another alternative embodiment of a display panel according to an embodiment of the present invention. In fig. 8, pixels are not shown in the display area, and only reset traces are shown for clarity of illustrating the connection relationship between the traces in the display panel. As shown in fig. 8, the display panel further includes: the reset trace connection portion FXL is located in the display notch area BA 1; a first reset trace FX1 and a third reset trace FX3 are electrically connected by reset trace connection FXL. Optionally, when the number of the first reset traces FX1 in the display panel is the same as that of the third reset traces FX3, the first reset traces FX1 and the third reset traces FX3 in the same row in the display panel are electrically connected in a one-to-one correspondence manner, and the wiring of the connection method is relatively simple. In this embodiment, the resistance of the reset trace connection FXL itself can act as a load, increasing the load on the first reset trace FX1 and the third reset trace FX3 to some extent, but the resistance of the reset trace connection FXL alone is still insufficient as load compensation, and there are still load differences between the first reset trace FX1 and the second reset trace FX2 and between the third reset trace FX3 and the second reset trace FX2, and it is still necessary to provide a capacitive compensation structure in the display panel.
The position of the capacitance compensation structure is not shown in fig. 8, and optionally, in this kind of display panel, the reset trace connection portion FXL may serve as a first capacitance portion of the capacitance compensation structure, and the second capacitance portion and the reset trace connection portion FXL are arranged to be overlapped in an insulating manner to form a capacitance, so that the load on the first reset trace and the third reset trace is increased. Optionally, the function of the reset trace connection portion FXL is only to achieve electrical connection between the first reset trace and the third reset trace, and then a capacitance compensation structure is disposed in the display panel to be electrically connected with the first reset trace and the second reset trace.
In an embodiment, fig. 9 is a partial schematic view of another alternative implementation of a display panel according to an embodiment of the present disclosure. As shown in fig. 9, all the reset traces that need to be capacitance compensated in the whole display panel are electrically connected together. That is, first reset trace FX1 and third reset trace FX3 are both connected together by reset trace connection FXL. In this case, all the first reset trace FX1 and the third reset trace FX3 in the display panel can perform capacitance compensation on both the first reset trace and the third reset trace through the same capacitance compensation structure BC, so that the load is increased. The position of the capacitance compensation structure BC in fig. 9 is only schematically shown, and is not a limitation to the present invention.
In some optional embodiments, at least two first reset traces located in the same first display area are electrically connected to each other through the reset trace portion, and/or at least two third reset traces located in the same third display area are electrically connected to each other through the reset trace portion. The multiple reset wires which need to be subjected to capacitance compensation in the same display area are electrically connected with each other to be subjected to compensation through the same capacitance compensation structure, the number of the capacitor compensation structures is saved, and the space occupied by the capacitor compensation structures in the display panel is saved. In the following, it is illustrated that all reset traces located in the same display area and requiring capacitance compensation are electrically connected together.
In an embodiment, fig. 10 is a partial schematic view of another alternative implementation of a display panel according to an embodiment of the present invention. As shown in fig. 10, the display panel further includes a reset trace connection portion FXL, where the reset trace connection portion FXL is located in the display notch area BA 1; the first reset traces FX1 in the same first display area AA1 are electrically connected to each other through the reset trace connection FXL, and the third reset traces FX3 in the same third display area AA3 are electrically connected to each other through the reset trace connection FXL.
In some embodiments, the display notch area is provided with an optical module installation area, and the optical module installation area may be provided in any of the embodiments corresponding to fig. 8 to 10. The following description will be made only by taking the example of setting the optical module setting area in the embodiment corresponding to fig. 8 as an example.
Fig. 11 is a partial schematic view of another alternative implementation of the display panel according to the embodiment of the present invention. As shown in fig. 11, the display notch area BA1 includes an optical module disposing area Q, and the reset trace connection portion FXL and the optical module disposing area Q overlap each other in a direction perpendicular to a plane of the display panel; reset and walk line connecting portion FXL and include transparent material, for example can set up the camera in optical module sets up district Q. In this embodiment, line connecting portion FXL resets includes transparent material, then light penetrates to reset and is walked light loss very little when line connecting portion FXL resets, can ignore basically, and line connecting portion FXL and optical module set up district Q overlap each other resets, and line connecting portion FXL resets and can not influence the optical module in optical module set up district Q and receive light. Optionally, the transparent material comprises an indium gallium zinc oxide material.
In some embodiments, in a direction perpendicular to a plane of the display panel, the capacitance compensation structure and the optical module arrangement region overlap each other; the capacitance compensation structure includes a transparent material. In the embodiments corresponding to fig. 8 to 10, the capacitance compensation structure and the optical module installation region may be overlapped with each other. The following description will be made only by taking the embodiment corresponding to fig. 8 as an example.
Fig. 12 is a partial schematic view of another alternative embodiment of a display panel according to an embodiment of the present invention. As shown in fig. 12, the display panel further includes: the reset trace connection portion FXL is located in the display notch area BA 1; a first reset trace FX1 and a third reset trace FX3 are electrically connected by reset trace connection FXL. In the direction perpendicular to the plane of the display panel, the capacitance compensation structure BC and the optical module setting area Q are mutually overlapped; the capacitance compensation structure BC comprises a transparent material. In this embodiment, the reset trace connection portion FXL may serve as the first capacitor portion of the capacitance compensation structure BC, and then the second capacitor portion is disposed to overlap with the reset trace connection portion FXL to form a capacitor. The first capacitor part and the second capacitor part are both made of transparent materials. The arrangement of the capacitance compensation structure and the mutual overlapping of the optical module arrangement area can realize load compensation of the first reset wiring and the third reset wiring, and is favorable for saving space in the display panel. And the capacitance compensation structure comprises a transparent material, so that light loss is very small after light penetrates through the capacitance compensation structure and can be basically ignored, the capacitance compensation structure and the optical module setting area are mutually overlapped, and the setting of the capacitance compensation structure cannot influence the optical module in the optical module setting area to receive light.
In the above embodiments of the present invention, the notch areas are schematically shown in a rectangular shape, and the present invention is not limited thereto. The shape of the display gap region may also be circular, oval, trapezoidal, triangular, or the like.
Fig. 13 is a schematic view of a display device according to an embodiment of the present invention. As shown in fig. 13, the display device includes a display panel 100 provided in any embodiment of the present invention. The display device provided by the embodiment of the invention can be any electronic product with a flexible display function, including but not limited to the following categories: the mobile terminal comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, a mobile phone, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
according to the display panel provided by the invention, the capacitance compensation structure is arranged in the display panel, one first reset wire is electrically connected with at least one capacitance compensation structure, the capacitance compensation structure can increase the load on the first reset wire to compensate the load difference caused by different numbers of electrically connected pixels, and the loads on the first reset wire and the second reset wire are ensured to be approximately the same, so that the electric potentials of the light-emitting control nodes in the pixel driving circuits respectively electrically connected with the first reset wire and the second reset wire are approximately the same, further the light-emitting brightness of the pixels respectively electrically connected with the first reset wire and the second reset wire is ensured to be approximately the same, the problem of uneven display is solved, and the display effect is improved.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. A display panel, comprising:
a display area and a non-display area surrounding the display area, the display area including a first display area and a second display area;
the display panel comprises a plurality of reset wires and a plurality of pixels, wherein the reset wires comprise a first reset wire and a second reset wire, the first reset wire is positioned in the first display area, and the second reset wire is positioned in the second display area; the number of the pixels electrically connected with one first reset wire is a, the number of the pixels electrically connected with one second reset wire is b, wherein a and b are integers, and a is more than 0 and less than b;
and one first reset routing is electrically connected with at least one capacitance compensation structure.
2. The display panel according to claim 1,
the display panel further includes a pixel driving circuit including: the device comprises a light-emitting control unit, a data unit, an initialization unit, a driving unit and a first node; wherein,
the initialization unit, the driving unit and the data unit are all connected to the first node;
the initialization unit is used for initializing the first node based on the received reset signal and resetting the pixel;
the light-emitting control unit is used for transmitting the received light-emitting signal to the pixel and controlling the pixel to emit light;
the data unit is used for transmitting the received data signal to the first node;
and the driving unit is used for controlling the driving unit to be turned on according to the potential of the first node so as to transmit the light-emitting signal to the pixel.
3. The display panel according to claim 2,
the pixel driving circuit further comprises a second node, a third node and a fourth node;
the initialization unit comprises a first transistor and a second transistor, wherein the control end of the first transistor is electrically connected with a first control signal end, the first end of the first transistor is electrically connected with a reset signal end, the second end of the first transistor is electrically connected with the first node, the control end of the second transistor is electrically connected with a fourth control signal end, the first end of the second transistor is electrically connected with the reset signal end, and the second end of the second transistor is electrically connected with the fourth node;
the data unit comprises a third transistor and a fourth transistor, wherein the control end of the third transistor is electrically connected with a second control signal end, the first end of the third transistor is electrically connected with a data signal end, the second end of the third transistor is electrically connected with the second node, the control end of the fourth transistor is electrically connected with the second control signal end, the first end of the fourth transistor is electrically connected with the first node, and the second end of the fourth transistor is electrically connected with the third node;
the light-emitting control unit comprises a fifth transistor, a sixth transistor and a capacitor, wherein the control end of the fifth transistor is electrically connected with a third control signal end, the first end of the fifth transistor is electrically connected with a light-emitting signal end, the second end of the fifth transistor is electrically connected with the second node, the control end of the sixth transistor is electrically connected with the third control signal end, the first end of the sixth transistor is electrically connected with the third node, the second end of the sixth transistor is electrically connected with the fourth node, the first electrode of the capacitor is electrically connected with the light-emitting signal end, and the second electrode of the capacitor is electrically connected with the first node;
the driving unit comprises a seventh transistor, a control end of the seventh transistor is electrically connected with the first node, a first end of the seventh transistor is electrically connected with the second node, and a second end of the seventh transistor is electrically connected with the third node;
the fourth node is electrically connected with the anode of the light emitting diode.
4. The display panel according to claim 1,
the non-display area comprises a display gap area, the display area further comprises a third display area, the reset wiring comprises a third reset wiring, and the third reset wiring is located in the third display area;
the number of the pixels electrically connected with one third reset wire is c, wherein c is an integer and c is more than 0 and less than b; one third reset trace is electrically connected with at least one capacitance compensation structure;
in a first direction, the first display area and the third display area are respectively located at both sides of the display notch area; in a second direction, the second display area is adjacent to the first display area, the display notch area, and the third display area, respectively, and the first direction crosses the second direction.
5. The display panel according to claim 4, further comprising:
the reset wiring connecting part is positioned in the display notch area;
one of the first reset traces is electrically connected to at least one of the third reset traces through the reset trace connection portion.
6. The display panel according to claim 4, further comprising:
the reset wiring connecting part is positioned in the display notch area;
the at least two first reset wires positioned in the same first display area are electrically connected with each other through the reset wire connecting part, and/or the at least two third reset wires positioned in the same third display area are electrically connected with each other through the reset wire connecting part.
7. The display panel of claim 5, wherein the display notch area includes an optical module disposing area, and the reset trace connection portion and the optical module disposing area overlap each other in a direction perpendicular to a plane of the display panel;
the reset wire connecting part comprises a transparent material.
8. The display panel according to claim 7, wherein the capacitance compensation structure and the optical module disposing region overlap each other in a direction perpendicular to a plane of the display panel;
the capacitance compensation structure includes a transparent material.
9. The display panel according to claim 1,
the capacitance compensation structure comprises a first capacitance part and a second capacitance part, wherein the first reset routing is electrically connected with the first capacitance part;
the display panel further comprises a power line, the power line comprises an anode power line, and the anode power line is electrically connected with the second capacitor portion.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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