CN111724743A

CN111724743A - Pixel driving circuit, driving method thereof and display device

Info

Publication number: CN111724743A
Application number: CN202010707596.4A
Authority: CN
Inventors: 杨波; 田学伟; 方飞; 曾科文; 何祥飞; 王亚明; 王玲玲
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-07-21
Filing date: 2020-07-21
Publication date: 2020-09-29

Abstract

The disclosure provides a pixel driving circuit, a driving method thereof and a display device, relates to the technical field of display, and can improve the brightness uniformity of each light-emitting device. The pixel driving circuit comprises an input sub-circuit, a charging control sub-circuit, a driving sub-circuit, a light-emitting control sub-circuit, a resetting sub-circuit, a first energy storage sub-circuit and a second energy storage sub-circuit. The input sub-circuit is coupled with the grid scanning signal end, the data signal end and the first node; the charging control sub-circuit is coupled with the charging control signal terminal, the first power supply voltage signal terminal and the second node; the driving sub-circuit is coupled with the first node, the second node and the light-emitting control sub-circuit; the light-emitting control sub-circuit is coupled with the light-emitting scanning signal terminal and the light-emitting device; the reset sub-circuit is coupled with the grid scanning signal end, the reset signal end and the light-emitting device; the first tank sub-circuit is coupled with the first node and the second node; the second tank sub-circuit is coupled to the second node and the reset signal terminal. The pixel driving circuit is applied to a display device.

Description

Pixel driving circuit, driving method thereof and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a display device.

Background

At present, an OLED (Organic Light-Emitting Diode) display device has become one of the mainstream display fields due to its characteristics of self-luminescence, low driving power consumption, high Light-Emitting conversion efficiency, short response time, low cost, and the like.

The OLED display device includes a plurality of sub-pixels, each of which includes a pixel driving circuit and a light emitting device, and the light emitting device is driven by the pixel driving circuit to emit light, thereby implementing display.

Disclosure of Invention

It is an object of some embodiments of the present disclosure to provide a pixel driving circuit, a driving method thereof, and a display device, which can improve uniformity of light emission luminance of each light emitting device.

In order to achieve the above purpose, some embodiments of the present disclosure provide the following technical solutions:

in a first aspect, a pixel driving circuit is provided. The pixel driving circuit comprises an input sub-circuit, a charging control sub-circuit, a driving sub-circuit, a light-emitting control sub-circuit, a resetting sub-circuit, a first energy storage sub-circuit and a second energy storage sub-circuit.

The reset sub-circuit is coupled with the grid scanning signal end, the reset signal end and the light-emitting device. The reset sub-circuit is configured to transmit a reset signal received at the reset signal terminal to the light emitting device to reset the light emitting device in response to a gate scan signal received at the gate scan signal terminal.

The input sub-circuit is coupled to the gate scan signal terminal, the data signal terminal, and the first node. The input sub-circuit is configured to transmit a data signal received at the data signal terminal to the first node under control of the gate scan signal.

The charging control sub-circuit is coupled to the charging control signal terminal, the first power voltage signal terminal, and the second node. The charge control subcircuit is configured to transmit a first supply voltage signal received at the first supply voltage signal terminal to the second node in response to a charge control signal received at the charge control signal terminal.

The first tank subcircuit is coupled with the first node and the second node. The first tank subcircuit is configured to be charged according to voltages of the first node and the second node. And enabling the voltage of the second node to jump under the action of the voltage of the first node under the condition that the first tank sub-circuit and the second tank sub-circuit form a series relation.

The second tank sub-circuit is coupled to the second node and the reset signal terminal. The second tank sub-circuit is configured to charge in accordance with a voltage of the second node and a reset signal received at the reset signal terminal.

The driving sub-circuit is coupled with the first node, the second node and the light emission control sub-circuit. The driving sub-circuit is configured to form a path in cooperation with the light-emitting control sub-circuit and the reset sub-circuit under the control of the voltage of the first node, so that the threshold voltage of the driving transistor in the driving sub-circuit is written into the first energy storage sub-circuit.

The light-emitting control sub-circuit is also coupled with a light-emitting scanning signal terminal and the light-emitting device. The light emission control sub-circuit is configured to form a path in cooperation with the charging control sub-circuit and the driving sub-circuit in response to a light emission scan signal received at the light emission scan signal terminal, and transmit the first power supply voltage signal to the light emitting device to drive the light emitting device to emit light.

In the pixel driving circuit provided by the embodiment of the disclosure, the driving sub-circuit, the light-emitting control sub-circuit and the reset sub-circuit are turned on, and the driving sub-circuit, the light-emitting control sub-circuit and the reset sub-circuit are matched to form a passage, so that a conductive path from the second node to the reset signal end is conducted, and the voltage of the second node is changed under the action of the voltage of the reset signal end until the driving sub-circuit is turned off, so that the threshold voltage of the driving transistor in the driving sub-circuit is written into the first energy storage sub-circuit. In the light-emitting stage, the driving transistor is turned on by utilizing the discharging action of the first energy storage sub-circuit, so that the influence of the threshold voltage of the driving transistor on the current flowing through the light-emitting device can be eliminated, and the problem of nonuniform light-emitting brightness of different light-emitting devices caused by threshold voltage offset is avoided.

And the first energy storage sub-circuit is connected with the second energy storage sub-circuit in series by turning off the charging control sub-circuit, the driving sub-circuit and the light-emitting control sub-circuit. The input sub-circuit transmits a data signal having a second voltage to the first node, causing the voltage at the first node to jump from the first voltage to the second voltage. According to the principle of series voltage division of the capacitors, the voltage of the first node jumps, so that the voltage of the second node jumps, and the compensation of the first power supply voltage signal transmitted to the second node is realized. In the light-emitting stage, the influence of the first power supply voltage signal on the current passing through the light-emitting device can be eliminated, and the problem of non-uniform light-emitting brightness of different light-emitting devices caused by attenuation of the first power supply voltage signal in the transmission process of a corresponding signal wire (namely the first power supply voltage signal wire) is avoided.

In summary, the pixel driving circuit can improve the uniformity of the luminance of each light emitting device in the display device, and is beneficial to improving the uniformity of the screen luminance of the display device.

In some embodiments, the input sub-circuit comprises a first transistor. A control electrode of the first transistor is coupled to the gate scan signal terminal, a first electrode of the first transistor is coupled to the data signal terminal, and a second electrode of the first transistor is coupled to the first node.

In some embodiments, the charge control sub-circuit comprises a second transistor. A control electrode of the second transistor is coupled to the charge control signal terminal, a first electrode of the second transistor is coupled to the first power voltage signal terminal, and a second electrode of the second transistor is coupled to the second node.

In some embodiments, the driving sub-circuit comprises a third transistor. A control electrode of the third transistor is coupled to the first node, a first electrode of the third transistor is coupled to the second node, and a second electrode of the third transistor is coupled to the light emission control sub-circuit.

In some embodiments, the emission control sub-circuit includes a fourth transistor. A control electrode of the fourth transistor is coupled to the light emitting scan signal terminal, a first electrode of the fourth transistor is coupled to the driving sub-circuit, and a second electrode of the fourth transistor is coupled to the light emitting device.

In some embodiments, the reset sub-circuit includes a fifth transistor; a control electrode of the fifth transistor is coupled to the gate scan signal terminal, a first electrode of the fifth transistor is coupled to the reset signal terminal, and a second electrode of the fifth transistor is coupled to the light emitting device.

In some embodiments, the first tank sub-circuit comprises a first capacitor. A first terminal of the first capacitor is coupled to the first node and a second terminal of the first capacitor is coupled to the second node. The second tank sub-circuit comprises a second capacitor. A first terminal of the second capacitor is coupled to the reset signal terminal, and a second terminal of the second capacitor is coupled to the second node.

In some embodiments, the light emitting device is further coupled to a second power supply voltage signal terminal. The voltage of the reset signal transmitted by the reset signal end is less than the voltage of the second power supply voltage signal transmitted by the second power supply voltage signal end.

In a second aspect, a driving method of a pixel driving circuit is provided, and the driving method of the pixel driving circuit is applied to the pixel driving circuit described in the first aspect. The driving method includes: one frame period includes a reset phase, a threshold voltage compensation phase, a power supply voltage compensation phase, and a light emitting phase.

In the reset phase: the input sub-circuit transmits a data signal having a first voltage received at the data signal terminal to the first node. The charge control subcircuit transmits a first supply voltage signal received at the first supply voltage signal terminal to the second node. The reset sub-circuit transmits a reset signal received at the reset signal terminal to the light emitting device to reset the light emitting device. Under the action of the voltages of the first node and the second node, the first energy storage sub-circuit is charged. And under the action of the voltage of the reset signal end and the voltage of the second node, the second energy storage sub-circuit is charged.

During the threshold voltage compensation phase: the input sub-circuit transmits the data signal having the first voltage to the first node. The driving sub-circuit, the light-emitting control sub-circuit and the reset sub-circuit are opened and matched to form a passage, so that the voltage of the second node is changed under the action of the voltage of the reset signal end, and the threshold voltage of the driving sub-circuit is written into the first energy storage sub-circuit.

During the supply voltage compensation phase: the input sub-circuit transmits a data signal having a second voltage received at the data signal terminal to the first node. And the charging control sub-circuit and the light-emitting control sub-circuit are closed, so that the first energy storage sub-circuit and the second energy storage sub-circuit are connected in series, and the voltage of the second node jumps.

In the light emitting stage: the charge control subcircuit transmits the first power supply voltage signal to the second node. The first tank sub-circuit couples the voltage of the first node according to the voltage of the second node to change the voltage of the first node. The driving sub-circuit transmits a first power voltage signal transmitted to the second node to the light emission control sub-circuit. The light emitting control sub-circuit transmits the first power voltage signal to the light emitting device to drive the light emitting device to emit light.

The beneficial effects that can be achieved by the driving method of the pixel driving circuit provided by the embodiment of the disclosure are the same as those that can be achieved by the pixel driving circuit provided by the first aspect, and are not described herein again.

In a third aspect, there is provided a display device comprising a plurality of pixel driving circuits as described in the first aspect.

The beneficial effects that can be achieved by the display device provided by the embodiment of the present disclosure are the same as those that can be achieved by the pixel driving circuit provided by the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display device according to some embodiments of the present disclosure;

FIG. 2 is a diagram of a pixel driving architecture of a display device according to some embodiments of the present disclosure;

FIG. 3 is a block diagram of a pixel driving circuit according to some embodiments of the present disclosure;

FIG. 4 is a block diagram of another pixel driving circuit according to some embodiments of the present disclosure;

FIG. 5 is a timing diagram of a pixel driving circuit according to some embodiments of the present disclosure;

6-9 are diagrams of operating states of pixel driving circuits at different timing stages according to some embodiments of the present disclosure;

FIG. 10 is a graph of voltage or current changes at different timing stages for some nodes and film layers of a pixel driving circuit according to some embodiments of the present disclosure;

fig. 11 to 14 are top views of some film layers in an array substrate according to some embodiments of the present disclosure;

FIG. 15 is a cross-sectional view of a display device according to some embodiments of the present disclosure;

fig. 16 is a schematic view illustrating a test of a display device according to the related art;

FIG. 17 is a graph showing the relationship between the distance from each point in the display area to the driving circuit board and the light emitting brightness in FIG. 16.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Some embodiments of the present disclosure provide a display device. The display device may be, for example, a mobile phone, a tablet computer, a Personal Digital Assistant (PDA), an in-vehicle computer, a wearable display device, or the like. The embodiment of the present disclosure does not particularly limit the specific form of the display device.

As shown in fig. 1 and 2, the display device 01 includes a display Area AA (Active Area, AA Area for short; also called as effective display Area) and a peripheral Area BB disposed on at least one side of the display Area AA.

In the display area AA, a plurality of sub pixels 10, a plurality of gate scanning signal lines gl (gate line) extending in the horizontal direction X, and a plurality of data signal lines dl (data line) extending in the vertical direction Y are provided. For convenience of explanation, the plurality of sub-pixels 10 are described as an example of a matrix arrangement in the present disclosure. At this time, the sub-pixels 10 arranged in a row in the horizontal direction X are referred to as a row of sub-pixels, the sub-pixels 10 arranged in a row in the vertical direction Y are referred to as a column of sub-pixels, a row of sub-pixels may be coupled to one gate scanning signal line GL, and a column of sub-pixels may be coupled to one data signal line DL.

As shown in fig. 2, taking the display device 01 as an active light emitting display device (e.g., an OLED display device) as an example, each sub-pixel 10 includes a pixel driving circuit 100 and a light emitting device D, the pixel driving circuit 100 is coupled to the light emitting device D, and the pixel driving circuit 100 is further coupled to a gate scanning signal line GL and a data signal line DL. The pixel driving circuit 100 transmits the data signal transmitted from the data signal line DL to the light emitting device D under the control of the gate scan signal transmitted from the gate scan signal line GL, thereby driving the light emitting device D to emit light.

In the related art, a power supply voltage signal required for a pixel driving circuit of each sub-pixel in a display device is transmitted through a power supply voltage signal line arranged in a display panel of the display device. For example, the display panel includes a plurality of power voltage signal lines extending in a column direction, and the pixel driving circuit of each column of sub-pixels is coupled to one of the power voltage signal lines. One side of the display panel is provided with a driving circuit board which is coupled with a plurality of power voltage signal wires and can supply power voltage signals to the power voltage signal wires.

However, since the driving circuit board is disposed at one side of the display panel, there is a case where the power supply voltage signal is attenuated during transmission on the power supply voltage signal line, and the more the power supply voltage signal is attenuated as the transmission distance (i.e., the distance from the position point on the power supply voltage signal line to the driving circuit board) increases; namely, the signal attenuation of the position closest to the driving circuit board is minimum, and the signal attenuation of the position farthest from the driving circuit board is maximum. This causes a difference in power supply voltage signals supplied to the pixel driving circuits of each sub-pixel in the same column, which causes a difference in light emission luminance of the light emitting devices coupled to the pixel driving circuits, thereby causing a problem of non-uniformity (mura) in light emission luminance of the display device.

Referring to the following test, as shown in fig. 16, the display device 01 'includes a display panel 02' and a driving Circuit board 03 ', also called an Integrated Circuit (IC), located at one side of the display panel 02', and nine test points are selected from a display area AA 'of the display panel 01', and for example, the nine test points may be arranged in a rectangular array to respectively detect the light emitting brightness of each test point. Referring to fig. 17, the abscissa in fig. 17 represents the distance between the test point and the driving circuit board 03', and the ordinate represents the light emission luminance. The luminance of a point closer to the driving circuit board 03 'in the column direction Y of the display area AA' is higher than that of a point farther from the driving circuit board 03 ', that is, the luminance of a region farther from the driving circuit board 03' in the display area AA 'in the column direction Y of the display area AA' is lower. For example, in the same column direction Y, the distances of the

dots

1, 2, and 3 from the driving circuit board 03' gradually increase, and the light emission luminances of the

dots

1, 2, and 3 gradually decrease; for another example, along the same column direction Y, the distances from the driving circuit board 03' to the

points

4, 5, and 6 gradually increase, and the light-emitting luminances of the

points

4, 5, and 6 gradually decrease; as another example, in the same column direction Y, the distances of the

dots

7, 8, and 9 from the drive circuit board 03' gradually increase, and the light emission luminances of the

dots

7, 8, and 9 gradually decrease.

In addition, in the related art, the pixel driving circuit includes a driving transistor for driving the light emitting device to emit light, which may cause a threshold voltage of the driving transistor to shift due to an unstable manufacturing process of the driving transistor, and the shift amount of the threshold voltage of the driving transistor in different sub-pixels is different, which may eventually cause a problem that a screen of the display apparatus has uneven light emitting brightness.

To solve the above problem, as shown in fig. 3, some embodiments of the present disclosure provide a pixel driving circuit 100, where the pixel driving circuit 100 includes: an input sub-circuit 101, a charging control sub-circuit 102, a driving sub-circuit 103, a light emission control sub-circuit 104, a reset sub-circuit 105, a first tank sub-circuit 106 and a second tank sub-circuit 107.

The input sub-circuit 101, the Gate signal terminal Gate, the Data signal terminal Data, and the first node N₁And (4) coupling. The input sub-circuit 101 is configured to transmit a Data signal received at the Data signal terminal Data to the first node N in response to a Gate scan signal received at the Gate scan signal terminal Gate₁。

Note that the display device 01 is provided with gate scanning signal lines GL for transmitting gate scanning signals, and data signal lines DL for transmitting data signals. Based on this, the Gate scanning signal terminal Gate in the pixel driving circuit 100 is coupled to the Gate scanning signal line GL to receive the Gate scanning signal; the Data signal terminal Data is coupled to the Data signal line DL for receiving a Data signal.

Charging control sub-circuit 102, charging control signal terminal Con, first power voltage signal terminal VDD and second node N₂And (4) coupling. The charge control sub-circuit 102 is configured to transmit the first supply voltage signal received at the first supply voltage signal terminal VDD to the second node N in response to the charge control signal received at the charge control signal terminal Con₂。

It should be noted that, the display device 01 is provided with a charging control signal line for transmitting a charging control signal, and the charging control signal terminal Con is coupled to the charging control signal line for receiving the charging control signal.

The "first power supply voltage signal terminal VDD" is configured to transmit a direct current level signal. The first power voltage signal terminal VDD may be coupled to a VDD line (a first power voltage signal line) for transmitting a first power voltage signal in the display device 01 to receive the first power voltage signal. The first power supply voltage signal may be a dc high level signal or a dc low level signal. In the case where the pixel driving circuit 100 is coupled to the anode of the light emitting device D, the first power voltage signal is a dc high level signal, i.e., the "first power voltage signal terminal VDD" is configured to transmit the dc high level signal.

The driving sub-circuit 103 and the first node N₁A second node N₂And a light emission control sub-circuit 104. The driving sub-circuit 103 is configured to be at a first node N₁Is controlled by the voltage of the driving transistor in the driving sub-circuit 103, and the light emission control sub-circuit 104 and the reset sub-circuit 105 cooperate to form a path for the threshold voltage V of the driving transistor_thWriting to the first tank sub-circuit 106.

The emission control sub-circuit 104 further has an emission scan signal terminal EM and a third node N₃Is coupled, and the third node N₃The light emitting device D is coupled, that is, the light emission control sub-circuit 104 is also coupled to the light emission scan signal terminal EM and the light emitting device D. The light emission control sub-circuit 104 is configured to form a path in cooperation with the charging control sub-circuit 102 and the driving sub-circuit 103 in response to the light emission scan signal received at the light emission scan signal terminal EM, and transmit the first power voltage signal from the first power voltage signal terminal VDD to the light emitting device D to drive the light emitting device D to emit light.

The display device 01 is provided with a light-emission scanning signal line EL for transmitting a light-emission scanning signal. The emission scan signal terminal EM is coupled to the emission scan signal line EL to receive an emission scan signal.

In some embodiments, the light emission control sub-circuit 104 is coupled to an anode of the light emitting device D, in which case a cathode of the light emitting device D is coupled to the second power supply voltage signal terminal VSS. The second power voltage signal terminal VSS is configured to transmit a second power voltage signal to the light emitting device D.

Note that the "second power supply voltage signal terminal VSS" is configured to transmit a dc level signal. The second power voltage signal terminal VSS may be coupled to a VSS line (a second power voltage signal line) of the display device 01 for transmitting a second power voltage signal, so as to receive the second power voltage signal. The second power supply voltage signal may be a dc high level signal or a dc low level signal. In the case where the second power voltage signal terminal VSS is coupled to the cathode of the light emitting device D, the first power voltage signal is a dc low level signal, i.e., "the second power voltage signal terminal VSS" is configured to transmit the dc low level signal.

Reset sub-circuit 105, Gate of Gate scanning signal terminal, and third node N₃And a fourth node N₄And (4) coupling. Fourth node N₄And also to a reset signal terminal Sus, i.e., the reset sub-circuit 105 is coupled to the Gate scan signal terminal Gate, the light emitting device D, and the reset signal terminal Sus. The reset sub-circuit 105 is configured to transmit a reset signal received at a reset signal terminal Sus to the light emitting device D in response to a Gate scan signal received at a Gate scan signal terminal Gate to reset the light emitting device D.

The display device 01 is provided with a reset signal line for transmitting a reset signal. The reset signal terminal Sus is coupled to the reset signal line to receive a reset signal.

Illustratively, in a case where the reset sub-circuit 105 is coupled to the anode of the light emitting device D, the cathode of the light emitting device D is coupled to the second power voltage signal terminal VSS, and the second power voltage signal transmitted by the second power voltage signal terminal VSS is a dc low-level signal, the reset signal transmitted by the reset signal terminal Sus is a low-level signal. Further, the voltage value of the reset signal may be smaller than the voltage value of the second power voltage signal, so that in the reset phase P1, the reset signal not only can eliminate the residual positive charges on the anode of the light emitting device, but also because the voltage of the reset signal is smaller than the voltage of the second power voltage signal, the light emitting device D is not turned on in other phases except the light emitting phase in the frame period, thereby avoiding affecting the display effect of the display apparatus.

First tank sub-circuit 106 and first node N₁And a second node N₂And (4) coupling. The first tank subcircuit 106 is configured to operate according to a first node N₁And a second node N₂Charging the voltage of (a); and, in the case where the first tank sub-circuit 106 and the second tank sub-circuit 107 form a series relationship, at the first node N₁Under the action of the voltage of (2), the second node N is enabled₂The voltage of (2) jumps.

Second tank sub-circuit 107 and second node N₂And a fourth node N₄Coupled, i.e. the second tank sub-circuit 107 and the second node N₂And a reset signal terminal Sus. The second tank sub-circuit 107 is configured to operate according to a second node N₂And a reset signal received at a reset signal terminal Sus.

The pixel driving circuit 100 provided by the present disclosure includes an input sub-circuit 101, a charging control sub-circuit 102, a driving sub-circuit 103, a light-emitting control sub-circuit 104, a resetting sub-circuit 105, a first tank sub-circuit 106, and a second tank sub-circuit 107, as shown in fig. 5, some embodiments of the present disclosure provide a driving method of the pixel driving circuit 100, where the driving method includes:

one frame period T includes: a reset phase P1, a threshold voltage compensation phase P2, a power supply voltage compensation phase P3, and a light emission phase P4.

In the reset phase P1, a Gate scan signal V is generated from a Gate scan signal terminal Gate_gateThe input sub-circuit 101 is turned on to provide the data signal V with the first voltage_date(L) to the first node N₁. At a charge control signal V from a charge control signal terminal Con_conUnder the control of (3), the charge control sub-circuit 102 is turned on to transmit the first power voltage signal to the second node N₂. At a first node N₁And a second node N₂Under the action of the voltage of (3), the first tank sub-circuit 106 furtherAnd (4) charging the rows. Fourth node N₄Is the voltage of the reset signal, at a second node N₂And a fourth node N₄The second tank sub-circuit 107 is charged by the voltage of (a). At this stage, the Gate scanning signal V from the Gate scanning signal terminal Gate_gateThe reset sub-circuit 105 is turned on, and transmits a reset signal from the reset signal terminal Sus to the light emitting device D to reset the light emitting device D.

It should be noted that the data signal V_dateCan be a square wave pulse signal, the voltage of the square wave pulse part of the square wave pulse signal is the data signal V_dateThe voltage of the non-square wave pulse part of the square wave pulse signal is the data signal V_dateIs not operating voltage. In the reset phase P1 and the subsequent phases, the data signal V with the first voltage is mentioned_dateThe "first voltage" in (L) "refers to the data signal V_dateOf the data signal V having the second voltage_date(H) "middle" second voltage "refers to data signal V_dateThe operating voltage of (c).

Due to the driving sub-circuit 103 at the first node N₁Is turned on or off under the control of the voltage of (1), i.e. the driving transistor in the driving sub-circuit 103 is driven at the first node N₁Is turned on or off under the control of the voltage of (a). Therefore, the type of the driving transistor determines the magnitudes of the "first voltage" and the "second voltage". According to the requirements of each stage on the on-state or off-state of the driving transistor, under the condition that the driving transistor adopts an N-type transistor, the first voltage is high voltage, and the second voltage is low voltage; in the case where the driving transistor is a P-type transistor, the "first voltage" is a low voltage, and the "second voltage" is a high voltage. In the embodiment of the present disclosure, the driving transistor is a P-type transistor, the "first voltage" is a low voltage, and the "second voltage" is a high voltage.

In the threshold voltage compensation phase P2, the Gate scan signal V from the Gate scan signal terminal Gate_gateUnder the control of (2), the input sub-circuit 101 is turned on and still hasThe data signal V having a first voltage_date(L) to the first node N₁. At a first node N₁Under control of the voltage of (3), the drive sub-circuit 103 is turned on. At the same time, an emission scanning signal V from an emission scanning signal terminal EM_emThe light emission control sub-circuit 104 is turned on; and, at the Gate scanning signal V from the Gate scanning signal terminal Gate_gateUnder the control of (3), the reset sub-circuit 105 is turned on, and the driving sub-circuit 103, the light-emitting control sub-circuit 104 and the reset sub-circuit 105 cooperate to form a passage to conduct the second node N₂A conductive path to the reset signal terminal Sus to make the second node N₂Until the driving transistor in the driving sub-circuit 103 is turned off, under the action of the voltage of the reset signal terminal Sus, so that the threshold voltage V of the driving transistor is set_thWriting to the first tank sub-circuit 106.

In the power supply voltage compensation phase P3, the Gate scan signal V from the Gate scan signal terminal Gate_gateUnder the control of (1), the input sub-circuit 101 is turned on, and a Data signal V having a second voltage to be received at the Data signal terminal Data is generated_date(H) To the first node N₁The driving sub-circuit 103 is at a first node N₁Is turned off under the control of the voltage of (a). At the same time, a charge control signal V is provided from a charge control signal terminal Con_conUnder the control of (3), the charge control sub-circuit 102 is turned off; at a light emission scanning signal V from a light emission scanning signal terminal EM_emUnder the control of (1), the light-emitting control sub-circuit 104 is turned off, so that the first tank sub-circuit 106 is connected in series with the second tank sub-circuit 107 via the first node N₁Voltage jump of (2) to make the second node N₂The voltage of (2) jumps.

In the light emitting period P4, the charging control signal V from the charging control signal terminal Con_conUnder the control of (3), the charge control sub-circuit 102 is turned on to transmit the first power voltage signal to the second node N₂. The first tank sub-circuit 106 is based on the second node N₂To the first node N₁Is coupled to change the first node N₁The voltage of (c). At the changed first node N₁Under the control of voltage ofThe driving sub-circuit 103 is turned on to transmit to the second node N₂Is transmitted to the light emission control sub-circuit 104. At a light emission scanning signal V from a light emission scanning signal terminal EM_emThe light emitting control sub-circuit 104 is turned on to transmit the first power voltage signal to the light emitting device D to drive the light emitting device D to emit light.

In the pixel driving circuit 100 and the driving method thereof provided by the above-mentioned embodiment of the present disclosure, the reset sub-circuit 105 is coupled to the reset signal terminal Sus and the light emitting device D, and the reset sub-circuit 105 transmits the reset signal received at the reset signal terminal Sus to the light emitting device D, and the reset signal can eliminate the residual charge in the light emitting device D to reset the light emitting device D, so that in the light emitting phase P1, the influence of the residual charge in the light emitting device D in the previous frame period on the display of the picture in the current frame is avoided, and the uniformity of the light emitting brightness of the light emitting device D in each sub-pixel 10 is ensured.

And, the driving sub-circuit 103, the light-emitting control sub-circuit 104 and the reset sub-circuit 105 are turned on, and the three cooperate to form a path to turn on the second node N₂A conductive path to the reset signal terminal Sus to make the second node N₂Until the driving transistor in the driving sub-circuit 103 is turned off to turn off the threshold voltage V of the driving transistor_thWriting to the first tank sub-circuit 106. By the above way, in the light emitting period P4, the driving transistor is turned on by the discharging action of the first energy storage sub-circuit, so that the threshold voltage V of the driving transistor can be eliminated_thThe influence of the offset on the current passing through the light emitting device D improves the uniformity of the light emitting luminance of the light emitting device D within each sub-pixel 10.

Then, the charging control sub-circuit 102, the driving sub-circuit 103, and the light emission control sub-circuit 104 are turned off, and the first tank sub-circuit 106 and the second tank sub-circuit 107 are connected in series. The input sub-circuit 101 will have a data signal V of a second voltage_date(H) To the first node N₁Make the first node N₁Jumps from the voltage of the first voltage to the voltage of the second voltage. According to capacitor stringPrinciple of joint voltage division, first node N₁To make the second node N jump₂To make a transition for a subsequent transmission to the second node N₂Is compensated for. In the light-emitting period P4, the influence of the attenuation of the first power supply voltage signal on the current passing through the light-emitting device D can be eliminated, and the uniformity of the light-emitting luminance of the light-emitting device D in each sub-pixel 10 is further improved.

As shown in fig. 4, specific configurations of the input sub-circuit 101, the charging control sub-circuit 102, the driving sub-circuit 103, the light-emitting control sub-circuit 104, the reset sub-circuit 105, the first tank sub-circuit 106, and the second tank sub-circuit 107 included in the pixel driving circuit 100 will be described below.

In some embodiments, the input sub-circuit 101 comprises a first transistor T₁. A first transistor T₁Is coupled to a Gate signal terminal Gate, a first transistor T₁A first electrode coupled to the Data signal terminal Data, a first transistor T₁Second pole and first node N₁And (4) coupling. A first transistor T₁Is configured to receive the Gate scan signal V transmitted at the Gate scan signal terminal Gate during the reset phase P1, the threshold voltage compensation phase P2 and the power supply voltage compensation phase P3_gateIs turned on under the control of (1), and the Data signal V received at the Data signal terminal Data is_dataTo the first node N₁。

Here, the data signal V is in the reset phase P1 and the threshold voltage compensation phase P2_dataFor the data signal V having the first voltage_date(L); during the power supply voltage compensation phase P3, the data signal V_dataFor the data signal V having the second voltage_date(H)。

In some embodiments, the charge control subcircuit 102 includes a second transistor T₂. Second transistor T₂Is coupled to the charging control signal terminal Con, and a second transistor T₂A first electrode coupled to a first power supply voltage signal terminal VDD, a second transistor T₂Second pole and second node N₂And (4) coupling. Second transistor T₂Is configured to, inA bit phase P1 and a light-emitting phase P4, a charging control signal V transmitted by a charging control signal terminal Con_conIs turned on to transmit the first power voltage signal received at the first power voltage signal terminal VDD to the second node N₂。

In some embodiments, the driving sub-circuit 103 comprises a third transistor T₃I.e. the drive transistor. A third transistor T₃Control electrode of and first node N₁Coupled to a third transistor T₃First pole and second node N₂Coupled to a third transistor T₃Is coupled to the emission control sub-circuit 104. A third transistor T₃Is configured to be at a first node N during a threshold voltage compensation phase P2₁Is turned on under the control of the voltage, and forms a path in cooperation with the light emission control sub-circuit 104 and the reset sub-circuit 105 to make the third transistor T₃Is written into the first tank sub-circuit 106.

In some embodiments, the light emission control sub-circuit 104 includes a fourth transistor T₄. A fourth transistor T₄Is coupled to the emission scan signal terminal EM, and a fourth transistor T₄Is coupled to the drive sub-circuit 103, a fourth transistor T₄Is coupled to the light emitting device D (the fourth transistor T is shown in fig. 4)₄Through the third node N₃Coupled with the light emitting device D). A fourth transistor T₄Is configured such that, in the light emission period P4, the light emission scanning signal V transmitted at the light emission scanning signal terminal EM_emIs controlled to be turned on with the second transistor T₂And a third transistor T₃And forming a passage in a matching manner, and transmitting the first power voltage signal to the light-emitting device D so as to drive the light-emitting device D to emit light.

In some embodiments, the reset sub-circuit 105 includes a fifth transistor T₅. A fifth transistor T₅Is coupled to the Gate scanning signal terminal Gate, and a fifth transistor T₅Is coupled to the reset signal terminal Sus (a fifth transistor T is shown in fig. 4)₅Through the fourth node N₄Coupled to the reset signal terminal Sus), a fifth transistor T₅Is coupled to the light emitting device D (a fifth transistor T is shown in fig. 4)₅Through the third node N₃Coupled with the light emitting device D). A fifth transistor T₅Is configured such that, in the reset phase P1, the Gate scan signal V transmitted at the Gate scan signal terminal Gate_gateIs turned on to transmit the reset signal received at the reset signal terminal Sus to the light emitting device D to reset the light emitting device D.

Illustratively, as shown in fig. 4, the third node N3 is coupled to the anode of the light emitting device D. In this case, the reset signal is a low-level signal. In the reset phase P1, by the reset sub-circuit 105 transmitting a reset signal to the anode of the light emitting device, the residual positive charges on the anode of the light emitting device can be eliminated to reset the light emitting device D.

In some embodiments, the first tank subcircuit 106 includes a first capacitor C₁. A first capacitor C₁First end and first node N₁Coupled to a first capacitor C₁Second terminal and second node N₂And (4) coupling. A first capacitor C₁Is configured to reset, during a reset phase P1, according to the first node N₁And a second node N₂Is charged. And, in the power supply voltage compensation phase P3, the second transistor T is controlled to be enabled₂A third transistor T₃And a fourth transistor T₄Is turned off so that the first tank sub-circuit 106 and the second tank sub-circuit 107 form a series relationship. In this case, the first capacitor C₁Is also configured to, at a first node N₁Under the action of the voltage of (2), the second node N is enabled₂The voltage of (2) jumps.

In some embodiments, the second tank subcircuit 107 includes a second capacitor C₂. A second capacitor C₂Is coupled to the reset signal terminal Sus (a second capacitor C is shown in fig. 4)₂Through the fourth node N₄Coupled to a reset signal terminal Sus), a second capacitor C₂Second terminal and second node N₂And (4) coupling. A second capacitor C₂Is configured to reset, during a reset phase P1, according to the second node N₂And a reset signal received at a reset signal terminal Sus.

In the related art, a pixel driving circuit of a display device mostly adopts a 7T1C pixel driving circuit, where "T" denotes a thin film transistor, "C" denotes a capacitor, and 7T1C denotes that the pixel driving circuit includes seven thin film transistors and one capacitor. The pixel driving circuit 100 of the present disclosure is a 5T2C pixel driving circuit, that is, the pixel driving circuit 100 includes five thin film transistors and two capacitors, so that the number of thin film transistors is reduced, and thus the loss of the pixel driving circuit 100 is reduced. Moreover, since the pixel driving circuit 100 is disposed in the sub-pixel 10, the number of thin film transistors is reduced, which can reduce the area of the pixel driving circuit 100, thereby being beneficial to reducing the area of the sub-pixel 10, so that more sub-pixels 10 can be disposed in the display area AA having the same area, thereby being beneficial to increasing the resolution of the display device 01.

It should be noted that the transistors used in the pixel driving circuit 100 provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors are all taken as examples in the embodiments of the present disclosure for description.

In the embodiment of the present disclosure, the control electrode of each thin film transistor used in the pixel driving circuit 100 is a gate electrode of the thin film transistor, the first electrode is one of a source electrode and a drain electrode of the thin film transistor, and the second electrode is the other of the source electrode and the drain electrode of the thin film transistor. Since the source and drain electrodes of the thin film transistor may be symmetrical in structure, the source and drain electrodes may not be different in structure, that is, the first and second poles of the thin film transistor in the embodiment of the present disclosure may not be different in structure. Illustratively, in the case where the thin film transistor is a P-type transistor, the first pole of the thin film transistor is a source electrode, and the second pole of the thin film transistor is a drain electrode; illustratively, in the case where the thin film transistor is an N-type transistor, the first pole of the thin film transistor is a drain electrode, and the second pole of the thin film transistor is a source electrode.

In the embodiments of the present disclosure, the thin film transistors are all described by taking P-type transistors as an example, and in the pixel driving method provided below, the P-type transistors are also described as an example. It should be noted that the embodiments of the present disclosure include but are not limited thereto. For example, one or more thin film transistors in the pixel driving circuit 100 provided by the embodiment of the present disclosure may also be N-type transistors, and it is only necessary to connect the respective poles of the selected type of thin film transistors with reference to the respective poles of the corresponding thin film transistors in the embodiment of the present disclosure, and enable the corresponding voltage terminals to provide the corresponding high-level signal or low-level signal.

Also, in the embodiment of the present disclosure, the first capacitor C1 and the second capacitor C2 may be capacitor devices separately fabricated through a process, for example, by fabricating a dedicated capacitor electrode, and each capacitor electrode of the capacitor may be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), or the like. The capacitor can also be a parasitic capacitance between the thin film transistors, or realized by the thin film transistors and other devices and lines, or realized by using the parasitic capacitance between the lines of the circuit itself.

Also, in the circuit provided by the embodiment of the present disclosure, the first node N1, the second node N2, the third node N3, and the fourth node N₄Instead of representing the actual components, these nodes represent junctions of the relevant electrical connections in the circuit diagram, i.e. the nodes are equivalent nodes of the junctions of the relevant electrical connections in the circuit diagram.

In addition, in the embodiment of the present disclosure, the specific implementation manners of the input sub-circuit 101, the charging control sub-circuit 102, the driving sub-circuit 103, the light-emitting control sub-circuit 104, the resetting sub-circuit 105, the first tank sub-circuit 106, and the second tank sub-circuit 107 are not limited to the above-described manners, and may be any implementation manners, such as conventional connection manners well known to those skilled in the art, as long as the corresponding functions are guaranteed to be implemented. The above examples do not limit the scope of the present disclosure. In practical applications, a skilled person may choose to use or not use one or more of the above circuits according to the circumstances, and various combination modifications based on the above circuits do not depart from the principle of the present disclosure, and are not described in detail herein.

Some embodiments of the present disclosure also provide a driving method of a pixel driving circuit, which is applied to the pixel driving circuit as described in the above embodiments (see fig. 3 and 4).

In the following description, the first power voltage signal transmitted by the first power voltage signal terminal VDD is a dc high level signal, the second voltage signal transmitted by the second power voltage signal terminal VSS is a dc low level signal, and the reset signal transmitted by the reset signal terminal Sus is a dc low level signal.

In the exemplary description of each stage, it is exemplified that the pixel driving circuit 100 has a structure of 5T2C, and 5 thin film transistors included in the structure of 5T2C are all P row transistors. Further, "1" indicates a high level, and "0" indicates a low level.

As shown in fig. 5, the driving method includes: one frame period includes a reset phase P1, a threshold voltage compensation phase P2, a power supply voltage compensation phase P3, and a light emission phase P4.

In the reset phase P1:

the Gate scanning signal V transmitted from the Gate scanning signal terminal Gate of the input sub-circuit 101_gateUnder the control of (1), a Data signal V with a first voltage is received at a Data signal terminal Data_date(L) to the first node N₁。

The charging control signal V transmitted by the charging control sub-circuit 102 at the charging control signal terminal Con_conTransmits the first power voltage signal received at the first power voltage signal terminal VDD to the second node N₂。

Resetting the Gate scanning signal V transmitted by the sub-circuit 105 at the Gate scanning signal terminal Gate_gateTransmits a reset signal received at the reset signal terminal Sus to the light emitting device D to reset the light emitting device D.

At a first node N₁And a second node N₂Under the action of the voltage of (a), the first tank sub-circuit 106 is charged.

At the voltage of the reset signal and the second node N₂The second tank sub-circuit 107 is charged by the voltage of (b).

Illustratively, as shown in fig. 5 and 6, V is set in the reset phase P1_gate＝0，V_con＝0，V_em＝1，V_date(L)＝0。

A first transistor T₁On-grid scanning signal V_gateIs turned on to have the data signal V of the first voltage_date(L) to the first node N₁. As shown in FIG. 10, a first node N₁Has a voltage value of V_date(L). Second transistor T₂In the charging control signal V_conIs controlled to be conducted to transmit the first power voltage signal to the second node N₂. As shown in fig. 10, the second node N₂Has a voltage value of V_dd. A first capacitor C₁According to a first node N₁And a second node N₂Is charged.

The reset signal received at the reset signal terminal Sus is transmitted to the fourth node N₄A second capacitor C₂According to the second node N₂And the fourth node N₄Is charged.

A fifth transistor T₅On-grid scanning signal V_gateIs turned on to transmit the reset signal to the light emitting device D. The reset signal may remove residual charges on the light emitting device D to reset the light emitting device D.

In addition, in the reset phase P1, the third transistor T is turned on₃At a first node N₁Is turned on to disconnect the conductive path from the first power voltage signal terminal VDD to the light emitting device D, and to prevent the light emitting device D from emitting light at other stages except for the light emitting stage P4, by controlling the light emitting scan signal V received at the light emitting scan signal terminal EM_emMaking the fourth transistor T₄In the light emission scanning signal V_emIs cut off under the control of (1).

Note that, as shown in fig. 10, since the light emitting device D does not emit light at the other stages except for the light emitting stage P4, it is possible to prevent the light emitting device D from emitting light at the other stagesThe current of the light emitting device D is zero in the reset phase P1, the threshold voltage compensation phase P2, and the power supply voltage compensation phase P3. Further, as shown in fig. 10, in the reset phase P1, the threshold voltage compensation phase P2 and the power supply voltage compensation phase P3, the anode of the light emitting device D and the third node N₃In the coupled state, the voltage value of the anode of the light emitting device D is V_sus(i.e., the voltage value of the reset signal).

During the threshold voltage compensation phase P2:

the input sub-circuit 101 converts the data signal V having the first voltage_date(L) to the first node N₁。

The driving sub-circuit 103, the light-emitting control sub-circuit 104 and the reset sub-circuit 105 are turned on, and the three cooperate to form a path, so that the second node N₂Is changed by the voltage of the reset signal terminal Sus, the threshold voltage of the driving sub-circuit 103 is written into the first tank sub-circuit 106.

In addition, the charging control sub-circuit 102 is in the charging control signal V_conIs turned off under the control of (2), and ensures the second node N₂Is changed by the voltage of the reset signal terminal Sus.

Illustratively, as shown in FIGS. 5 and 7, V is applied during the threshold voltage compensation phase P2_gate＝0，V_con＝1，V_em＝0，V_date(L)＝0。

A first transistor T₁On-grid scanning signal V_gateIs turned on and still has the data signal V of the first voltage_date(L) to the first node N₁. As shown in FIG. 10, a first node N₁Has a voltage value of V_date(L). Second transistor T₂In the charging control signal V_conCut off under the control of (1); a third transistor T₃At a first node N₁Is turned on under the control of the voltage of the fourth transistor T₄In the light emission scanning signal V_emIs turned on under the control of (1), the fifth transistor T₅On-grid scanning signal V_gateIs conducted under the control of the first node, the second node and the third node are matched to form a channel so as to conduct the second node N₂A conductive path to the reset signal terminal Sus.

In the third transistor T₃A fourth transistor T₄And a fifth transistor T₅In the formed path, the second node N₂Has a voltage difference with the reset signal terminal Sus, so that the second node N₂Is gradually reduced under the action of the voltage of the reset signal terminal Sus until the second node N₂Is reduced to V_date(L)-V_thFIG. 10 shows a second node N₂Change in voltage value of. At this time, the first node N₁And a second node N₂I.e. the third transistor T₃Voltage difference of gate and source V_gsHas a difference of V_thI.e. V_gs＝V_thIn which V is_thIs a third transistor T₃The threshold voltage of (2).

According to the characteristics of the P-type transistor, when V is_gs＜V_thWhen the transistor is on; when V is_gs≥V_thWhen this happens, the transistor is turned off. Thus when the second node N is₂Is reduced to V_date(L)-V_thWhile the third transistor T is turned on₃Is switched from an on state to an OFF-bias (OFF-Bais) state, so that the third transistor T₃A fourth transistor T₄And a fifth transistor T₅The formed path is broken, and the second node N₂No longer decreases.

In the process, the first capacitor C₁Are respectively V_date(L)(N₁Point voltage), V_date(L)-V_th(N₂Point voltage) with a voltage difference of V between the two terminals_thThereby realizing the third transistor T₃Threshold voltage V of_thWriting into the first capacitor C₁In (1).

During the supply voltage compensation phase P3:

the input sub-circuit 101 receives the Data signal V with the second voltage at the Data signal terminal Data_date(H) To the first node N₁。

The charging control sub-circuit 102 and the light emission control sub-circuit 104 are turned off, and the first tank sub-circuit 106 is connected in series with the second tank sub-circuit 107, so that the first tank sub-circuitTwo nodes N₂The voltage of (2) jumps.

Illustratively, as shown in fig. 5 and 8, V is set during the supply voltage compensation phase P3_gate＝0，V_con＝1，V_em＝1，V_date(H)＝1。

A first transistor T₁On-grid scanning signal V_gateIs turned on to have the data signal V of the second voltage_date(H) To the first node N₁. As shown in FIG. 10, a first node N₁Has a voltage value of V_date(H) In that respect A third transistor T₃At a first node N₁Is turned off under the control of the voltage of the second transistor T₂In the charging control signal V_conIs turned off, the fourth transistor T₄In the light emission scanning signal V_emIs turned off under the control of (1) to make the first capacitor C₁And a second capacitor C₂Are connected in series. Further, a fifth transistor T₅On-grid scanning signal V_gateIs turned on under the control of (1).

By the above arrangement, the first node N₁Voltage value of from V_date(L) jump to V_date(H) I.e. the first node N₁Voltage value of variable quantity V_date(H)-V_date(L). Note the first capacitor C₁Has a capacitance value of C1, a second capacitor C₂Has a capacitance value of C2, and the first node N is based on the principle of series voltage division of capacitors₁To make the second node N jump₂Has a second node N₂The voltage value of the change amount is

The second node N₂Has a voltage value of

FIG. 10 shows a second node N₂A jump in voltage value of (c).

In the light emission phase P4:

the charge control sub-circuit 102 transmits the first power voltage signal to the second node N₂。

The first tank sub-circuit 106 is based on the second node N₂To the first node N₁Is coupled to change the first node N₁The voltage of (c).

The driving sub-circuit 103 will transmit to the second node N₂Is transmitted to the light emission control sub-circuit 104.

The light emission control sub-circuit 104 transmits a first power voltage signal to the light emitting device D to drive the light emitting device D to emit light.

Illustratively, as shown in FIGS. 5 and 9, V_gate＝1，V_con＝0，V_em＝0，V_date＝0。

A first transistor T₁On-grid scanning signal V_gateIs cut off under the control of (1). Second transistor T₂In the charging control signal V_conIs controlled to be conducted to transmit the first power voltage signal to the second node N₂And thus the second node N₂Has a voltage value of V_ddAs shown in fig. 10. According to the charge retention law of the capacitor, due to the second node N₂Voltage of

Becomes V_ddI.e. the first capacitor C₁The voltage value of the second terminal has a variation of

Thereby the first capacitor C₁Also the voltage of the first terminal of (1) is changed by the same amount, i.e. the first node N₁Has a voltage value of

FIG. 10 shows a first node N₁A change curve of the voltage value of (c).

Now at the first node N₁Under the control of the voltage of, the third transistor T₃Is conducted and will be transmitted to the second node N₂Is transmitted to the fourth transistor T₄The first pole of (1).

A fourth transistor T₄In the light emission scanning signal V_emIs turned on to transmit the first power voltage signal to the light emitting device D to drive the light emitting device D to emit light. Fig. 10 shows the voltage value of the anode of the light emitting device D and the current value through the anode at the light emitting period P4 when current passes through the light emitting device D.

Further, a fifth transistor T₅On-grid scanning signal V_gateIs cut off under the control of (1).

A third transistor T₃Voltage difference of gate and source V_gsI.e. the first node N₁And a second node N₂At the light emitting stage P4, the third transistor T₃The calculation formula of the gate-source voltage difference of (1) is,

according to the calculation formula of the driving current,

wherein, I_dsIs a third transistor T₃Is also the operating current through the light emitting device D; μ is a third transistor T₃(ii) carrier mobility; c_oxIs a third transistor T₃The unit area channel capacitance of (2); W/L is a third transistor T₃The channel width to length ratio of (1).

The third transistor T can be obtained from the calculation formula of the upper driving current₃The magnitude of the generated driving current and the third transistor T₃Threshold voltage V of_thThe first power supply voltage signal received at the first power supply voltage signal terminal VDD and the second power supply voltage signal transmitted by the second power supply voltage signal terminal VSS are independent of each other, so that the third transistor T₃The magnitude of the generated driving current is not influenced by the threshold voltage deviation and the attenuation of the power supply voltage signals (including the first power supply voltage signal and the second power supply voltage signal), and the pixel caused by the preparation process is avoidedThird transistor T in driver circuit 100₃The different threshold voltages of the driving circuits cause different magnitudes of the driving currents, and the different magnitudes of the driving currents cause different influences on the light-emitting brightness of the light-emitting devices D due to the attenuation of the power supply voltage signals, so that the uniformity of the light-emitting brightness of each light-emitting device D is improved.

As shown in fig. 11 to 14, some embodiments of the present disclosure further provide an array substrate 1, where the array substrate 1 includes a plurality of pixel driving circuits 100 as described in some embodiments above (only one pixel driving circuit 100 in the array substrate 1 is shown in the drawings).

The array substrate 1 includes: the semiconductor device includes a substrate 101, an active layer M1 disposed on one side of the substrate 101, a first gate conductive layer M2, a second gate conductive layer M3 and a source/drain conductive layer M4 sequentially disposed on one side of the active layer M1 away from the substrate 101. Each film layer is a conductive film layer, and besides the conductive film layers, the array substrate 1 further comprises an insulating layer arranged between every two adjacent conductive film layers so as to avoid short circuit between the two adjacent conductive film layers.

In the case where the pixel driving circuit 100 has the structure of 5T2C shown in fig. 4, the pixel driving circuit 100 includes a first transistor T₁A second transistor T₂A third transistor T₃A fourth transistor T₄A fifth transistor T₅A first capacitor C₁And a second capacitor C₂The structure of each of the components in the array substrate 1 will be described below.

As shown in fig. 11, in some embodiments, the active layer M1 includes a first transistor T₁A second transistor T₂A third transistor T₃A fourth transistor T₄And a fifth transistor T₅A channel portion, a source portion and a drain portion. In fig. 11, the portions of the active layer M1 framed by the dashed line frames representing the respective transistors are channel portions of the respective transistors, and the portions located on both sides of the dashed line frames are source portions and drain portions of the respective transistors. Wherein the source and drain parts of the transistor refer to the first and second pole, respectively, of the transistor or to the second pole, respectively, of the transistorTwo poles and a first pole.

As shown in fig. 12, in some embodiments, the first gate conductive layer M2 includes a first transistor T₁A second transistor T₂A third transistor T₃A fourth transistor T₄A fifth transistor T₅The gate of each transistor is indicated by a portion of the first gate conductive layer M2 enclosed by a dashed line frame representing each transistor. Here, the gate of each transistor refers to a control electrode of each transistor.

In some embodiments, the first gate conductive layer M2 further includes a gate scanning signal line GL, a light-emitting scanning signal line EL, and a charging control signal line L_conWherein one gate scanning signal line GL is divided into two gate scanning signal lines GL1 and GL2 in the display area AA of the display device 01. A gate of the first transistor T1 is coupled to a gate scan signal line GL2, and a gate of the second transistor T₂Gate and charge control signal line L_conCoupled to, a fourth transistor T₄Is coupled to a light-emitting scanning signal line EL, a fifth transistor T₅Is coupled to the gate scanning signal line GL. For example, the gate of the first transistor T1 is integrated with the gate scanning signal line GL, and the second transistor T₂Gate and charge control signal line L_conAs an integral structure, a fourth transistor T₄The grid electrode of the first transistor T and the light-emitting scanning signal line EL are in an integral structure₅The gate electrode of (a) and the gate scanning signal line GL1 are integrally structured.

In some embodiments, the first gate conductive layer M2 further includes a first capacitor C₁First plate a (i.e. first capacitor C)₁Is also the first capacitor C₁And a first node N₁One end of the coupling). Represents a first capacitor C₁The portion of the first gate conductive layer M2 outlined by the dashed line frame of (a) represents the first capacitor C₁The first plate a.

Exemplarily, a third transistor T is represented₃The portion of the first plate a outlined by the dashed line frame of (a) represents the third transistor T₃Of the first capacitor C₁First plate a and a third transistor T₃Is common to the gates.

In some embodiments, the first gate conductive layer M2 further includes a second capacitor C₂Second plate C (i.e. second capacitor C)₂Is also the second capacitor C₂And a fourth node N₄One end of the coupling). Represents a second capacitor C₂The portion of the first gate conductive layer M2 outlined by the dashed line frame of (a) represents the second capacitor C₂And a second plate c.

As shown in fig. 13, in some embodiments, the second gate conductive layer M3 includes a first capacitor C₁Second plate b (i.e. first capacitor C)₁Is also the first capacitor C₁And a second node N₂One end of the coupling). Represents a first capacitor C₁The portion of the second gate conductive layer M3 outlined by the dashed line frame of (a) is denoted as a first capacitor C₁And (b) a second plate. Wherein the first capacitor C₁The second plate b is provided with a via hole exposing the first capacitor C₁The first plate a.

In some embodiments, the second gate conductive layer M3 further includes a second capacitor C₂First plate d (i.e. second capacitor C)₂Is also the second capacitor C₂And a second node N₂One end of the coupling). Represents a second capacitor C₂The portion of the second gate conductive layer M3 framed by the dashed line frame of (a) is denoted as a second capacitor C₂The first plate d. The first plate d of the second capacitor C2 has a via hole exposing the second plate C of the second capacitor C2.

In some embodiments, the second gate conductive layer M3 further includes a reset signal line L_susFor transmitting a reset signal.

As shown in fig. 14, in some embodiments, the source-drain conductive layer M4 includes a VDD line and a data signal line DL. The VDD line passes through the via hole and the second transistor T₂Is coupled to the source portion or the drain portion of (a). The data signal line DL passes through the via hole and the first transistor T₁Is coupled to the source portion or the drain portion of (a).

In some embodiments, the source-drain conductive layer M4 further includes a conductive pattern H1, which is believed to beSignal line DL and first transistor T₁Is coupled to the first transistor T, one end of the conductive pattern H1 passes through the via hole and the first transistor T₁Is coupled to the drain portion or the source portion of the first capacitor C, and the other end of the first capacitor C₁And the first capacitor C and the via hole on the second plate b₁Is coupled to the first plate a. The conductive pattern H1 and the first capacitor C₁Is insulated from the second plate b.

In some embodiments, the source-drain conductive layer M4 further includes a conductive pattern H2 at the VDD line and the second transistor T₂Is coupled, one end of the conductive pattern H2 is connected to the second transistor T through the via₂Is coupled to the other terminal through a via on the first plate d of the second capacitor C2 to the second plate C of the second capacitor C2. Note that the conductive pattern H2 is insulated from the first plate d of the second capacitor C2. The conductive pattern H2 also passes through the via hole and the first capacitor C₁Is coupled to the second plate b.

In some embodiments, the source-drain conductive layer M4 further includes a conductive pattern H3, one end of the conductive pattern H3 is coupled to the first plate d of the second capacitor C2 through a via, and the other end is coupled to the reset signal line L through a via_susAnd (4) coupling. And, the conductive pattern H3 also passes through the via hole and the fifth transistor T₅Is coupled to the source portion or the drain portion of (a).

In some embodiments, the source-drain conductive layer M4 further includes a conductive pattern H4, and the conductive pattern H4 passes through the via hole and the fourth transistor T₄Is coupled to the source portion or the drain portion of (a).

As shown in fig. 14, in some embodiments, an anode D1 of the light emitting device D is disposed above the source-drain conductive layer M4, and the anode D1 of the light emitting device D is coupled to the conductive pattern H4 through a via hole.

It should be noted that, in the above description, the active layer M1 is located on the side of the first gate conductive layer M2 and the second gate conductive layer M3 close to the substrate 101, that is, each transistor in the pixel driving circuit 100 has a top gate structure. However, the structure of each transistor in the embodiments of the present disclosure is not limited thereto, and it may also be a bottom gate structure, and the structure of each corresponding film layer is not described herein again.

The advantageous effects of the array substrate 1 are the same as those of the pixel driving circuit 100 in the above embodiments, and are not described herein again.

Some embodiments of the present disclosure also provide a display device 01, as shown in fig. 15, the display device 01 including an array substrate 1 provided with the pixel driving circuit 100 described above.

The array substrate 1 includes a substrate 101 and a pixel driving circuit 100 disposed on one side of the substrate 101. Each pixel driving circuit 100 includes a plurality of thin film transistors, for example, a plurality of thin film transistors including a first transistor T₁A second transistor T₂A third transistor T₃A fourth transistor T₄And a fifth transistor T₅Only one of the thin film transistors is shown in fig. 15: a fourth transistor T₄。

As shown in fig. 15, the fourth transistor T₄May include an active layer 103, a gate insulating layer 104, a gate electrode 105, an interlayer insulating layer 106, a source electrode 107, and a drain electrode 108, which are sequentially stacked on a substrate base 101. Wherein the active layer 103 includes a channel portion 103a, a source portion 103b and a drain portion 103c, and the source 107 and the drain 108 are coupled to the source portion 103b and the drain portion 103c of the active layer 103 through vias, respectively. The source 107 and the drain 108 may be made of the same material and disposed in the same layer.

The array substrate 1 further includes a buffer layer 102 disposed between the substrate 101 and the pixel driving circuit 100, and the buffer layer 102 can protect the substrate 101.

In some embodiments, the display device 01 further includes a passivation layer 201 and a planarization layer 202 disposed on a side of the array substrate 1 away from the substrate 101. Wherein the passivation layer 201 and the planarization layer 202 are disposed therein for exposing the fourth transistor T₄So that the anode D1 of the light emitting device D passes through the via hole and the fourth transistor T₄Is coupled to the source 107 or the drain 108. This via exposing the fourth crystal is shown in fig. 15Pipe T₄In this case, the fourth transistor T₄The drain electrode 108 corresponds to the conductive pattern H2 in fig. 15.

The material of the passivation layer 201 may be an inorganic material, and the material of the planarization layer 202 may be an organic material.

As shown in fig. 15, the light emitting device D includes an anode D1, a light emitting layer D2 disposed on the side of the anode D1 away from the substrate base plate 101, and a cathode D3 disposed on the side of the light emitting layer D2 away from the substrate base plate 101.

Wherein the anode D1 of the light emitting device D is connected to the fourth transistor T in the pixel driving circuit 100 through the via holes opened in the via passivation layer 201 and the planarization layer 202₄Coupled, the anode D1 of the light emitting device D and the fourth transistor T are shown in FIG. 15₄The drain 108 of (a) is coupled to the case. So that the pixel driving circuit 100 may be used to transmit a first power voltage signal to the anode of the light emitting device D and the cathode D3 of the light emitting device D is used to receive a second power voltage signal. Thus, an electric field is formed between the anode D1 and the cathode D3 of the light emitting device D, so that light emission at the light emitting layer D2 can be driven.

The cathodes D3 of the light-emitting devices D may communicate with each other, and form a planar electrode structure covering the entire surface, that is, the cathode D3 may be a structure in which the entire layer is formed. Fig. 15 shows only a portion of the cathode D3 as one light emitting device D.

In some embodiments, the display device 01 further includes a pixel defining layer 203 disposed on a side of the planarization layer 202 away from the substrate base plate 101, the pixel defining layer 203 having a plurality of openings, one opening corresponding to one light emitting device D.

It should be noted that, in some embodiments, the light emitting device D may be a top emission type (emitting light in a direction away from the array substrate 1), a bottom emission type (emitting light in a direction close to the array substrate 1), or a double-sided emission type (emitting light in both a direction away from the array substrate 1 and a direction close to the array substrate 1).

For example, in the case where the light emitting device D is a top emission type light emitting device, the anode D1 near the array substrate 1 is opaque, and the cathode D3 far from the array substrate 1 is transparent or translucent; in the case where the light emitting device D is a bottom emission type light emitting device, the anode D1 near the array substrate 1 is transparent or translucent, and the cathode D3 distant from the array substrate 1 is opaque; in the case where the light emitting device D is a double-sided light emitting type light emitting device, both the anode D1 near the array substrate 1 and the cathode D3 far from the array substrate 1 are transparent or translucent.

In some embodiments, the display device 01 further comprises an encapsulation structure 204. For example, the package structure 204 may be a package film or a package substrate. In the case where the encapsulation structure 204 is an encapsulation film, the encapsulation structure 204 may be a laminated structure formed by sequentially laminating at least three films, in which the film closest to the base substrate 101 and the film farthest from the base substrate 101 may both be inorganic films, and the film between two adjacent inorganic films may be an organic film.

The display device 01 provided by the present disclosure has the same beneficial effects as the pixel driving circuit 100 described above, and by adopting the 5T2C pixel driving circuit, the number of thin film transistors arranged is reduced, so that the loss of the pixel driving circuit 100 is reduced, the area of the sub-pixel 10 is reduced, and the display resolution of the display device 01 is increased. The pixel driving circuit 100 compensates the threshold voltage of the driving transistor and the power supply voltage, so that the problem that the currents passing through the light emitting devices D are inconsistent due to the threshold voltage deviation of the driving transistor and the attenuation of the power supply voltage signal is solved, the uniformity of the light emitting brightness of each light emitting device D is ensured, and the problem that the light emitting brightness of the display device 01 is uneven is solved.

In some embodiments, the display device 01 further includes a frame, a circuit board, a display driver IC (integrated circuit), and other electronic components, and the array substrate 1 is disposed in the frame.

The display device 01 provided by the embodiments of the present disclosure may be any device that displays images, whether moving (e.g., video) or stationary (e.g., still image), and whether text or text. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, Personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., a display of images for a piece of jewelry), and so forth.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A pixel driving circuit, comprising: the light-emitting control circuit comprises an input sub-circuit, a charging control sub-circuit, a driving sub-circuit, a light-emitting control sub-circuit, a resetting sub-circuit, a first energy storage sub-circuit and a second energy storage sub-circuit; wherein,

the reset sub-circuit is coupled with the grid scanning signal end, the reset signal end and the light-emitting device; the reset sub-circuit is configured to transmit a reset signal received at the reset signal terminal to the light emitting device to reset the light emitting device in response to a gate scan signal received at the gate scan signal terminal;

the input sub-circuit is coupled with the grid scanning signal end, the data signal end and the first node; the input sub-circuit is configured to transmit a data signal received at the data signal terminal to the first node under control of the gate scan signal;

the charging control sub-circuit is coupled with a charging control signal end, a first power supply voltage signal end and a second node; the charge control subcircuit is configured to transmit a first supply voltage signal received at the first supply voltage signal terminal to the second node in response to a charge control signal received at the charge control signal terminal;

the first tank subcircuit is coupled with the first node and the second node; the first tank subcircuit is configured to be charged according to voltages of the first node and the second node; and under the condition that the first energy storage sub-circuit and the second energy storage sub-circuit form a series connection relation, under the action of the voltage of the first node, the voltage of the second node jumps;

the second tank sub-circuit is coupled with the second node and the reset signal terminal; the second tank subcircuit is configured to charge in accordance with a voltage of the second node and a reset signal received at the reset signal terminal;

the driving sub-circuit is coupled with the first node, the second node and the light emitting control sub-circuit; the driving sub-circuit is configured to form a path in cooperation with the light-emitting control sub-circuit and the reset sub-circuit under the control of the voltage of the first node, so that the threshold voltage of the driving transistor in the driving sub-circuit is written into the first energy storage sub-circuit;

the light-emitting control sub-circuit is also coupled with a light-emitting scanning signal end and the light-emitting device; the light emission control sub-circuit is configured to form a path in cooperation with the charging control sub-circuit and the driving sub-circuit in response to a light emission scan signal received at the light emission scan signal terminal, and transmit the first power supply voltage signal to the light emitting device to drive the light emitting device to emit light.

2. The pixel driving circuit according to claim 1, wherein the input sub-circuit comprises a first transistor; a control electrode of the first transistor is coupled to the gate scan signal terminal, a first electrode of the first transistor is coupled to the data signal terminal, and a second electrode of the first transistor is coupled to the first node.

3. The pixel driving circuit according to claim 1, wherein the charge control sub-circuit comprises a second transistor; a control electrode of the second transistor is coupled to the charge control signal terminal, a first electrode of the second transistor is coupled to the first power voltage signal terminal, and a second electrode of the second transistor is coupled to the second node.

4. The pixel driving circuit according to claim 1, wherein the driving sub-circuit comprises a third transistor; a control electrode of the third transistor is coupled to the first node, a first electrode of the third transistor is coupled to the second node, and a second electrode of the third transistor is coupled to the light emission control sub-circuit.

5. The pixel driving circuit according to claim 1, wherein the light emission control sub-circuit comprises a fourth transistor; a control electrode of the fourth transistor is coupled to the light emitting scan signal terminal, a first electrode of the fourth transistor is coupled to the driving sub-circuit, and a second electrode of the fourth transistor is coupled to the light emitting device.

6. The pixel driving circuit according to claim 1, wherein the reset sub-circuit comprises a fifth transistor; a control electrode of the fifth transistor is coupled to the gate scan signal terminal, a first electrode of the fifth transistor is coupled to the reset signal terminal, and a second electrode of the fifth transistor is coupled to the light emitting device.

7. The pixel driving circuit of claim 1, wherein the first tank sub-circuit comprises a first capacitor; a first terminal of the first capacitor is coupled to the first node and a second terminal of the first capacitor is coupled to the second node;

the second tank sub-circuit comprises a second capacitor; a first terminal of the second capacitor is coupled to the reset signal terminal, and a second terminal of the second capacitor is coupled to the second node.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein the light emitting device is further coupled to a second power supply voltage signal terminal; the voltage of the reset signal transmitted by the reset signal end is less than the voltage of the second power supply voltage signal transmitted by the second power supply voltage signal end.

9. A driving method of a pixel driving circuit, which is applied to the pixel driving circuit according to any one of claims 1 to 8; the driving method includes:

one frame period includes a reset phase, a threshold voltage compensation phase, a power supply voltage compensation phase and a light emitting phase;

in the reset phase:

the input sub-circuit transmits a data signal having a first voltage received at the data signal terminal to the first node;

the charge control subcircuit transmits a first supply voltage signal received at the first supply voltage signal terminal to the second node;

the reset sub-circuit transmits a reset signal received at the reset signal terminal to the light emitting device to reset the light emitting device;

the first energy storage sub-circuit is charged under the action of the voltages of the first node and the second node;

under the action of the voltage of the reset signal end and the voltage of the second node, the second energy storage sub-circuit is charged;

during the threshold voltage compensation phase:

the input sub-circuit transmits the data signal having the first voltage to the first node;

the driving sub-circuit, the light-emitting control sub-circuit and the reset sub-circuit are opened and matched to form a passage, so that the voltage of the second node is changed under the action of the voltage of the reset signal end, and the threshold voltage of the driving sub-circuit is written into the first energy storage sub-circuit;

during the supply voltage compensation phase:

the input sub-circuit transmits a data signal having a second voltage received at the data signal terminal to the first node;

the charging control sub-circuit and the light-emitting control sub-circuit are closed, and the first energy storage sub-circuit and the second energy storage sub-circuit are connected in series to enable the voltage of the second node to jump;

in the light emitting stage:

the charge control subcircuit transmits the first power supply voltage signal to the second node;

the first energy storage sub-circuit couples the voltage of the first node according to the voltage of the second node so as to change the voltage of the first node;

the driving sub-circuit transmits a first power supply voltage signal transmitted to the second node to the light emission control sub-circuit;

the light emitting control sub-circuit transmits the first power voltage signal to the light emitting device to drive the light emitting device to emit light.

10. A display device comprising a plurality of pixel driving circuits according to any one of claims 1 to 8.