CN1885396A

CN1885396A - Organic light emitting diode display

Info

Publication number: CN1885396A
Application number: CNA2006100835444A
Authority: CN
Inventors: 朴权植; 尹洙荣; 全敏斗
Original assignee: LG Philips LCD Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2005-06-25
Filing date: 2006-06-05
Publication date: 2006-12-27
Anticipated expiration: 2026-06-05
Also published as: KR101184065B1; KR20060135434A; CN100559442C

Abstract

An organic light emitting diode display device includes: a pixel array having a plurality of scan lines and a plurality of data lines that cross each other, a plurality of power voltage supply lines to which a high level power supply voltage is supplied and that are substantially parallel to the data lines, a plurality of reset lines substantially parallel to the scan lines, a plurality of organic light emitting diodes that emit light due to the high level power supply voltage from the power voltage supply line, and a plurality of organic light emitting diode drive circuits that drive the organic light emitting diode with data from the data line in response to a scan signal from the scan line and that is initialized in response to a reset signal from the reset line; a scan drive circuit that supplies the scan signal to the scan lines; a reset drive circuit that supplies the reset signal to the reset lines that initializes the organic light emitting diode drive circuit; and a data drive circuit that supplies the data to the data lines respectively, wherein the scan drive circuit and the reset drive circuit are on a substrate including the pixel array.

Description

Organic light emitting diode display

The application requires the korean patent application P2005-055393 that submits on June 25th, 2005 and the rights and interests of the korean patent application P2005-056551 that submits on June 28th, 2005, here is incorporated herein by reference.

Invention field

The present invention relates to a kind of organic light emitting diodde desplay device, relate in particular to a kind of organic light emitting diodde desplay device that is applicable to the performance change of the device that prevents to drive Organic Light Emitting Diode and guarantees the reliability of device.

Background technology

Recently, various outstanding flat-panel display devices occurred, reduced weight and volume, thereby can eliminate the shortcoming of cathode ray tube (CRT).Such flat-panel display device comprises LCD (LCD), Field Emission Display (FED), plasma display device (PDP) and light emitting diode (LED) display etc.

Light-emitting diode display spare use in these display devices is a kind of can be by the luminous LED that is compounded to form phosphor material in electronics and hole.Light-emitting diode display spare is divided into the inorganic light-emitting diode display spare and organic LED (OLED) display device that adopt organic compound as phosphor material of employing mineral compound as phosphor material usually.A kind of like this OLED display device is highlighted and is called the display device that surmounts the epoch, because it has advantages such as low voltage drive, autoluminescence, thin thickness, wide visual angle, rapid response speed and high-contrast.

OLED generally includes electron injecting layer, electron transfer layer, luminescent layer, hole transmission layer and the hole injection layer that places between negative electrode and the anode.In such OLED, when between anode and negative electrode, applying predetermined voltage, the electronics that produces from negative electrode enters luminescent layer through electron injecting layer and electron transfer layer, enter luminescent layer from anode by hole injection layer and hole transmission layer from the hole that anode produces simultaneously, thereby, because compound and luminous at luminescent layer of electronics that flows into by electron transfer layer and hole transmission layer and hole.

As shown in Figure 1, use the active array type OLED display device of above-mentioned OLED to comprise having n * m the pixel P[i that in pixel area, is arranged as n * m matrix type, j] oled panel 13, pixel area is intersected to Gn (n is a positive integer) and m bar data line D1 to Dm (m is a positive integer) by n bar sweep trace G1 and limits; Be used for the scan drive circuit 12 of the sweep trace G1 of driving OLED panel 13 to Gn; Be used for the data drive circuit 11 of the data line D1 of driving OLED panel 13 to Dm; And be used for to each pixel P[i j] provide that high power supply voltage VDD's provide line S1 to Sm with data line D1 to the m bar voltage that Dm be arranged in parallel.Here P[i, j] be the pixel that is positioned at the capable j row of i, i is that the positive integer and the j that are less than or equal to n are the positive integers that is less than or equal to m.

Scan drive circuit 12 comprises a plurality of grid drive integrated circults.Each grid drive integrated circult comprise one each horizontal cycle to sweep signal be shifted successively with output shift register; Output signal amplitude of oscillation with shift register converts to and is fit to drive the pixel driving device, thin film transistor (TFT) TFT just, the level translator of the amplitude of oscillation; And one be connected level translator and sweep trace G1 to the output buffer between the Gn.

Scan drive circuit 12 provides sweep signal that the horizontal line of the organic LED panel 13 of data is provided with selection to sweep trace G1 to Gn successively.

Data drive circuit 11 becomes analog data voltage with the numerical data voltage transitions of outside input, and whenever data drive circuit 11 provides analog data voltage to data line D1 to Dm what sweep signal was provided.

When sweep signal is applied to sweep trace G1 to Gn, each P[i, j] pixel receives data voltage from data line D1 to Dm, and generation is corresponding to the light of data voltage.

For this purpose, each P[i, j] pixel comprises that having anode and supply voltage provides the OLED that line S1 links to each other to Sm and be connected to sweep trace G1 is applied with low supply voltage VSS to Dm's and on it to Gn and data line D1 OLED driving circuit 15.

OLED driving circuit 15 comprises being used to respond from sweep trace G1 and will be provided to the first transistor T1 of first node N1 from data line D1 to the data voltage of Dm to the sweep signal of Gn; Be used for transistor seconds T2 in response to the Control of Voltage OLED current amount flowing of first node N1; And give first node N1 the memory capacitance Cs of charging.

The drive waveforms of OLED driving circuit 15 as shown in Figure 2.In Fig. 2, ' 1F ' is a frame period, and ' 1H ' is a horizontal cycle, ' Vg_i ' is the gate voltage that provides from i sweep trace Gi, and ' Psc ' is sweep signal, and ' Vd_j ' is the data voltage that provides from j data line Dj, ' VN1 ' is voltage and the ' I of first node N1 _OLED' be the electric current that flows through OLED.

With reference to Fig. 1 and 2, when sweep signal by sweep trace G1 when Gn is applied to the first transistor T1 and goes up, the first transistor T1 conducting, thus will be provided to first node N1 from the data voltage Vd of data line D1 to Dm.The data voltage Vd that is provided to first node N1 charges among the memory capacitance Cs and is applied to the grid of transistor seconds T2.If under the effect of the data voltage Vd that provides by this way, transistor seconds T2 conducting, electric current flows through OLED so.Simultaneously, under the effect of high power supply voltage VDD, produce the electric current flow through OLED, and the magnitude of current is directly proportional with voltage magnitude on being applied to transistor seconds T2.In addition, even the first transistor T1 ends, transistor seconds T2 keeps conducting state under the effect of memory capacitance Cs, thereby is controlled at current amount flowing among the OLED, up to applying next frame data voltage Vd.

In Fig. 1 and 2, there are the following problems for the OLED display device of prior art:

The first, positive data voltage Vd is applied to the grid of the transistor seconds T2 of driving OLED for a long time.With the passing of time, under positive data voltage Vd effect, accumulation has gate bias stress (gate bias stress) as shown in Figure 3 among the transistor seconds T2.And the gate bias pressure of accumulation causes the skew of the threshold voltage Vth of transistor seconds T2.With the passing of time, because the performance degradation of transistor seconds T2, the OLED display device of prior art becomes unstable aspect driving and its reliability reduces.Shown in Fig. 4 B is when the long-time repetitiousness of negative current is added to transistor gate, and the characteristics of transistor that is caused by the negative-grid bias stress changes, and the arrow mark in Fig. 4 A and 4B shows the motion of transistor thresholds voltage Vth.

The second, be used for electric charge in the Control Node of scan drive circuit 12 control outputs owing to remain in, be applied with unwanted voltage on the grid line, the reliability of prior art OLED display device scan operation reduces thus.Especially, if for the output of the shift register that increases scan drive circuit 12 was charged to the Q node with residual charge in the non-scan period, non-expectation voltage occurs at grid line so, therefore in transistor T 1, T2, produce leakage current, and the reliability of scan operation reduces.

The 3rd, in the OLED of prior art display device, driving circuit, scan drive circuit 12 height such as cost such as grade for example, and owing to scan drive circuit 12 need be adhered to operation on the substrate that forms cell array, so the manufacturing cost height.

Summary of the invention

Therefore, an object of the present invention is to provide a kind of organic light emitting diodde desplay device, be suitable for preventing that the device performance that drives Organic Light Emitting Diode from changing and the assurance device reliability.

Another object of the present invention provides a kind of organic light emitting diodde desplay device, the reliability when being suitable for guaranteeing driving OLED by the residual charge that periodically discharges Control Node in sweep trace and the scan drive circuit.

Further object of the present invention provides a kind of organic light emitting diodde desplay device, is suitable for reducing circuit cost and manufacturing process.

In order to realize these and other objects of the present invention, according to an aspect of the present invention, a kind of organic light emitting diodde desplay device comprises: cell array, have multi-strip scanning line intersected with each other and many data lines, many are applied with high power supply voltage and provide line with supply voltage that data line be arranged in parallel, many the reset lines that be arranged in parallel with sweep trace, luminous light emitting diode under a plurality of high power supply voltage effects that line is provided at supply voltage, according to the OLED driver circuit from the data-driven Organic Light Emitting Diode of data line, and this OLED driver circuit response is from the reset signal initializes of reset line from the sweep signal of sweep trace in many bar responses; Be used for providing the scan drive circuit of sweep signal to sweep trace; Be used for being provided for the reset drives circuit of the reset signal of initialization OLED driver circuit to reset line; Be used for providing to data line respectively the data drive circuit of data; And scan drive circuit and reset drives circuit are positioned on the substrate that is formed with cell array.

In organic light emitting diodde desplay device, cell array places between scan drive circuit and the reset drives circuit.

In organic light emitting diodde desplay device, OLED driver circuit comprises: be used for the responding scanning signal provides switching transistor from data to first node; Be used for driving transistors by the Control of Voltage Organic Light Emitting Diode streaming current of described first node; And the reset transistor that is used to respond reset signal discharge first node.

In organic light emitting diodde desplay device, reset signal postpones in sweep signal.

In organic light emitting diodde desplay device, reset signal about 1/2 frame period behind the self-scanning signal produces.

In organic light emitting diodde desplay device, the transistor in transistor in the cell array and the transistor in the scan drive circuit, the reset drives circuit is the amorphous silicon transistor.

In organic light emitting diodde desplay device, the transistor in transistor in the cell array and the transistor in the scan drive circuit, the reset drives circuit is a polysilicon transistors.

Organic light emitting diodde desplay device according to a further aspect of the invention comprises: cell array, have multi-strip scanning line intersected with each other and many data lines, many are applied with high power supply voltage and provide line with supply voltage that data line be arranged in parallel, many the reset lines that be arranged in parallel with sweep trace, luminous Organic Light Emitting Diode under a plurality of high power supply voltage effects that line is provided at supply voltage, according to the OLED driver circuit from the data-driven Organic Light Emitting Diode of data line, and this OLED driver circuit response is from the reset signal initializes of reset line from the sweep signal of sweep trace in a plurality of responses; Utilizing each grade to have first pulls up transistor and a plurality of level of first pull-down transistor provides the scan drive circuits of sweep signal to sweep trace, first voltage that pulls up transistor response the one Q node provides sweep signal to sweep trace, and first pull-down transistor responds the voltage discharge sweep trace of a QB node; Utilizing each grade to have second pulls up transistor and a plurality of level of second pull-down transistor provides the reset drives circuit of reset signal to reset line, second voltage that pulls up transistor response the 2nd Q node provides reset signal to reset line, and second pull-down transistor responds the voltage discharge reduction line of the 2nd QB node; Be used for responding the first transistor of reset signal discharge scan drive circuit the one Q node; And the transistor seconds that is used for responding scanning signal discharge reduction driving circuit the 2nd Q node.

In organic light emitting diodde desplay device, OLED driver circuit comprises: be used for the responding scanning signal provides switching transistor from data to first node; Be used for driving transistors by the Control of Voltage Organic Light Emitting Diode streaming current of first node; And the reset transistor that is used to respond reset signal discharge first node.

In organic light emitting diodde desplay device, the transistor in transistor in the cell array and the transistor in the turntable driving, the reset drives circuit is a polysilicon transistors.

In organic light emitting diodde desplay device, a plurality of level of scan drive circuit comprises the n-1 level, in response to one of the wherein any output n-1 sweep signal (n is the integer more than or equal to 3) of enabling signal and n-2 sweep signal; And the n level, respond the n-1 sweep signal and export the n sweep signal; And wherein the n-1 level responds n sweep signal discharge a Q node and the QB node that charges.

In organic light emitting diodde desplay device, a plurality of level of reset drives circuit comprises: n-1 level, output n-1 reset signal (n is the integer more than or equal to 3) that one of response enabling signal and n-2 reset signal are wherein any; And the n level, respond n-1 level reset signal and export the n reset signal; And wherein the n-1 level is in response to n reset signal discharge the 2nd Q node and the 2nd QB node that charges.

In organic light emitting diodde desplay device, the first transistor has the source electrode that is connected to a Q node, be connected to the grid of reset line and be connected to the drain electrode of low-voltage source; Transistor seconds has the source electrode that is connected to the 2nd Q node, be connected to the grid of sweep trace and be connected to the drain electrode of low-voltage source.

Organic light emitting diodde desplay device comprises the 3rd transistor that is used to respond reset signal discharge sweep trace; With the 4th transistor that is used for responding scanning signal discharge reduction line.

In organic light emitting diodde desplay device, the 3rd transistor has the source electrode that is connected to sweep trace, be connected to the grid of reset line and be connected to the drain electrode of low-voltage source; The 4th transistor has the source electrode that is connected to reset line, be connected to the grid of sweep trace and be connected to the drain electrode of low-voltage source.

In organic light emitting diodde desplay device, reset line is connected to each other together and applies reset signal simultaneously thereon; Reset line after interconnecting generally is connected to the grid that is formed at respectively in a plurality of the first transistors; Sweep trace is connected to the grid of transistor seconds with man-to-man relation.

In organic light emitting diodde desplay device, the quantity of the level of reset drives circuit is less than the quantity of the level of scan drive circuit.

In organic light emitting diodde desplay device, reset line is connected to each other together and applies reset signal simultaneously thereon; Reset line after interconnecting generally is connected to the grid that is formed at respectively in a plurality of the 3rd transistors; Sweep trace is connected to the 4th transistorized grid with man-to-man relation.

In organic light emitting diodde desplay device, the quantity of the level of reset drives circuit is less than the quantity of scan drive circuit level.

Organic light emitting diodde desplay device according to a further aspect of the present invention comprises: cell array, have multi-strip scanning line intersected with each other and many data lines, many are applied with high power supply voltage and provide line with supply voltage that data line be arranged in parallel, many the reset lines that be arranged in parallel with sweep trace, luminous Organic Light Emitting Diode under a plurality of high power supply voltage effects that line is provided at supply voltage, according to the OLED driver circuit from the data-driven Organic Light Emitting Diode of data line, and this OLED driver circuit response is from the reset signal initializes of reset line from the sweep signal of sweep trace in a plurality of responses; Utilizing each grade to have first pulls up transistor and a plurality of level of first pull-down transistor provides the scan drive circuits of sweep signal to sweep trace, first voltage that pulls up transistor response the one Q node provides sweep signal to sweep trace, and first pull-down transistor responds QB node voltage discharge sweep trace; Utilizing each grade to have second pulls up transistor and reset drives circuit that a plurality of level of second pull-down transistor provides reset signal to arrive reset line, second voltage that pulls up transistor response the 2nd Q node provides reset signal to reset line, and second pull-down transistor responds the voltage discharge reduction line of the 2nd QB node; Be used to respond the first transistor of reset signal discharge sweep trace; And the transistor seconds that is used for sweep signal discharge reduction line.

In organic light emitting diodde desplay device, OLED driver circuit comprises: be used for the responding scanning signal provides switching transistor from data to first node; Be used for driving transistors by the Control of Voltage Organic Light Emitting Diode streaming current of first node; And the reset transistor of response reset signal discharge first node.

In organic light emitting diodde desplay device, a plurality of levels of reset drives letter circuit comprise the n-1 level, output n-1 reset signal (n is the integer more than or equal to 3) that one of response enabling signal and n-2 reset signal are wherein any; And the n level, respond n-1 level reset signal and export the n reset signal; And wherein the n-1 level is in response to n reset signal discharge the 2nd Q node and the 2nd QB node that charges.

In organic light emitting diodde desplay device, the first transistor has the source electrode that is connected to sweep trace, be connected to the grid of reset line and be connected to the drain electrode of low-voltage source; Transistor seconds has the source electrode that is connected to reset line, be connected to the grid of sweep trace and be connected to the drain electrode of low-voltage source.

Description of drawings

These and other purposes of the present invention with reference to the accompanying drawings, will obtain clear the elaboration from following detailed description to embodiment of the present invention, wherein:

Fig. 1 is the figure of explanation prior art organic light emitting diodde desplay device;

Fig. 2 is the figure of key diagram 1 OLED driver circuit drive waveforms;

Fig. 3 is the figure of the relation of explanation gate bias stress and voltage application time;

Fig. 4 A is the figure that the device property variation that is caused by positive gate bias stress is described;

Fig. 4 B is the figure that the device property variation that is caused by the negative-grid bias stress is described;

Fig. 5 is the block diagram according to first embodiment of the invention OLED display device;

Fig. 6 is the oscillogram of the I/O waveform of OLED display device shown in Figure 5;

Fig. 7 is the figure that reduces according to gate bias stress in the OLED display device of embodiment of the present invention;

Fig. 8 is the detailed diagram of first embodiment of scan drive circuit shown in Figure 5 and reset drives circuit;

Fig. 9 is the block diagram according to the OLED display device of second embodiment of the invention;

Figure 10 is the detailed diagram of second embodiment of scan drive circuit shown in Fig. 5 or 9 and reset drives circuit;

Figure 11 is the circuit diagram that describes first embodiment of scan drive circuit shown in Figure 10 and reset drives circuit in detail;

Figure 12 is the circuit diagram that describes second embodiment of scan drive circuit shown in Figure 10 and reset drives circuit in detail;

Figure 13 is the circuit diagram that describes the 3rd embodiment of scan drive circuit shown in Figure 10 and reset drives circuit in detail;

Figure 14 is the block diagram that describes the 3rd embodiment of scan drive circuit shown in Fig. 9 and reset drives circuit in detail;

Figure 15 is the circuit diagram that describes first embodiment of scan drive circuit shown in Figure 14 and reset drives circuit in detail;

Figure 16 is the circuit diagram that describes second embodiment of scan drive circuit shown in Figure 14 and reset drives circuit in detail; And

Figure 17 is the circuit diagram that describes the 3rd embodiment of scan drive circuit shown in Figure 14 and reset drives circuit in detail.

Embodiment

Below in detail with reference to preferred implementation of the present invention, embodiment wherein is shown in the drawings.

Below with reference to Fig. 5 to 17 explanation embodiments of the present invention.

With reference to Fig. 5, comprise having n * m the pixel P[i that in pixel area, arranges, j with n * m matrix type according to the OLED display device of embodiment of the present invention], pixel area is limited to the Dm intersection to Gn and m bar data line D1 by n bar sweep trace G1; M bar supply voltage provide line S1 to Sm to each pixel P[i, j] high power supply voltage VDD is provided, and be arranged in parallel to Dm with data line D1; Reset line R1 is to Rn, with sweep trace G1 to Gn be arranged in parallel and to each pixel P[i, j] reset signal is provided; Scan drive circuit 102 is used for driven sweep line G1 to Gn; Reset drives circuit 106 is used to drive reset line R1 to Rn; And data drive circuit 101, be used for driving data lines D1 to Dm.

Scan drive circuit 102 and reset drives circuit 106 are formed on the substrate with cell array, and wherein the data line D1 that comprises of cell array provides line S1 to Sm and pixel P[i, j to Dm, sweep trace G1 to Gn, supply voltage] all be formed on this substrate.

Scan drive circuit 102 comprises that one is shifted sweep signal with the shift register of output successively at each horizontal cycle, and provides sweep signal to sweep trace G1 to Gn successively.

Reset drives circuit 106 comprises a shift register, and it is shifted with output to reset signal, and provides reset signal to reset line R1 to Rn successively.Reset drives circuit 106 is formed on one side relative with scan drive circuit 102, has pixel region 108 between the two.

Scan drive circuit 102 and reset drives circuit 106 comprise the transistor of a plurality of employing amorphous silicons (a-Si), adopt the identical mode of transistor with the TFT of cell array, thereby they can be formed on the identical substrate together with cell array.On the other hand, if the TFT transistor of cell array is formed by polysilicon, the TFT transistor of scan drive circuit and reset drives circuit also is to be formed by polysilicon so.

By this way, scan drive circuit 102 and reset drives circuit 106 are formed in the oled panel 103 with cell array with the embedding form, therefore, and the cost minimization of circuit and no longer need the operation that forms circuit or adhere to the cell array substrate.

Data drive circuit 101 will become analog data voltage from the digital data conversion of outside input.And data drive circuit 101 when sweep signal is provided to data line D1 to the Dm analog data voltage.

When sweep signal is applied to sweep trace G1 to Gn, each pixel P[i, j] receive data voltage from data line D1 to Dm, send the light corresponding, and comprising pixel P[i, j with data voltage] pixel area 108 in Show Picture.

For this purpose, each P[i, j] pixel comprises having the OLED that the anode that line S1 links to each other to Sm is provided with supply voltage, and OLED driving circuit 105, driving circuit 105 be connected to sweep trace G1 to Gn, data line D1 to Dm, reset line R1 is applied with low supply voltage VSS to Rn, on it.

OLED driving circuit 105 comprises and is used for the sweep signal to Gn in response to sweep trace G1, will be applied to the first transistor T1 of first node N1 from data line D1 to the data voltage of Dm; Be used for transistor seconds T2 in response to the Control of Voltage OLED current amount flowing of first node N1; With in response to the 3rd transistor T 3 that to the reset signal of Rn first node is discharged from reset line R1.First to the 3rd transistor T 1 is formed by amorphous silicon to T3.

The drive waveforms of OLED driving circuit 105 as shown in Figure 6.In Fig. 6, ' 1F ' is a frame period, ' 1H ' is a horizontal cycle, ' Vg_i ' is the gate voltage that provides from i sweep trace Gi, and ' Psc ' is sweep signal, and ' Vd_j ' is the data voltage that provides from j data line Dj, ' Vr_i ' is the resetting voltage that provides from i reset line Ri, ' Prs ' is reset signal, and ' VN1 ' is voltage and the ' I of first node N1 _OLED' be the electric current that flows through OLED.

In the OLED driving element, when sweep signal i sweep trace is applied on it, the first transistor T1 conducting, thus will be provided to first node N1 from the data voltage Vd_j of j data line.The data voltage Vd_j that is provided to first node N1 is applied to the grid of transistor seconds T2.If in this manner under the effect of the data voltage Vd_j that provides, transistor seconds T2 conducting, electric current flows through OLED so.Simultaneously, under the effect of high power supply voltage VDD, produce the electric current flow through OLED, and the magnitude of current is directly proportional with the voltage magnitude of data voltage Vd_j on being applied to transistor seconds T2.In addition, even the first transistor T1 ends, transistor seconds T2 keeps conducting state under the effect of the data voltage of floating on the first node N1, and the conducting under of the 3rd transistor T 3, thereby make transistor seconds T2 keep conducting state to discharge up to first node N1 from the reset signal Prs effect of i reset line Ri.Simultaneously, for each frame period, from the reset signal Prs of i reset line Ri than 1/2 frame period of scanning signal delay that will provide.

With than sweep signal Psc at interval under the effect of the reset signal Prs that produces of 1/2 frame period, the voltage of first node N1 is by 3 discharges of the 3rd transistor T, so transistor seconds T2 has the restore cycle of the drive cycle and 1/2 frame of 1/2 frame.That is to say that as shown in Figure 7, transistor seconds T2 gate bias stress of cumulative growth in the drive cycle of 1/2 frame reduced in the restore cycle of 1/2 frame.

In other words, the bias stress in field cycle was recovered in the later half frame period before the transistor seconds T2, thereby, prevented owing to transistor seconds the performance change that the i.e. degeneration of OLED driving element causes.Therefore, the reliability of raising OLED drive circuit works is possible.

On the other hand, in embodiment, the mistiming between sweep signal Psc and the reset signal Prs was interpreted as for 1/2 frame period, but the mistiming can be adjusted according to panel characteristics and TFT characteristic.

Fig. 8 brief description the structure of scan drive circuit 102 and the reset drives circuit 106 of said scanning signals Psc and reset signal Prs is provided.

With reference to figure 8, scan drive circuit 102 comprises a shift register that is connected in series and is formed by the n level.In shift register, first enabling signal Vst1 is input to the first order, and the output signal of previous stage be input to successively second to the n level as enabling signal.Further, each grade has identical circuit structure, and is shifted in response to the output signal of clock signal clk to enabling signal Vst1 or previous stage, produces to have the sweep signal that pulse width is approximately a horizontal cycle.The sweep signal of Chan Shenging is applied to sweep trace G1 successively to Gn by this way.

Reset drives circuit 106 comprises the shift register with scan drive circuit 102 basic identical circuit structures, and provide reset signal to reset line R1 to Rn successively, reset signal is in the downward sweep signal that is later than of effect of the second enabling signal Vst2 that produces with the time that postpones about 1/2 frame period than the first enabling signal Vst1.In this manner, there is the mistiming that produces by the mistiming between the first enabling signal Vst1 and the second enabling signal Vst2 between aforementioned sweep signal and the reset signal.That is to say, can be by the operating cycle and the restore cycle of control enabling signal Vst1 and Vst2 control OLED driving element.

In Fig. 8, two two phase clocks of clock signal clk employing that are applied to scan drive circuit 102 and reset drives circuit 106 are example, but clock signal can be known three phase clock, four phase clocks or higher phase clock.And scan drive circuit 102 can be driven by identical clock signal with reset drives circuit 106, perhaps drives in response to the clock signal that differs from one another.

In the embodiment shown in Figure 5, each pixel P[i, j] OLED driving circuit 105 be connected to the negative electrode of OLED, but also may form a kind of structure of anode that OLED driving circuit 107 is connected to OLED.

Figure 10 is the block diagram that describes second embodiment of scan drive circuit shown in Fig. 5 or 9 and reset drives circuit in detail.

With reference to Figure 10, each comprises n the level (the 1st grade to the n level) that is connected in series scan drive circuit 102 and reset drives circuit 106.

In scan drive circuit 102, the first enabling signal Vst1 is input to the first order, and previous stage sweep signal Vg_i-1 be input to the 2nd to the n level as enabling signal.And next stage sweep signal Vg_i+1 is input to first to (n-1) level conduct level reset signal, and the level reset signal of coming from the vitual stage (not shown) is input to the n level.And, each grade has identical circuit structure basically, and in response to arbitrary clock signal in four clock signal C 1 to C4, the first enabling signal Vst1 or previous stage sweep signal Vg_I is shifted, therefore, produce the sweep signal of pulse width with a horizontal cycle.

The second enabling signal Vst2 is more late than first enabling signal Vst1 generation.Correspondingly, reset signal is than being applied to the scanning signal delay schedule time of sweep trace G1 to Gn.

With reference to Figure 11, scan drive circuit 102 comprises in response to coming from the reset signal Vr_1 of reset line R1 to Rn makes the first transistor T1 of the first order 201 to the Q node discharge of n level 20n to Vr_n, and reset drives circuit 106 comprises in response to making the transistor seconds T2 of the first order 601 to the Q node discharge of n level 60n from sweep trace G1 to the sweep signal Vg of Gn.

In scan drive circuit 102,, in level 201, carry out charging of Q node and QB node discharge so if enabling signal Vst1 is input to the set end S of the first order 201.Subsequently, first clock signal C 1 with high logic voltage is input to the first order 201 and the first order 201 is in its Q node when the state of charging, and the first sweep signal Vg_1 is applied to the first sweep trace G1 by (full-up) T-up that pulls up transistor.Simultaneously, the first sweep signal Vg_1 is applied to the set end S of the second level 202, the QB node of the Q node of the second level 202 of charging and the second level 202 of discharging.Further, the first sweep signal Vg_1 is applied on the grid of transistor seconds T2 of reset drives circuit 106.Therefore, by the first sweep signal Vg_1 conducting transistor seconds T2, the Q node of the first order 601 in the forced electric discharge reset drives circuit 106.

Subsequently, the second sweep signal Vg_2 by second clock signal C2 202 generations in the second level are applied to the second sweep trace G2, and are applied to the reset terminal R of the first order 201 simultaneously as the level reset signal.The Q node and the QB node that charges of the second sweep signal Vg_2 discharge first order 201.Therefore, when the second sweep signal Vg_2 produced, the first sweep trace G1 was by pull-down transistor (full-down) T_dn discharge.Further, the second sweep signal Vg_2 is applied to and is included in the reset drives circuit 106 grid of transistor seconds T2 in the second level 602.Therefore, by the second sweep signal Vg_2, conducting transistor seconds T2, the Q node of the second level 602 in the discharge reduction driving circuit 106.

In an identical manner, the 3rd sweep signal Vg_3 that exports from the third level 203 is applied to three scan line G3, and simultaneously as a level reset signal initializes second level 202.By this operation, scan drive circuit 102 applies the Q node of sweep signal and discharge reduction driving circuit 106 successively to Gn to sweep trace G1.

The reset operation of reset drives circuit 106 and aforementioned scan drive circuit 102 essentially identical modes are carried out.

In reset drives circuit 106,, in the first order 601, carry out charging of Q node and QB node discharge so if enabling signal Vst2 is input to the set end S of the first order 601.Subsequently, be under the charged state at the Q node, first clock signal C 1 with logic high voltage is applied to the first reset line R1 by the T-up that pulls up transistor as the first reset signal Vr_1.Simultaneously, the first reset signal Vr_1 is applied to the set end S of the second level 602, with the Q node of the charging second level 602 and the QB node of the second level 602 of discharging.Further, the first reset signal Vr_1 is applied on the grid of the first transistor T1.Therefore, by the first reset signal Vr_1, conducting the first transistor T1 is with the Q node of the first order in the forced electric discharge scan drive circuit 102 201.

Subsequently, the 602 second reset signal Vr_2 that produce are applied to the second reset line R2 in the second level by second clock signal C2, and are applied to the reset terminal R of the first order 601 simultaneously as the level reset signal.The Q node and the QB node that charges of the second reset signal Vr_2 discharge first order 601.Therefore, when the second reset signal Vr_2 produced, the first reset line R1 discharged by pull-down transistor T_dn.Further, the second reset signal Vr_2 is applied to the grid of the first transistor T1 that is included in the second level 202 in the scan drive circuit 102.Therefore, the Q node by the second level 202 in the second reset signal Vr_2 conducting the first transistor T1 forced electric discharge scan drive circuit 102.

In an identical manner, the 3rd reset signal Vr_3 that exports from the third level 603 is applied to the 3rd reset line R3, and simultaneously as a level reset signal initializes second level 602.By this operation, reset drives circuit 106 applies the Q node of sweep signal and discharge scan drive circuit 102 successively to Rn to reset line R1.

By this way, therefore the output forced electric discharge Q node of scan drive circuit 102 and reset drives circuit 106 another grades of usefulness, can prevent the OLED fault that is caused by the unusual electric charge of Q node and improve operational reliability.

Figure 12 is the circuit diagram that describes second embodiment of scan drive circuit shown in Figure 10 and reset drives circuit in detail.

With reference to Figure 12, scan drive circuit 102 comprises reset signal Vr_1 three transistor T 3 to Vr_n discharge sweep trace G1 to Gn of response reset line R1 to Rn, and reset drives circuit 106 comprises sweep signal Vg_1 four transistor T 4 to Vg_n reset line R1 to Rn of responding scanning line G1 to Gn.

The source electrode of the 3rd transistor T 3 is connected to sweep trace G1 to Gn, and its drain electrode is connected to low-voltage source VSS.And the grid of the 3rd transistor T 3 is connected to reset line R1 to Rn.

The source electrode of the 4th transistor T 4 is connected to reset line R1 to Rn, and its drain electrode is connected to low-voltage source VSS.And the grid of the 4th transistor T 4 is connected to sweep trace G1 to Gn.

In scan drive circuit 102,, in the first order 201, carry out charging of Q node and QB node discharge so if enabling signal Vst1 is input to the first order 201.If when the state of the Q of the first order 201 node, have a source electrode that high-tension first clock signal is applied to the T-up that pulls up transistor in charging, the first sweep signal Vg_1 is applied to the first sweep trace G1 so, the first sweep signal Vg_1 is applied to the set end S of the second level 202 as enabling signal simultaneously, thereby charges the Q node of the second level 202 and the QB node of the second level 202 of discharging.Further, the first sweep signal Vg_1 is applied on the grid that is connected to the 4th transistor T 4 on the first reset line R1 with the first reset line R1 that discharges.

Be applied to the second sweep trace G2 by second clock signal C2 at the second sweep signal Vg_2 that the second level 202 of scan drive circuit 102 produces, and be applied to the reset terminal R of the first order 201 simultaneously, thereby the Q node of the discharge first order 201 and the QB node of the first order 201 of charging.Therefore, if produce the second sweep signal Vg_2, the pull-down transistor T_dn of the first order 201 discharges into low supply voltage VSS with the first sweep trace G1, and the T_up conducting that pulls up transistor of the second level 202 simultaneously charges into the voltage of second clock signal C2 to sweep trace G2.Further, the second sweep signal Vg_2 is applied on the grid of the 4th transistor T 4 that is connected to the second reset line R2, with the second reset line R2 that discharges.

By this operation, scan drive circuit 102 applies sweep signal Vg_1 to Vg_n to sweep trace G1 to Gn successively, the previous stage of initialization simultaneously.Further, scan drive circuit 102 successively discharge reduction line R1 to Rn.

In reset drives circuit 106,, in the first order 601, carry out charging of Q node and QB node discharge so if enabling signal Vst2 is input to the first order 601.If when the state of the Q of the first order 601 node, have a source electrode that high-tension first clock signal is applied to the T-up that pulls up transistor in charging, the first reset signal Vr_1 is applied to the first reset line R1 so, and the first reset signal Vr_1 is applied to the set end S of the second level 602 as enabling signal simultaneously, thereby charges the Q node of the second level 602 and the QB node of the second level 602 of discharging.Further, the first reset signal Vr_1 is applied on the grid that is connected to the transistor seconds T2 on the first sweep trace G1 with the first sweep trace G1 that discharges.

Be applied to the second reset line R2 by second clock signal C2 at the second sweep signal Vg_2 that the second level 602 of reset drives circuit 106 produces, and be applied to the reset terminal R of the first order 601 simultaneously, thereby the Q node of the discharge first order 601 and the QB node of the first order 601 of charging.Therefore, if produce the second reset signal Vr_2, the pull-down transistor T_dn conducting of the first order 601 is to discharge into low supply voltage VSS with the first reset line R1, and the T_up conducting that pulls up transistor of the second level 602 is to charge into the voltage of second clock signal C2 at reset line R2 simultaneously.Further, the second reset signal Vr_2 is applied on the grid of the 3rd transistor T 3 that is connected to the second sweep trace G2 with the second sweep trace G2 that discharges.

By this operation, reset drives circuit 106 applies reset signal Vr_1 to Vr_n to reset line R1 to Rn successively, the previous stage of initialization simultaneously.Further, reset drives circuit 106 discharges sweep trace G1 successively to Gn.

With reference to Figure 13, scan drive circuit 102 comprises response from reset signal Vr_1 the first transistor T1 to the Vr_n discharge first order 201 to the Q node of n level 20n of reset line R1 to Rn, and three transistor T 3 of response reset signal Vr_1 to Vr_n discharge sweep trace G1 to Gn.

And, reset drives circuit 106 comprises response from the transistor seconds of sweep trace G1 to the sweep signal Vg of the Gn discharge first order 601 to the Q node of n level 60n, and response is from sweep signal Vg_1 four transistor T 4 to Vg_n discharge reduction line R1 to Rn of sweep trace G1 to Gn.

The source electrode of the first transistor T1 is connected to the first order 201 that is included in the scan drive circuit 102 Q node to n level 20n, and its drain electrode is connected to low-voltage source VSS.And the grid of the first transistor T1 is connected to reset line R1 to Rn.

The source electrode of transistor seconds T2 is connected to the first order 601 that is included in the reset drives circuit 106 Q node to n level 60n, and its drain electrode is connected to low-voltage source VSS.And the grid of transistor seconds T2 is connected to reset line R1 to Rn.

The source electrode of the 3rd transistor T 3 is connected to sweep trace G1 to Gn, and its drain electrode is connected to low-voltage source VSS.Simultaneously, the grid of the 3rd transistor T 3 is connected to reset line R1 to Rn.

Scan drive circuit 102 shown in Figure 13 and reset drives circuit 106 are embodiments that the circuit structure of scan drive circuit 102 shown in Figure 11 and Figure 12 and reset drives circuit 106 mixes.

In scan drive circuit 102,, in the first order 201, carry out charging of Q node and QB node discharge so if enabling signal Vst1 is input to the first order 201.If under the state of charging, have the source electrode that high-tension first clock signal is applied to the T-up that pulls up transistor at the Q of the first order 201 node, the first sweep signal Vg_1 is applied to the first sweep trace G1 so, and the first sweep signal Vg_1 is applied to the set end S of the second level 202 as enabling signal simultaneously, thereby charges the Q node of the second level 202 and the QB node of the second level 202 of discharging.Further, the first sweep signal Vg_1 makes the second and the 4th transistor T 2, the T4 conducting of the first order 601 that is connected to reset drives circuit 106, thus the Q node and the first reset line R1 that discharges of the discharge first order 601.

Be applied to the second sweep trace G2 by second clock signal C2 at the second sweep signal Vg_2 that the second level 202 at scan drive circuit 102 produces, and be applied to the reset terminal R of the first order 201 simultaneously, thereby the Q node of the discharge first order 201 and the QB node of the first order 201 of charging.Therefore, if produce the second sweep signal Vg_2, the pull-down transistor T_dn conducting of the first order 201 to be discharging into low supply voltage VSS with the first sweep trace G1, and the T_up conducting that pulls up transistor of the second level 202 simultaneously is to charge into the voltage of second clock signal C2 to the second sweep trace G2.Further, the second sweep signal Vg_2 makes the second and the 4th transistor T 2, the T4 conducting of the second level 602 that is connected to reset drives circuit 206, thus the Q node and the second reset line R2 that discharges of the discharge second level 602.

By this operation, scan drive circuit 102 applies sweep signal Vg_1 to Vg_n to sweep trace G1 to Gn successively, the previous stage of initialization simultaneously.Further, in reset drives circuit 106 first order 601 Q node to the n level 60n discharge successively and simultaneously reset line R1 discharge successively to Rn.

In reset drives circuit 106,, in the first order 601, carry out charging of Q node and QB node discharge so if enabling signal Vst1 is input to the first order 601.If first clock signal that has a high logic voltage when the state of the Q of the first order 601 node in charging is applied to the source electrode of the T-up that pulls up transistor, the first reset signal Vr_1 is applied to the first reset line R1 so, and be applied to the set end S of the second level 602 simultaneously as enabling signal, thereby the Q node of the charging second level 602 and the QB node of the second level 602 of discharging.Further, the first reset signal Vr_1 makes the first and the 3rd transistor T 1, the T3 conducting of the first order 201 that is connected to scan drive circuit 102, thus the Q node and the first sweep trace G1 that discharges of the discharge first order 201.

Be applied to the second reset line R2 by second clock signal C2 at the second sweep signal Vg_2 that the second level 602 of reset drives circuit 106 produces, and be applied to the reset terminal R of the first order 601 simultaneously, thereby the Q node of the discharge first order 601 and the QB node of the first order 601 of charging.Therefore, if produce the second reset signal Vr_2, the pull-down transistor T_dn of the first order 601 makes the first reset line R1 discharge into low supply voltage VSS, and the T_up conducting that pulls up transistor of the while second level 602 is to charge into the voltage of second clock signal C2 to the second reset line R2.Further, the second reset signal Vr_2 applies the first and the 3rd transistor T 1 of the second level 202 that is connected to second scan drive circuit 102, the grid of T3, thereby makes the first and the 3rd transistor T 1, the T3 conducting Q node and the second sweep trace G2 that discharges with the discharge second level 202.

By this operation, reset drives circuit 106 applies reset signal Vr_1 to Vr_n to reset line R1 to Rn successively, the previous stage of initialization simultaneously.Further, the first order 201 is discharged successively to the Q node of n level 20n in scan drive circuit 102, and sweep trace G1 is to Gn discharge simultaneously successively.

Figure 14 is the block diagram that describes the 3rd embodiment of scan drive circuit shown in Fig. 5 or 9 and reset drives circuit in detail.

With reference to Figure 14, reset drives circuit 306 applies reset signal to R1 two reset lines of adjacency in the Rn simultaneously, and comprises n/2 grade of the reset signal that is shifted successively.

The scan drive circuit 302 of this embodiment comprises n the level that applies sweep signal successively to sweep trace G1 to Gn.

Each scan drive circuit 302 and reset drives circuit 306 are realized by circuit shown in Figure 15 to 17.

With reference to Figure 15, scan drive circuit 302 comprise response odd number reset signal Vr_1, Vr_3 ..., Vr_ (n/2)-1, discharge (4k+1) (K is not less than 0 natural number) level 201,205 ..., the 11 transistor T 11 of the Q node of 20n-3; Response odd number reset signal Vr_1, Vr_3 ..., Vr_ (n/2)-1, discharge (4k+2) level 202,206 ..., the 13 transistor T 13 of the Q node of 20n-2; Response even number reset signal Vr_2, Vr_4 ..., Vr_ (n/2), discharge (4k+3) level 203,207 ..., the 14 transistor T 14 of the Q node of 20n-1; And response even number reset signal Vr_2, Vr_4 ..., Vr_ (n/2), discharge (4k+4) level 204,208 ..., the 15 transistor T 15 of the Q node of 20n;

Reset drives circuit 306 comprise response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1, discharge odd level 601,603 ..., the tenth two-transistor T12 of the Q node of 60n/2-1; And response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1, discharge even level 602,604 ..., the 15 transistor T 15 of the Q node of 60n/2.

In scan drive circuit 302,, in the first order 201, carry out charging of Q node and QB node discharge so if enabling signal Vst1 is input to the set end S of the first order 201.Subsequently, when first clock signal C 1 with high logic voltage is input to the first order 201 and the first order 201 when being in the state of its Q node in charging, the first sweep signal Vg_1 is applied to the first sweep trace G1 by the T-up that pulls up transistor.Simultaneously, the first sweep signal Vg_1 is applied to the set end S of the second level 202, the QB node of the Q node of the second level 202 of charging and the second level 202 of discharging.Further, the first sweep signal Vg_1 is applied on the grid of the tenth two-transistor T12 of reset drives circuit 306.Therefore, by the first sweep signal Vg_1, the Q node of the first order 601 in conducting the tenth two-transistor T12 forced electric discharge reset drives circuit 306.

Subsequently, the 202 second sweep signal Vg_2 that produce are applied to the second sweep trace G2 in the second level by second clock signal C2, and are applied to the reset terminal R of the first order 201 simultaneously as the level reset signal.The Q node and the QB node that charges of the second sweep signal Vg_2 discharge first order 201.Therefore, when the second sweep signal Vg_2 produced, the first sweep trace G1 was by pull-down transistor T_dn discharge.Be applied to three scan line G3 from the 3rd sweep signal Vg_3 of the third level 203 outputs, and simultaneously as the level reset signal initializes second level 202.And 15 conductings of the 15 transistor T are arranged in the Q node of reset drives circuit 306 second level 602 with discharge.By this operation, scan drive circuit 302 applies the Q node to Gn sweep signal and discharge reduction driving circuit 306 to sweep trace G1 successively.

In reset drives circuit 306,, in the first order 601, carry out charging of Q node and QB node discharge so if enabling signal Vst2 is input to the set end S of the first order 601.Subsequently, when Q node charged state, first clock signal C 1 with high logic voltage is applied on the first and second reset line R1 and the R2 by the T-up that pulls up transistor simultaneously as the first reset signal Vr_1.Simultaneously, charge the Q node of the second level 602 and the QB node of the second level 602 of discharging of the first reset signal Vr_1 set end S that is applied to the second level 602.Further, the first reset signal Vr_1 is applied on the grid of the 11 and the 13 transistor T 11 of scan drive circuit 302 and T13.Therefore, by the first reset signal Vr_1 conducting the 11 and the 13 transistor T 11, T13, thus in the discharge reduction driving circuit 302 first and second grade 201,202 Q node.

Subsequently, the 602 second reset signal Vr_2 that produce are applied to the third and fourth reset line R3, R4 in the second level by the 3rd clock signal C 3, and are applied to the reset terminal R of the first order 601 simultaneously as the level reset signal.The Q node and the QB node that charges of the second reset signal Vr_2 discharge first order 601.Therefore, when the second reset signal Vr_2 produced, the first reset line R1 discharged by pull-down transistor T_dn.Further, the second reset signal Vr_2 is applied to the grid of the 14 and the 15 transistor T 14, T15.Therefore, by third and fourth grade 203,204 Q node in the second reset signal Vr_2 conducting the 14 and the 15 transistor T 14, the T15 forced electric discharge scan drive circuit 302.

By this operation, reset drives circuit 306 applies reset signal and the Q node of the scan drive circuit 302 that discharges successively to reset line R1 to Rn successively.

With reference to Figure 16, scan drive circuit 302 comprise response odd number reset signal Vr_1, Vr_3 ..., Vr_ (n/2)-1, discharge (4k+1) (K is not less than 0 natural number) sweep trace G1, G5 ..., the 17 transistor T 17 of Gn-3; Response odd number reset signal Vr_1, Vr_3 ..., Vr_ (n/2)-1 discharge (4k+2) sweep trace G2, G6 ..., the 18 transistor T 18 of Gn-2; Response even number reset signal Vr_2, Vr_4 ..., Vr_ (n/2), discharge (4k+3) sweep trace G3, G7 ..., the 19 transistor T 19 of Gn-1; And response even number reset signal Vr_2, Vr_4 ..., Vr_ (n/2), discharge (4k+4) sweep trace G4, G8 ..., the 20 transistor T 20 of Gn.

Reset drives circuit 306 comprise response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1, discharge odd level 601,603 ..., the tenth two-transistor T12 of the Q node of 60n/2-1; Response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1, discharge (4k+1) and (4k+2) reset line R1, R2 ..., the 21 transistor T 21 of Rn-3, Rn-2; Response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1 discharge even level 602,604 ..., the 15 transistor T 15 of the Q node of 60n/2; And response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1, discharge (4k+3) and 4k reset line R3, R4 ..., the 20 two-transistor T22 of Rn-1, Rn.

In scan drive circuit 302,, in the first order 201, carry out charging of Q node and QB node discharge so if enabling signal Vst1 is input to the first order 201.If being in its Q node, the first order 201 has the source electrode that high-tension first clock signal is input to the T-up that pulls up transistor at the state of charging, then the first sweep signal Vg_1 is applied to the first sweep trace G1 and is applied to simultaneously the set end S of the second level 202 as enabling signal, thus the Q node of the charging second level 202 and the QB node of the second level 202 of discharging.Further, the first sweep signal Vg_1 is applied on the grid of the 12 and the 21 transistor T 12, T21 the Q node and the first and second reset line R1 and the R2 that discharge of the first order 601 in the discharge reduction driving circuit 306.

Be applied to the second sweep trace G2 by the second clock signal C2 second sweep signal Vg_2 that the second level 202 produces in scan drive circuit 302, and be applied to the reset terminal R of the first order 201 simultaneously, thus the Q node and the QB node that charges of the discharge first order 201.Therefore, if produce the second sweep signal Vg_2, the pull-down transistor T_dn conducting of the first order is so that the first sweep trace G1 discharges into low supply voltage VSS, and the T_up conducting that pulls up transistor of the while second level 202 is so that the second sweep trace G2 charges into the voltage of second clock signal C2.

Be applied to three scan line G3 from the 3rd sweep signal Vg_3 of the third level 203 outputs, simultaneously as the level reset signal initializes second level 202.And the 15 and the 20 two-transistor T15, T22 conducting are arranged in the Q node of reset drives circuit 306 second level 602 with discharge, and the discharge third and fourth reset line R3, R4.By this operation, scan drive circuit 302 apply successively sweep signal Vg_1 to Vg_n to sweep trace G1 to Gn and successively the Q node of discharge reduction driving circuit 306 and reset line R1 to Rn.

In the first order 601 of reset drives circuit 306,, in the first order 601, carry out charging of Q node and QB node discharge so if enabling signal Vst2 is input to the set end S of the first order 601.Subsequently, when Q node charged state, first clock signal C 1 with high logic voltage is applied on the first and second reset line R1 and the R2 as the first reset signal Vr_1 simultaneously by the T-up that pulls up transistor.Simultaneously, the first reset signal Vr_1 is applied to the set end S of the second level 602, thus the Q node of the charging second level 602 and the QB node of the second level 602 of discharging.Further, the first reset signal Vr_1 is applied on the grid of the 17 and the 18 transistor T 17 of scan drive circuit 302 and T18.Therefore, the 17 and the 18 transistor T 17, T18 are by the first reset signal Vr_1 conducting, with the first and second sweep trace G1, the G2 of discharging.

Subsequently, the 602 second sweep signal Vg_2 that produce are applied to the third and fourth reset line R3, R4 simultaneously in the second level by the 3rd clock signal C 3, and are applied to the reset terminal R of the first order 601 simultaneously as the level reset signal.The Q node of the second reset signal Vr_2 discharge first order 601 and the charging QB node of the first order 601.Therefore, when the second reset signal Vr_2 produced, the first reset line R1 was by pull-down transistor T_dn discharge.Further, the second reset signal Vr_2 is applied to the grid of the 19 and the 20 transistor T 19, T20.Therefore, by the second reset signal Vr_2, the 19 and the 20 transistor T 19, T20 conducting are with the forced electric discharge third and fourth sweep trace G3, G4.

By this operation, reset drives circuit 306 successively to reset line R1 to Rn/2 apply reset signal Vr_1 to Vr_n and discharge sweep trace G1 to Gn.

With reference to Figure 17, scan drive circuit 302 comprise response odd number reset signal Vr_1, Vr_3 ..., Vr_ (n/2)-1 discharge (4k+1) (K is not less than 0 natural number) level 201,205 ..., the 11 transistor T 11 of the Q node of 20n-3; Response odd number reset signal Vr_1, Vr_3 ..., Vr_ (n/2)-1 discharge (4k+2) level 202,206 ..., the 13 transistor T 13 of the Q node of 20n-2; Response odd number reset signal Vr_1, Vr_3 ..., Vr_ (n/2)-1 discharge (4k+1) sweep trace G1, G5 ..., the 17 transistor T 17 of Gn-3; Response odd number reset signal Vr_1, Vr_3 ..., Vr_ (n/2)-1 discharge (4k+2) sweep trace G2, G6 ..., the 18 transistor T 18 of Gn-2; In response to even number reset signal Vr_2, Vr_4 ..., Vr_n/2 discharge (4k+3) level 203,207 ..., the 14 transistor T 14 of the Q node of 20n-1; Response even number reset signal Vr_2, Vr_4 ..., Vr_n/2 discharge (4k+4) level 204,208 ..., the 15 transistor T 15 of the Q node of 20n; Response even number reset signal Vr_2, Vr_4 ..., Vr_n/2 discharge (4k+3) sweep trace G3, G7 ..., the 19 transistor T 19 of Gn-1; And response even number reset signal Vr_2, Vr_4 ..., Vr_n/2 discharge (4k+4) sweep trace G4, G8 ..., the 20 transistor T 20 of Gn.

Reset drives circuit 306 comprise response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1 discharge odd level 601,603 ..., the tenth two-transistor T12 of the Q node of 60n/2-1; Response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1 discharge (4k+1) and (4k+2) reset line R1, R2 ..., the 21 transistor T 21 of Rn-3, Rn-2; Response odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1 discharge even level 602,604 ..., the 15 transistor T 15 of the Q node of 60n/2; And in response to odd number sweep signal Vg_1, Vg_3 ..., Vg_ (n/2)-1 discharge (4k+3) and 4k reset line R3, R4 ..., the 20 two-transistor T22 of Rn-1.

In scan drive circuit 302,, in the first order 201, carry out charging of Q node and QB node discharge so if enabling signal Vst1 is input to the first order 201.If when the first order 201 is in its Q node at the state that charges, have the source electrode that high-tension first clock signal is input to the T-up that pulls up transistor, the first sweep signal Vg_1 is applied to the first sweep trace G1 by the T-up that pulls up transistor.Simultaneously, the first sweep signal Vg_1 is applied to the set end S of the second level 202 as enabling signal, thereby charges the Q node of the second level 202 and the QB node of the second level 202 of discharging.Further, the first sweep signal Vg_1 is applied on the grid of the 12 and the 21 transistor T 12, T21 the Q node and the first and second reset line R1 and the R2 that discharge of the first order 601 in the discharge reduction driving circuit 306.

Be applied to the second sweep trace G2 by second clock signal C2 at the second sweep signal Vg_2 that the second level 202 of scan drive circuit 302 produces, and be applied to the reset terminal R of the first order 201 simultaneously, thereby the Q node of the discharge first order 201 and the charging QB node of the first order 201.Therefore, if produce the second sweep signal Vg_2, the pull-down transistor T_dn conducting of the first order 201 is so that the first sweep trace G1 discharges into low supply voltage VSS, and the T_up conducting that pulls up transistor of the while second level 202 is so that the second sweep trace G2 charges into the voltage of second clock signal C2.

Be applied to three scan line G3 from the 3rd sweep signal Vg_3 of the third level 203 outputs, and simultaneously as the level reset signal initializes second level 202.And the 15 and the 20 two-transistor T15, T22 conducting are arranged in the Q node of reset drives circuit 306 second level 602 with discharge, and the discharge third and fourth reset line R3, R4.By this operation, scan drive circuit 302 successively to sweep trace G1 to Gn apply sweep signal Vg_1 to Vg_n and successively the Q node of discharge reduction driving circuit and reset line R1 to Rn.

In the first order 601 of reset drives circuit 306,, in the first order 601, carry out charging of Q node and QB node discharge so if enabling signal Vst2 is input to the set end S of the first order 601.Subsequently, when Q node charged state, first clock signal C 1 with high logic voltage is applied on the first and second reset line R1 and the R2 as the first reset signal Vr_1 simultaneously by the T-up that pulls up transistor.Simultaneously, the first reset signal Vr_1 is applied to the set end S of the second level 602, thus the Q node of the charging second level 602 and the QB node of the second level 602 of discharging.Further, the first reset signal Vr_1 is applied on the grid of the 11, the 13, the 17 and the 18 transistor T 11, T13, T17 and T18 of scan drive circuit 302.Therefore, the 11, the 13, the 17 and the 18 transistor T 11, T13, T17 and T18 are by the first reset signal Vr_1 conducting, with first and second grade 201,202 Q node in the discharge scan drive circuit 302, and the discharge first and second sweep trace G1, G2.

Subsequently, the 602 second reset signal Vr_2 that produce are applied to the third and fourth reset line R3, R4 simultaneously in the second level by the 3rd clock signal C 3, and are applied to the reset terminal R of the first order 601 simultaneously as the level reset signal.The Q node of the second reset signal Vr_2 discharge first order 601 and the QB node of the first order 601 of charging.Therefore, when the second reset signal Vr_2 produced, the first reset line R1 discharged by pull-down transistor T_dn.Further, the second reset signal Vr_2 is applied to the grid of the 14, the 15, the 19 and the 20 transistor T 14, T15, T19, T20.Therefore, by the second reset signal Vr_2 the 14, the 15, the 19 and the 20 transistor T 14, T15, T19, T20 conducting, thereby in the forced electric discharge scan drive circuit 302 third and fourth grade 203,204 Q node, and forced electric discharge the 3rd, the 4th sweep trace G3, G4 simultaneously.

By this operation, reset drives circuit 306 applies reset signal Vr_1 to Vr_n to reset line R1 to Rn/2 successively, and the Q node of the scan drive circuit 302 that discharges successively and discharge sweep trace G1 are to Gn.

In sum, can be by preventing to guarantee the operational reliability of OLED driving circuit according to OLED display device of the present invention by the characteristic variations that OLED driving element especially transistor degradation causes, and realize reducing cost and making the advantage of thinning by in organic LED panel, embedding scan drive circuit and reset drives circuit.

Further, according to OLED display device of the present invention, the output of the driving circuit that differs from one another by utilization, discharge line by line the Q node of scan drive circuit, Q node, sweep trace and the reset line of reset drives circuit, thus solve owing in the driving process, produce the problem that driving circuit reliability that partial charge causes is degenerated.

Although described the present invention by embodiment shown in the drawings, but for will be understood by those skilled in the art that, the present invention is not limited in these embodiments, and comprise those various modification that do not break away from spiritual scope of the present invention and when changing, therefore, scope of the present invention is only by appended claim and the decision of their equivalent.

Claims

1, a kind of organic light emitting diodde desplay device comprises:

Cell array, have multi-strip scanning line intersected with each other and many data lines, a plurality of be applied with high power supply voltage and with supply voltage that data line be arranged in parallel provide reset line that line, many and sweep trace be arranged in parallel, a plurality of supply voltage provide light emitting diode luminous under the high power supply voltage effect of line and a plurality of response from the sweep signal of sweep trace according to OLED driver circuit from the data-driven Organic Light Emitting Diode of data line, and this OLED driver circuit response is from the reset signal initializes of reset line;

Be used for providing the scan drive circuit of sweep signal to sweep trace;

Be used for being provided for the reset drives circuit of the reset signal of initialization OLED driver circuit to reset line; And

Be used for providing to data line respectively the data drive circuit of data,

And wherein, scan drive circuit and reset drives circuit are positioned on the substrate that is formed with cell array.

2, organic light emitting diodde desplay device according to claim 1 is characterized in that, described cell array places between scan drive circuit and the reset drives circuit.

3, organic light emitting diodde desplay device according to claim 2 is characterized in that, described OLED driver circuit comprises:

Being used for the responding scanning signal provides the switching transistor of data to first node;

Be used for driving transistors by the Control of Voltage Organic Light Emitting Diode streaming current of described first node; And

Be used to respond the reset transistor of the described first node discharge of reset enable signal.

4, organic light emitting diodde desplay device according to claim 3 is characterized in that, described reset signal postpones in sweep signal.

5, organic light emitting diodde desplay device according to claim 4 is characterized in that, described reset signal about 1/2 frame period behind the self-scanning signal produces.

6, organic light emitting diodde desplay device according to claim 3 is characterized in that, the transistor in transistor in the described cell array and the transistor in the scan drive circuit, the reset drives circuit is the amorphous silicon transistor.

7, organic light emitting diodde desplay device according to claim 3 is characterized in that, the transistor in transistor in the described cell array and the transistor in the scan drive circuit, the reset drives circuit is a polysilicon transistors.

8, a kind of organic light emitting diodde desplay device comprises:

Cell array, have multi-strip scanning line intersected with each other and many data lines, many be applied with high power supply voltage and with supply voltage that data line be arranged in parallel provide reset line that line, many and sweep trace be arranged in parallel, a plurality of Organic Light Emitting Diode luminous under the high power supply voltage effect that line is provided from supply voltage, a plurality of response from the sweep signal of sweep trace according to OLED driver circuit from the data-driven Organic Light Emitting Diode of data line, and this OLED driver circuit response is from the reset signal initializes of reset line;

Be used to utilize a plurality of levels that the scan drive circuit of sweep signal is provided to sweep trace, each level has first and pulls up transistor and first pull-down transistor, the described voltage that pulls up transistor response the one Q node provides sweep signal to sweep trace, and described pull-down transistor responds the voltage discharge sweep trace of a QB node;

Being used to utilize each grade to have first pulls up transistor and a plurality of levels of second pull-down transistor provide the reset drives circuit of reset signal to reset line, the described voltage that pulls up transistor response the 2nd Q node provides second of reset signal to pull up transistor to reset line, and described second pull-down transistor responds the voltage discharge reduction line of the 2nd QB node;

Be used to respond the first transistor of a described Q node of reset signal discharge scan drive circuit; And

The transistor seconds that is used for described the 2nd Q node of responding scanning signal discharge reduction driving circuit.

9, organic light emitting diodde desplay device according to claim 8 is characterized in that, described cell array places between scan drive circuit and the reset drives circuit.

10, organic light emitting diodde desplay device according to claim 9 is characterized in that, described OLED driver circuit comprises:

Be used for ringing the respective scanned signal provides switching transistor from data to first node;

Be used to respond the discharge reset transistor of described first node of reset signal.

11, organic light emitting diodde desplay device according to claim 10 is characterized in that, described reset signal postpones in sweep signal.

12, organic light emitting diodde desplay device according to claim 11 is characterized in that, described reset signal about 1/2 frame period behind the self-scanning signal produces.

13, organic light emitting diodde desplay device according to claim 10 is characterized in that, the transistor in transistor in the described cell array and the transistor in the scan drive circuit, the reset drives circuit is the amorphous silicon transistor.

14, organic light emitting diodde desplay device according to claim 10 is characterized in that, the transistor in transistor in the described cell array and the transistor in the scan drive circuit, the reset drives circuit is a polysilicon transistors.

15, organic light emitting diodde desplay device according to claim 10 is characterized in that, a plurality of levels in the described scan drive circuit comprise:

The n-1 level, in response to one of the wherein any output n-1 sweep signal of enabling signal and n-2 sweep signal, wherein n is the integer more than or equal to 3; And

The n level responds the n-1 sweep signal and exports the n sweep signal;

And wherein the n-1 level responds n sweep signal discharge a Q node and the QB node that charges.

16, organic light emitting diodde desplay device according to claim 15 is characterized in that, a plurality of levels of described reset drives circuit comprise:

The n-1 level, output n-1 reset signal that one of response enabling signal and n-2 reset signal is wherein any, wherein n is the integer more than or equal to 3; And

The n level responds n-1 level reset signal and exports the n reset signal;

And wherein the n-1 level is in response to n reset signal discharge the 2nd Q node and the 2nd QB node that charges.

17, organic light emitting diodde desplay device according to claim 8 is characterized in that, described the first transistor has the source electrode that is connected to a described Q node, be connected to the grid of reset line and be connected to the drain electrode of low-voltage source; And transistor seconds has the source electrode that is connected to the 2nd Q node, be connected to the grid of sweep trace and be connected to the drain electrode of low-voltage source;

18, organic light emitting diodde desplay device according to claim 8 is characterized in that, comprises

Be used to respond the 3rd transistor of reset signal discharge sweep trace; And

The 4th transistor that is used for responding scanning signal discharge reduction line.

19, organic light emitting diodde desplay device according to claim 18 is characterized in that, described the 3rd transistor has the source electrode that is connected to sweep trace, be connected to the grid of reset line and be connected to the drain electrode of low-voltage source; And described the 4th transistor has the source electrode that is connected to reset line, be connected to the grid of sweep trace and be connected to the drain electrode of low-voltage source.

20, organic light emitting diodde desplay device according to claim 17 is characterized in that, described reset line is connected to each other and provides reset signal to described reset line simultaneously; Reset line after the connection is typically connected to the grid that is formed at respectively in a plurality of the first transistors; And sweep trace is connected to the grid of transistor seconds with man-to-man relation.

21, organic light emitting diodde desplay device according to claim 20 is characterized in that, the quantity of the level of described reset drives circuit is less than the quantity of the level of described scan drive circuit.

22, organic light emitting diodde desplay device according to claim 19 is characterized in that, described reset line is connected to each other together and reset signal provides on it simultaneously; Reset line after the connection is typically connected to the grid that is formed at respectively in a plurality of the 3rd transistors; And described sweep trace is connected to the 4th transistorized grid with man-to-man relation.

23, organic light emitting diodde desplay device according to claim 22 is characterized in that, the quantity of the level of described reset drives circuit is less than the quantity of the level of described scan drive circuit.

24, a kind of organic light emitting diodde desplay device comprises:

Cell array, have multi-strip scanning line intersected with each other and many data lines, many be applied with high power supply voltage and with supply voltage that data line be arranged in parallel provide reset line that line, many and sweep trace be arranged in parallel, a plurality of Organic Light Emitting Diode luminous under the high power supply voltage effect that line is provided from supply voltage, a plurality of response from the sweep signal of sweep trace according to OLED driver circuit from the data-driven Organic Light Emitting Diode of data line, and the response of described OLED driver circuit is from the reset signal initializes of reset line;

Being used to utilize each grade to have first pulls up transistor and a plurality of levels of first pull-down transistor provide the scan drive circuits of sweep signal to sweep trace, described first voltage that pulls up transistor response the one Q node provides sweep signal to sweep trace, and first pull-down transistor responds the voltage discharge sweep trace of a QB node;

Being used to utilize each grade to have second pulls up transistor and a plurality of levels of second pull-down transistor provide the reset drives circuit of reset signal to reset line, described second voltage that pulls up transistor response the 2nd Q node provides reset signal to reset line, and second pull-down transistor responds the voltage discharge reduction line of the 2nd QB node;

Be used to respond the first transistor of reset signal discharge sweep trace; And

The transistor seconds that is used for responding scanning signal discharge reduction line.

25, organic light emitting diodde desplay device according to claim 24 is characterized in that, described cell array places between scan drive circuit and the reset drives circuit.

26, organic light emitting diodde desplay device according to claim 25 is characterized in that, described OLED driver circuit comprises:

Be used to respond the reset transistor of reset signal discharge first node.

27, organic light emitting diodde desplay device according to claim 24 is characterized in that, described reset signal postpones in sweep signal.

28, organic light emitting diodde desplay device according to claim 27 is characterized in that, described reset signal about 1/2 frame period behind the self-scanning signal produces.

29, organic light emitting diodde desplay device according to claim 26 is characterized in that, the transistor in transistor in the described cell array and the transistor in the scan drive circuit, the reset drives circuit is the amorphous silicon transistor.

30, organic light emitting diodde desplay device according to claim 29 is characterized in that, the transistor in transistor in the described cell array and the transistor in the scan drive circuit, the reset drives circuit is a polysilicon transistors.

31, organic light emitting diodde desplay device according to claim 24 is characterized in that, a plurality of levels of described scan drive circuit comprise:

The n level responds the n-1 sweep signal and exports the n sweep signal;

32, organic light emitting diodde desplay device according to claim 31 is characterized in that, a plurality of levels of described reset drives circuit comprise:

The n level responds n-1 level reset signal and exports the n reset signal;

33, organic light emitting diodde desplay device according to claim 24 is characterized in that, described the first transistor has the source electrode that is connected to sweep trace, be connected to the grid of reset line and be connected to the drain electrode of low-voltage source; And described transistor seconds has the source electrode that is connected to reset line, be connected to the grid of sweep trace and be connected to the drain electrode of low-voltage source.

34, organic light emitting diodde desplay device according to claim 33 is characterized in that, described reset line is connected to each other together and reset signal provides on it simultaneously; Reset line after the connection is typically connected to the grid that is formed at respectively in a plurality of the first transistors; And described sweep trace is connected to the grid of transistor seconds with man-to-man relation.

35, organic light emitting diodde desplay device according to claim 34 is characterized in that, the quantity of the level of described reset drives circuit is less than the quantity of the level of described scan drive circuit.