CN109037206A - A kind of power device protection chip and preparation method thereof - Google Patents

Abstract

The invention provides a power device protection chip and a manufacturing method thereof, comprising: a substrate of the first conductivity type; a first epitaxial layer of the second conductivity type; a first buried layer of the first conductivity type and a substrate of the second conductivity type The second buried layer is formed in the first epitaxial layer; the second epitaxial layer of the first conductivity type; the first injection region of the first conductivity type and the second injection region of the second conductivity type are formed in the first conductivity type The upper surface of two epitaxial layers, and the first implantation region is connected to the second implantation region; the polysilicon layer penetrates the second epitaxial layer and is respectively connected to the first implantation region and the first buried layer a dielectric layer formed on the upper surface of the second epitaxial layer; a first electrode comprising a first part penetrating through the dielectric layer and extending to the second injection region and a second part formed on the surface of the dielectric layer ; The second electrode is formed on the lower surface of the substrate. The invention can improve device performance and reduce device cost.

Description

A power device protection chip and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a power device protection chip and a manufacturing method thereof.

Background technique

The power device protection chip is a solid-state semiconductor device specially designed to protect sensitive semiconductor devices from transient voltage surge damage. It has small clamping coefficient, small size, fast response, small leakage current and reliable High performance, so it has been widely used in voltage transient and surge protection. The low-capacitance power device protection chip is suitable for high-frequency circuit protection devices, because it can reduce the interference of parasitic capacitance on the circuit and reduce the attenuation of high-frequency circuit signals.

Electrostatic discharge, as well as other random voltage transients in the form of voltage surges, are commonly found in a variety of electronic devices. As semiconductor devices are increasingly miniaturized, high-density, and multi-functional, electronic devices are increasingly vulnerable to voltage surges, which can even cause fatal injuries. Voltage surges ranging from electrostatic discharge to lightning can induce transient current spikes. Power device protection chips are often used to protect sensitive circuits from surges. Based on different applications, the power device protection chip can protect the circuit by changing the surge discharge path and its own clamping voltage.

Currently commonly used power device protection chips, if bidirectional protection is required, multiple power device protection chips need to be connected in series or in parallel, which increases the device area and manufacturing cost.

Contents of the invention

Based on the above problems, the present invention proposes a power device protection chip and a manufacturing method thereof, which reduces the manufacturing cost of the power device protection chip while improving the performance of the power device protection chip.

In view of this, an embodiment of the present invention provides a power device protection chip on the one hand, and the power device protection chip includes:

a substrate of the first conductivity type;

a first epitaxial layer of a second conductivity type grown on the upper surface of the substrate;

The first buried layer of the first conductivity type and the second buried layer of the second conductivity type are formed in the first epitaxial layer, and at least part of the surfaces of the first buried layer and the second buried layer are exposed on the On the upper surface of the first epitaxial layer, the doping concentration of the second buried layer is higher than that of the first epitaxial layer;

A second epitaxial layer of the first conductivity type is formed on the upper surface of the first epitaxial layer, and the doping concentration of the first buried layer is higher than that of the second epitaxial layer;

A first injection region of the first conductivity type and a second injection region of the second conductivity type are formed on the upper surface of the second epitaxial layer, and the first injection region is connected to the second injection region, the The doping concentration of the first implanted region is higher than the doping concentration of the second epitaxial layer;

a polysilicon layer penetrating through the second epitaxial layer and connected to the first implanted region and the first buried layer respectively;

a dielectric layer formed on the upper surface of the second epitaxial layer;

a first electrode, comprising a first portion penetrating through the dielectric layer and extending to the second injection region and a second portion formed on the surface of the dielectric layer;

The second electrode is formed on the lower surface of the substrate and connected to the substrate.

Further, the doping concentration of the first implanted region is higher than that of the first buried layer.

Further, the doping concentration of the second buried layer is higher than the doping concentration of the second implanted region.

Further, the second buried layer is disposed opposite to the second implantation region.

Further, the first buried layer includes a first sub-buried layer and a second sub-buried layer respectively arranged on both sides of the second buried layer, and the first implanted region includes The first sub-implantation region and the second sub-implantation region on both sides, the polysilicon layer includes a first polysilicon layer connected to the first sub-buried layer and the first sub-implantation region, and a first polysilicon layer connected to the first sub-implantation region. The second polysilicon layer connected to the second sub-buried layer and the second sub-implantation region.

Another aspect of the embodiment of the present invention provides a method for manufacturing a power device protection chip, the method comprising:

growing a first epitaxial layer of a second conductivity type on the surface of a substrate of the first conductivity type;

A first buried layer of the first conductivity type and a second buried layer of the second conductivity type are formed in the first epitaxial layer, and at least part of the surfaces of the first buried layer and the second buried layer are exposed on the first buried layer. On the upper surface of an epitaxial layer, the doping concentration of the second buried layer is higher than that of the first epitaxial layer;

A second epitaxial layer of the first conductivity type is formed on the upper surface of the first epitaxial layer, and the doping concentration of the first buried layer is higher than that of the second epitaxial layer;

forming a first trench penetrating through the second epitaxial layer and extending to the first buried layer, and forming a second trench located on the upper side of the first trench and communicating with the first trench;

A first injection region of the first conductivity type and a second injection region of the second conductivity type are formed on the upper surface of the second epitaxial layer, and the first injection region is connected to the first injection region, and the first injection region is connected to the first injection region. The doping concentration of the implanted region is higher than the doping concentration of the second epitaxial layer;

forming a polysilicon layer connected to the first buried layer in the first trench and the second trench, and connecting the polysilicon layer to the first implantation region;

forming a dielectric layer on the upper surface of the second epitaxial layer;

forming a first electrode, the first electrode comprising a first portion penetrating through the dielectric layer and extending to the second injection region and a second portion formed on the surface of the dielectric layer;

A second electrode connected to the substrate is formed on the lower surface of the substrate.

Further, the doping concentration of the first implanted region is higher than that of the first buried layer.

Further, the doping concentration of the second buried layer is higher than the doping concentration of the second implanted region.

Further, the second buried layer is arranged opposite to the second injection region.

Further, the first buried layer includes a first sub-buried layer and a second sub-buried layer respectively arranged on both sides of the second buried layer, and the first implanted region includes The first sub-implantation region and the second sub-implantation region on both sides, the polysilicon layer includes a first polysilicon layer connected to the first sub-buried layer and the first sub-implantation region, and a first polysilicon layer connected to the first sub-implantation region. The second polysilicon layer connected to the second sub-buried layer and the second sub-implantation region.

The technical solution of the embodiment of the present invention grows the first epitaxial layer of the second conductivity type on the surface of the substrate of the first conductivity type; forms the first buried layer of the first conductivity type and the second epitaxial layer in the first epitaxial layer a second buried layer of conductivity type, and at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first buried layer The doping concentration of an epitaxial layer; a second epitaxial layer of the first conductivity type is formed on the upper surface of the first epitaxial layer, and the doping concentration of the first buried layer is higher than that of the second epitaxial layer Concentration; forming a first trench penetrating through the second epitaxial layer and extending to the first buried layer, and forming a second trench located on the upper side of the first trench and communicating with the first trench ; forming a first injection region of the first conductivity type and a second injection region of the second conductivity type on the upper surface of the second epitaxial layer, and connecting the first injection region to the first injection region, the first injection region The doping concentration of an implanted region is higher than the doping concentration of the second epitaxial layer; a polysilicon layer connected to the first buried layer is formed in the first trench and the second trench, and the The polysilicon layer is connected to the first injection region; a dielectric layer is formed on the upper surface of the second epitaxial layer; a first electrode is formed, and the first electrode includes penetrating through the dielectric layer and extending to the second epitaxial layer. The first part of the injection region and the second part formed on the surface of the dielectric layer; the second electrode connected to the substrate is formed on the lower surface of the substrate. The technical scheme of the invention reduces the difficulty of the device manufacturing process, greatly reduces the parasitic capacitance, and improves the protection characteristics and reliability of the device.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. Those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative efforts.

1 is a schematic flow diagram of a method for manufacturing a power device protection chip provided by an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of a power device protection chip provided by an embodiment of the present invention;

3 to 10 are structural schematic diagrams of steps in a method for manufacturing a power device protection chip provided by an embodiment of the present invention;

Fig. 11 is an equivalent circuit diagram of a power device protection chip structure provided by an embodiment of the present invention;

In the figure: 1. substrate; 2. first epitaxial layer; 3. first buried layer; 4. second buried layer; 5. second epitaxial layer; 6. first trench; 7. first implantation region; 8. The second injection region; 9. The second trench; 10. The polysilicon layer; 11. The dielectric layer; 12. The first electrode; 121. The first part; 122. The second part; 13. The second electrode; a1, the first electrode A diode; b1, the second diode; c1, the third diode; a2, the fourth diode; b2, the fifth diode; c2, the sixth diode.

Detailed ways

The invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

If the purpose is to describe the situation directly on another layer or another area, the expression "A is directly above B" or "A is above and adjacent to B" will be used herein. In the present application, "A is located directly in B" means that A is located in B, and A is directly adjacent to B, rather than A being located in a doped region formed in B.

In the present application, the term "semiconductor structure" refers to a general designation of the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

In the following, many specific details of the present invention, such as device structures, materials, dimensions, processing methods and techniques, are described for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.

Referring to the accompanying drawings, a method for manufacturing a power device protection chip will be described in detail below.

A power device protection chip provided by an embodiment of the present invention and a manufacturing method thereof will be described in detail below with reference to FIGS. 1 to 10 .

An embodiment of the present invention provides a method for manufacturing a power device protection chip. As shown in FIG. 1 and FIG. 2 , the method for manufacturing the power device protection chip includes:

Step S1: growing the first epitaxial layer 2 of the second conductivity type on the surface of the substrate 1 of the first conductivity type;

Step S2: forming a first buried layer 3 of the first conductivity type and a second buried layer 4 of the second conductivity type in the first epitaxial layer 2, and the first buried layer 3 and the second buried layer 4 At least part of the surface is exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2;

Step S3: forming a second epitaxial layer 5 of the first conductivity type on the upper surface of the first epitaxial layer 2, and the doping concentration of the first buried layer 3 is higher than that of the second epitaxial layer 5 ;

Step S4: forming a first trench 6 penetrating through the second epitaxial layer 5 and extending to the first buried layer 3 , and forming a trench located on the upper side of the first trench 6 and connected to the first trench 6 . Unicom's second groove 9;

Step S5: forming a first implantation region 7 of the first conductivity type and a second implantation region 8 of the second conductivity type on the upper surface of the second epitaxial layer 5, and connecting the first implantation region 7 to the first Implantation region 7, the doping concentration of the first implantation region 7 is higher than the doping concentration of the second epitaxial layer 5;

Step S6: forming a polysilicon layer 10 connected to the first buried layer 3 in the first trench 6 and the second trench 9, and combining the polysilicon layer 10 with the first implanted region 7 connect;

Step S7: forming a dielectric layer 11 on the upper surface of the second epitaxial layer 5;

Step S8: forming the first electrode 12, the first electrode 12 includes a first portion 121 penetrating through the dielectric layer 11 and extending to the second injection region 8 and a second portion 122 formed on the surface of the dielectric layer 11 ; Forming a second electrode 13 connected to the substrate 1 on the lower surface of the substrate 1 .

Specifically, the first conductivity type is one of P-type doping and N-type doping, and the second conductivity type is the other of P-type doping and N-type doping.

For the convenience of description, it is hereby explained that the first conductivity type can be N-type doped, so that the second conductivity type can be P-type doped; the first conductivity type can also be P-type doped, so that The second conductivity type is N-type doping. It can be understood that when the first conductivity type is P-type doped and the second conductivity type is N-type doped, the substrate 1, the first buried layer 3, the second epitaxial Both the layer 5 and the first implantation region 7 are P-type doped, and the first epitaxial layer 2 , the second buried layer 4 and the second implantation region 8 are all N-type epitaxial layers. When the first conductivity type is N-type doped and the second conductivity type is P-type doped, the substrate 1, the first buried layer 3, the second epitaxial layer 5 and the The first implanted region 7 is all N-type doped, and the first epitaxial layer 2 , the second buried layer 4 and the second implanted region 8 are all P-type epitaxial layers. In the following embodiments, the first conductivity type is P-type doping and the second conductivity type is N-type doping as an example for description, but this is not limited thereto.

Specifically, both the P-type substrate and the P-type epitaxy belong to the P-type semiconductor, and the N-type substrate and the N-type epitaxy both belong to the N-type semiconductor. The P-type semiconductor is a silicon wafer doped with a trivalent element, such as boron element, indium element, aluminum element or any combination of the three. The N-type semiconductor is a silicon wafer doped with pentavalent elements, such as phosphorus or arsenic or any combination thereof.

Referring to FIG. 3 , step S1 is executed, specifically: growing a first epitaxial layer 2 of a second conductivity type on the surface of a substrate 1 of a first conductivity type. Wherein, the method of growing the first epitaxial layer 2 of the second conductivity type on the upper surface of the substrate 1 of the first conductivity type is not limited to a fixed method, it can be formed by epitaxial growth on the upper surface of the substrate 1, or The first epitaxial layer 2 is formed on the upper surface of the substrate 1 by means of ion implantation and/or diffusion. Further, the upper surface of the substrate 1 can be formed by epitaxial growth, and the upper surface of the substrate 1 can also be formed by ion implantation and/or diffusion of phosphorus or arsenic or any combination of the two. The first epitaxial layer 2 . Specifically, the method of epitaxy or diffusion includes a deposition process. In some embodiments of the present invention, the first epitaxial layer 2 can be formed on the upper surface of the substrate 1 using a deposition process, for example, the deposition process can be selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, One of a kind in sputtering. Preferably, the first epitaxial layer 2 is formed on the substrate 1 by chemical vapor deposition, and the chemical vapor deposition includes a vapor phase epitaxy process. In production, chemical vapor deposition mostly uses a vapor phase epitaxy process, and a vapor phase epitaxy process is used to form the first epitaxial layer 2 on the upper surface of the substrate 1. The vapor phase epitaxy process can improve the perfection of silicon materials, improve the integration of devices, and achieve Improve the minority carrier lifetime and reduce the leakage current of the storage unit. Preferably, the first epitaxial layer 2 and the substrate 1 are both made of silicon material, so that the substrate 1 and the first epitaxial layer 2 have silicon surfaces with the same crystal structure, thereby maintaining the resistance to impurity types and concentration control. In addition, the first epitaxial layer 2 reduces the series resistance while optimizing the breakdown voltage of the PN junction, and improves the device speed under moderate current intensity.

Please refer to FIG. 4, step S2 is performed, specifically: forming a first buried layer 3 of the first conductivity type and a second buried layer 4 of the second conductivity type in the first epitaxial layer 2, and the first At least part of the surfaces of the buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2 , and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2 . The first buried layer 3 and the second buried layer 4 can be formed by epitaxial growth, and can also be formed by ion implantation and/or diffusion. Further, the first buried layer 3 may be formed by epitaxial growth, or by ion implantation and/or diffusion of phosphorus element or arsenic element or any combination thereof. Similarly, the second buried layer 4 can be formed by epitaxial growth, and can also be formed by ion implantation and/or diffusion of boron element or indium element or aluminum element or any combination of the three. Preferably, the first buried layer 3 and the second buried layer 4 can be formed by ion implantation, and the formation of the first buried layer 3 and the second buried layer 4 by ion implantation can precisely control the concentration of impurities The total dose, depth distribution and surface uniformity can prevent the re-diffusion of original impurities, etc. At the same time, self-alignment technology can be realized to reduce the capacitance effect. In some embodiments of the present invention, at least part of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, that is, the first buried layer 3 and the The upper surface of the second buried layer 4 is exposed to the first epitaxial layer 2 .

Please refer to FIG. 5, step S3 is performed, specifically: forming a second epitaxial layer 5 of the first conductivity type on the upper surface of the first epitaxial layer 2, and the doping concentration of the first buried layer 3 is higher than the specified The doping concentration of the second epitaxial layer 5 is described above. Wherein, the method of forming the second epitaxial layer 5 of the first conductivity type on the upper surface of the first epitaxial layer 2 is not limited to a fixed method, and the second epitaxial layer 5 can be formed by means of epitaxy, diffusion and/or implantation. Layer 5, specifically, the method of epitaxy or diffusion includes a deposition process. Further, the second epitaxial layer 5 may be formed by means of epitaxy, diffusion and/or implantation of phosphorus or arsenic or any combination thereof. In some embodiments of the present invention, a deposition process is used to form the second epitaxial layer 5 on the upper surface of the first epitaxial layer 2, for example, the deposition process may be selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering One of a kind. Wherein, the chemical vapor deposition includes a vapor phase epitaxy process. Preferably, a vapor phase epitaxy process is used to form the second epitaxial layer 5 on the upper surface of the first epitaxial layer 2. The vapor phase epitaxy process can improve the perfection of the silicon material and improve the integration of the device. , to improve the minority carrier lifetime and reduce the leakage current of the storage unit. The second epitaxial layer 5 covers the upper surface of the first epitaxial layer 2 and has a certain thickness.

Further, the doping concentration of the first buried layer 3 is different from that of the second epitaxial layer 5 . Preferably, the doping concentration of the first buried layer 3 is higher than the doping concentration of the second epitaxial layer 5, and the first buried layer 3 is heavily doped, so that the first buried layer 3 The resistivity is lower than the resistivity of the second epitaxial layer 5, and the current will go to the lower side of the first epitaxial layer 2 along the buried layer with low resistivity, without overflowing into the second epitaxial layer 5, form parallel branches.

Referring to accompanying drawings 6 and 8, step S4 is performed, specifically: forming a first trench 6 penetrating through the second epitaxial layer 5 and extending to the first buried layer 3, and forming a trench 6 located in the first trench. The second groove 9 on the upper side of the groove 6 and communicating with the first groove 6 . In some embodiments of the present invention, a mask material is prepared on the upper surface of the second epitaxial layer 5, and the mask material is specifically a first photoresist, on the first photoresist layer by etching Etching forms a first trench 6 extending through the second epitaxial layer 5 to the first buried layer 3, and then removing the first photoresist. Wherein, the etching method includes dry etching and wet etching, preferably, the etching method used is dry etching, and dry etching includes light volatilization, vapor phase etching, plasma etching, etc., and dry etching Etching is easy to realize automation, no pollution is introduced in the processing process, and the cleanliness is high. In some embodiments of the present invention, the bottom surface of the first trench 6 is connected to the first buried layer 3 , for example, the bottom surface of the first trench 6 may extend to the first buried layer 3 Among them, the bottom surface of the first trench 6 may also be connected to the upper surface of the first buried layer 3 , so as to ensure that the bottom surface of the first trench 6 is in contact with the first buried layer 3 . Further, a second groove 9 coaxial with the first groove 6 is formed on the upper side of the first groove 6, and the inner diameter of the second groove 9 is larger than that of the first groove 6. the inside diameter of. The second trench 9 is located in the second epitaxial layer 5 , and one side of the second trench 9 is connected to the first injection region 7 . It should be noted that, the first groove 6 and the second groove 9 communicate with each other, so as to fill the first groove 6 and the second groove 9 with material more quickly and effectively. Regarding the shapes of the first trench 6 and the second trench 9, those skilled in the art can select trenches of different shapes according to the electrical performance of the device, the first trench 6 and the second trench The shape of 9 can be a rectangular groove, a square groove, a U-shaped groove, or even a spherical bottom groove, etc.

Referring to FIG. 7, step S5 is performed, specifically, a first implantation region 7 of the first conductivity type and a second implantation region 8 of the second conductivity type are formed on the upper surface of the second epitaxial layer 5, and the The first injection region 7 is connected to the first injection region 7 , and the doping concentration of the first injection region 7 is higher than the doping concentration of the second epitaxial layer 5 . In some embodiments of the present invention, a mask material is prepared on the upper surface of the second epitaxial layer 5, and the mask material is specifically a second photoresist, and light passes through the second photoresist layer. The etching method respectively forms a first implantation region 7 of the first conductivity type and a second implantation region 8 of the second conductivity type in the second epitaxial layer 5, wherein the first implantation region 7 and the second The injection regions 8 are adjacent and partially connected. The first implantation region 7 of the first conductivity type and the second implantation region 8 of the second conductivity type are formed on the upper surface of the second photoresist layer by ion implantation and/or diffusion, and then the first implantation region 8 is removed. Two photoresist layers. Further, the first implantation region 7 of the first conductivity type is formed on the upper surface of the second photoresist layer by means of ion implantation and/or diffusion of boron element or indium element or aluminum element or any combination of the three; At the same time, the second implantation region 8 of the second conductivity type is formed on the upper surface of the second photoresist layer by ion implantation and/or diffusion of phosphorus element or arsenic element or any combination of the two, and finally removed the second photoresist layer.

Further, the second buried layer 4 is disposed opposite to the second implantation region 8 . Preferably, the second buried layer 4 is disposed directly below the first implanted region 7, and the second implanted region 8 is disposed in the middle of the first implanted region 7, so as to form current from Conductive paths of the second injection region 8 , the first injection region 7 , the second epitaxial layer 5 and the second buried layer 4 . The doping concentration of the first injection region 7 is different from that of the second epitaxial layer 5 . Preferably, the doping concentration of the first implanted region 7 is higher than that of the second epitaxial layer 5, and when the current passes, the first implanted region 7 with high doping concentration precedes the second epitaxial layer 5. The epitaxial layer 5 is turned on so that the current passes through the second injection region 8 and the first injection region 7 to form a PN junction.

Further, the doping concentration of the first implanted region 7 is different from that of the first buried layer 3 . Preferably, the doping concentration of the first injection region 7 is higher than that of the first buried layer 3, so as to adjust the breakdown voltage of the power device protection chip.

Further, the doping concentration of the second implantation region 8 is different from that of the second buried layer 4 . Preferably, the doping concentration of the second buried layer 4 is higher than the doping concentration of the second injection region 8, so as to adjust the breakdown voltage of the power device protection chip.

Please refer to accompanying drawing 9, perform step S6, specifically: form the polysilicon layer 10 connected with the first buried layer 3 in the first trench 6 and the second trench 9, and place the polysilicon layer 10 is connected with the first injection region 7 . Since the first trench 6 communicates with the second trench 9, the polysilicon layer is formed in the first trench 6 and the second trench 9 by means of epitaxy, diffusion and/or implantation 10. Preferably, the polysilicon in the polysilicon layer 10 is specifically doped polysilicon. Doping polysilicon reduces the turn-on voltage under high current, and the effect of increasing the breakdown voltage can also be achieved by adjusting the doping concentration of polysilicon. Polysilicon is filled in the first trench 6 and the second trench 9 , so that the polysilicon layer 10 forms conductive channels electrically connected to the first buried layer 3 and the first implanted region 7 respectively. Further, the polysilicon layer 10 is formed by doping the intrinsic polysilicon with phosphorus ions or boron ions. Those skilled in the art can select different types of doped polysilicon according to the structure of the device. The polysilicon in the polysilicon layer 10 can be P-type polysilicon can also be N-type polysilicon. Specifically, the method of epitaxy, diffusion and/or implantation includes a deposition process. In some embodiments of the present invention, the first epitaxial layer 2 can be formed on the upper surface of the substrate 1 using a deposition process, for example, the deposition process can be selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, One of a kind in sputtering. Preferably, the polysilicon layer 10 is formed on the substrate 1 by Low Pressure Chemical Vapor Deposition (LPCVD for short), and the formed polysilicon layer 10 has high purity and good uniformity.

Referring to FIG. 9 , step S7 is executed, specifically: forming a dielectric layer 11 on the upper surface of the second epitaxial layer 5 . A dielectric layer 11 is formed on the upper surface of the second epitaxial layer 5 . The material of the dielectric layer 11 is silicon oxide, silicon nitride or silicon oxynitride, specifically, the dielectric layer 11 can be formed by sputtering, thermal oxidation or chemical vapor deposition. Preferably, the dielectric layer 11 is a silicon oxide layer formed by thermal oxidation, and in the subsequent doping step, the silicon oxide layer serves as a protective layer and will serve as an interlayer insulating layer of the final device. In addition, the dielectric layer 11 is provided with a certain thickness, so that the dielectric layer 11 plays the role of isolating current and insulating.

Further, one end of the polysilicon layer 10 penetrates the second epitaxial layer 5 and extends to the first buried layer 3 , and the other end is respectively connected to the first implantation region 7 and the dielectric layer 11 . It should be noted that the polysilicon layer 10 is first formed in the first trench 6, and then formed in the second trench 9, and the upper surface of the polysilicon layer 10 is higher than the second epitaxial The upper surface of the layer 5, so that the polysilicon layer 10 is not only connected to the first implantation region 7, but also connected to the dielectric layer 11.

Please refer to FIG. 10 , step S8 is performed, specifically: forming a first electrode 12, the first electrode 12 includes a first portion 121 penetrating through the dielectric layer 11 and extending to the second injection region 8 and formed in the The second part 122 on the surface of the dielectric layer 11; the second electrode 13 connected to the substrate 1 is formed on the lower surface of the substrate 1 . Firstly, a first contact hole (not shown) penetrating through the dielectric layer 11 and extending to the second implantation region 8 is formed by etching. Preferably, the first contact hole is formed by dry etching, and dry etching includes light volatilization, vapor phase etching, plasma etching, etc., and dry etching is easy to realize automation, no pollution is introduced in the process, and the cleanliness is high . Filling the first contact hole with a metal material to form a first portion 121 , and covering the upper surface of the dielectric layer 11 with a metal material to form the second portion 122 . The first portion 121 and the second portion 122 form a first metal layer connected to each other, that is, the first electrode 12 . The first electrode 12 is electrically connected to the second injection region 8 through the first portion 121 , so that a circuit flows to the path formed by the second injection region 8 and the first injection region 7 to form a PN junction. In addition, the lower surface of the substrate 1 is metallized to form a second metal layer, thereby forming a second electrode 13 electrically connected to the substrate 1 . The current flows through the substrate 1 along the second electrode 13 to an external circuit.

Further, the first buried layer 3 includes a first sub-buried layer and a second sub-buried layer respectively arranged on both sides of the second buried layer 4, and the first implanted region 7 includes sub-buried layers respectively arranged on the second buried layer 4. The first sub-implantation region and the second sub-implantation region on both sides of the second implantation region 8, the polysilicon layer 10 includes a first polysilicon layer 10 connected to the first sub-buried layer and the first sub-implantation region , and the second polysilicon layer 10 connected to the second sub-buried layer and the second sub-implantation region, so that the entire power device protection chip forms a symmetrical device structure, and when the current passes through the first In addition to the conductive paths formed by the electrode 12, the second injection region 8, the second epitaxial layer 5, the second buried layer 4, the first epitaxial layer 2, the substrate 1, and the second electrode 13, symmetrical branch.

It can be understood that, the first trench 6 is a deep trench, and the first buried layer 3 and the first The polysilicon layer 10 electrically connected to the injection region 7 forms a conductive channel for the polysilicon layer 10 for conducting electricity, and electrically connects the first injection region 7 to the first buried layer 3 to form a parallel Conductive pathway. In addition, the first buried layer 3 and the polysilicon layer 10 are symmetrically distributed to form a 3-way bidirectional parallel equivalent circuit. Due to the unidirectional conductivity of the diode and the small junction capacitance, it effectively reduces the The capacitor is connected to reduce the parasitic capacitance of the device in the high-frequency circuit.

Referring to the accompanying drawings, a power device protection chip will be described in detail below.

As shown in Figure 2, the implementation of the present invention provides a power device protection chip, the power device protection chip shown includes:

a substrate 1 of the first conductivity type;

The first epitaxial layer 2 of the second conductivity type is grown on the upper surface of the substrate 1;

The first buried layer 3 of the first conductivity type and the second buried layer 4 of the second conductivity type are formed in the first epitaxial layer 2, and at least part of the first buried layer 3 and the second buried layer 4 The surface is exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2;

The second epitaxial layer 5 of the first conductivity type is formed on the upper surface of the first epitaxial layer 2, and the doping concentration of the first buried layer 3 is higher than the doping concentration of the second epitaxial layer 5;

The first injection region 7 of the first conductivity type and the second injection region 8 of the second conductivity type are formed on the upper surface of the second epitaxial layer 5, and the first injection region 7 and the second injection region 8 connected, the doping concentration of the first injection region 7 is higher than the doping concentration of the second epitaxial layer 5;

a polysilicon layer 10 penetrating through the second epitaxial layer 5 and connected to the first implantation region 7 and the first buried layer 3 respectively;

a dielectric layer 11 formed on the upper surface of the second epitaxial layer 5;

The first electrode 12 includes a first portion 121 penetrating through the dielectric layer 11 and extending to the second injection region 8 and a second portion 122 formed on the surface of the dielectric layer 11;

The second electrode 13 is formed on the lower surface of the substrate 1 and connected to the substrate 1 .

Specifically, the first conductivity type is one of P-type doping and N-type doping, and the second conductivity type is the other of P-type doping and N-type doping.

For the convenience of description, it is hereby explained that the first conductivity type can be N-type doped, so that the second conductivity type can be P-type doped; the first conductivity type can also be P-type doped, so that The second conductivity type is N-type doping. It can be understood that when the first conductivity type is P-type doped and the second conductivity type is N-type doped, the substrate 1, the first buried layer 3, the second epitaxial Both the layer 5 and the first implantation region 7 are P-type doped, and the first epitaxial layer 2 , the second buried layer 4 and the second implantation region 8 are all N-type epitaxial layers. When the first conductivity type is N-type doped and the second conductivity type is P-type doped, the substrate 1, the first buried layer 3, the second epitaxial layer 5 and the The first implanted region 7 is all N-type doped, and the first epitaxial layer 2 , the second buried layer 4 and the second implanted region 8 are all P-type epitaxial layers. In the following embodiments, the first conductivity type is P-type doping and the second conductivity type is N-type doping as an example for description, but this is not limited thereto.

Specifically, both the P-type substrate and the P-type epitaxy belong to the P-type semiconductor, and the N-type substrate and the N-type epitaxy both belong to the N-type semiconductor. The P-type semiconductor is a silicon wafer doped with a trivalent element, such as boron element, indium element, aluminum element or any combination of the three. The N-type semiconductor is a silicon wafer doped with pentavalent elements, such as phosphorus or arsenic or any combination thereof.

In some embodiments of the present invention, as shown in FIG. 2 , the power device protection chip includes a substrate 1 of the first conductivity type and a first epitaxial layer 2 of the second conductivity type, and the first epitaxial layer 2 is grown on the upper surface of the substrate 1. Specifically, the substrate 1 is a carrier in an integrated circuit, the substrate 1 plays a supporting role, and the substrate 1 also participates in the work of the integrated circuit. The substrate 1 can be a silicon substrate, a sapphire substrate, a silicon carbide substrate, or even a silicon carbide substrate. Preferably, the substrate 1 is a silicon substrate, because The silicon substrate material has the characteristics of low cost, large size, and conductivity, which avoids edge effects and can greatly improve yield. The first epitaxial layer 2 of the second conductivity type grows on the upper surface of the substrate 1 of the first conductivity type, and a reaction occurs at the same time. When the current passes through the first epitaxial layer 2 and the substrate 1 in sequence, A PN junction is formed.

In some embodiments of the present invention, as shown in FIG. 2 , the power device protection chip further includes a first buried layer 3 of the first conductivity type and a second buried layer 4 of the second conductivity type, and the first buried layer Both the layer 3 and the second buried layer 4 are formed in the first epitaxial layer 2, and at least part of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the first epitaxial layer 2 On the surface, the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2 . Further, the first buried layer 3 and the second buried layer 4 are adjacent, and the first buried layer 3 and the second buried layer 4 may be spaced apart from each other, or may be connected to each other. In addition, both the first buried layer 3 and the second buried layer 4 are heavily doped, thereby reducing the resistivity of the first buried layer 3 and the second buried layer 4 . Preferably, the doping concentration of the second buried layer 4 is higher than the doping concentration of the first epitaxial layer 2, and the current will flow along the second buried layer 4 with low resistivity to the first epitaxial layer 2 lower side, thereby changing the current path, which is equivalent to reducing the series resistance.

In some embodiments of the present invention, as shown in FIG. 2 , the power device protection chip further includes a second epitaxial layer 5 of the first conductivity type, and the second epitaxial layer 5 is formed on the first epitaxial layer 2 upper surface. The thicknesses of the first epitaxial layer 2 and the second epitaxial layer 5 depend on the physical size of the semiconductor device to be realized and the silicon loss during the manufacturing process of the device. The second epitaxial layer 5 is grown on the upper surface of the first epitaxial layer 2 to reduce the leakage current of the PN junction in the semiconductor device.

In some embodiments of the present invention, as shown in FIG. 2 , the power device protection chip further includes a first implantation region 7 of the first conductivity type and a second implantation region 8 of the second conductivity type. The first implantation Region 7 and the second implanted region 8 are formed on the upper surface of the second epitaxial layer 5, and the first implanted region 7 is connected to the second implanted region 8, and the doped region of the first implanted region 7 The dopant concentration is higher than that of the second epitaxial layer 5 . In some embodiments of the present invention, both the first implantation region 7 and the second implantation region 8 are heavily doped, since the conductivity types of the first implantation region 7 and the second implantation region 8 are different , so the first implantation region 7 and the second implantation region 8 react to form a PN junction with a high doping concentration. It should be noted that the first injection region 7 and the second injection region 8 are adjacent to and partially connected, so that the current is formed along the PN junction formed by the first injection region 7 and the second injection region 8 Parallel branches. Further, the doping concentration of the first implanted region 7 is higher than that of the first buried layer 3 . Further, the doping concentration of the second buried layer 4 is higher than the doping concentration of the second implanted region 8 . Further, the second buried layer 4 is disposed opposite to the second implantation region 8 .

In some embodiments of the present invention, as shown in FIG. 2 , the power device protection chip further includes a polysilicon layer 10 , the polysilicon layer 10 penetrates the second epitaxial layer 5 and connects with the first injection region 7 respectively. connected to the first buried layer 3. The power device protection chip and even the semiconductor device are mostly made of single crystal silicon, and the polysilicon layer 10 is electrically connected to the first injection region 7 and the first buried layer 3 respectively, and the current flows through the first injection The region 7 then directly flows into the first buried layer 3, so that the discharge efficiency is higher. Specifically, the polysilicon layer 10 has high compatibility in single crystal silicon.

In some embodiments of the present invention, as shown in FIG. 2 , the power device protection chip further includes a dielectric layer 11 formed on the upper surface of the second epitaxial layer 5 . The dielectric layer 11 is used to isolate the second epitaxial layer 5 .

Further, one end of the polysilicon layer 10 penetrates the second epitaxial layer 5 and extends to the first buried layer 3 , and the other end is respectively connected to the first implantation region 7 and the dielectric layer 11 . One end of the polysilicon layer 10 penetrates the second epitaxial layer 5 and extends to the first buried layer 3, or one end of the polysilicon layer 10 penetrates the second epitaxial layer 5 and extends to the first buried layer 3. In the buried layer 3, one end of the polysilicon layer 10 may also penetrate through the second epitaxial layer 5 and extend to the upper surface of the first buried layer 3, so as to ensure that one end of the polysilicon layer and the first buried layer 3 contacts. More specifically, the other end of the polysilicon layer 10 extends from the upper surface of the second epitaxial layer 5 into the dielectric layer 11 to form a protrusion higher than the surface of the second epitaxial layer 5 . In one embodiment of the invention, the protrusion is square or rectangular. The protrusion is in contact with the dielectric layer 11, and one side of the protrusion of the polysilicon layer 10 is connected to the first injection region 7. Since the dielectric layer 11 is insulated, the other side of the polysilicon layer 10 is insulated. One end is electrically connected to the first injection region 7 .

In some embodiments of the present invention, as shown in FIG. 2 , the power device protection chip further includes a first electrode 12, and the first electrode 12 includes a The first part 121 of 8 and the second part 122 formed on the surface of the dielectric layer 11; the power device protection chip also includes a second electrode 13, which is formed on the lower surface of the substrate 1 and connected to the substrate 1. In some embodiments of the present invention, the first portion 121 penetrates the dielectric layer 11 and extends to the second injection region 8 , it may be that the first portion 121 penetrates the dielectric layer 11 and extends to the second injection region 8 . In the second implantation region 8 , the first portion 121 may also penetrate through the dielectric layer 11 and extend to the upper surface of the second implantation region 8 , ensuring that the first portion 121 is in contact with the second implantation region 8 . The first electrode 12 is specifically a first metal layer, the second electrode 13 is specifically a second metal layer, the first part 121 and the second part 122 are filled with a metal material, and the first part 121 and the second part 122 are filled with a metal material. The second portion 122 communicates and jointly forms the first metal layer. The first metal layer and the second metal layer have a certain thickness. The second metal layer is electrically connected to the substrate 1 .

Further, the first buried layer 3 includes a first sub-buried layer and a second sub-buried layer respectively arranged on both sides of the second buried layer 4, and the first implanted region 7 includes sub-buried layers respectively arranged on the second buried layer 4. The first sub-implantation region and the second sub-implantation region on both sides of the second implantation region 8, the polysilicon layer 10 includes a first polysilicon layer 10 connected to the first sub-buried layer and the first sub-implantation region , and the second polysilicon layer 10 connected to the second sub-buried layer and the second sub-implantation region, the overall structure of the power device protection chip is symmetrical and is a first primitive cell.

Please refer to the equivalent circuit diagram of the power device protection chip structure shown in Figure 11. When electricity is applied to the first electrode 12 and the second electrode 13 , the current flows from the first electrode 12 to the second electrode 13 . It should be noted that the forward direction and reverse direction of the PN junction formed below are judged by setting the first conductivity type as P-type, and setting the second conductivity type as N-type as an embodiment of the present invention, but not Not limited to this. The current passes through the first electrode 12, the second injection region 8, the second epitaxial layer 5, the second buried layer 4, the first epitaxial layer 2, the substrate 1 and the The second electrode 13 forms a main circuit. The second injection region 8 and the second epitaxial layer 5 form a reverse PN junction, thus forming a reverse first diode a1. The second epitaxial layer 5 and the second buried layer 4 form a forward PN junction, thus forming a forward second diode b1. The first epitaxial layer 2 and the substrate 1 form a reverse PN junction, thus forming a reverse third diode c1. An equivalent circuit consisting of three diodes is formed in the main circuit. When the current passes through the first electrode 12 and the second injection region 8 in sequence, due to the effect of the first injection region 7 and the polysilicon layer 10, the current is shunted after passing through the second injection region 8 in sequence into the polysilicon layer 10, and then sequentially pass through the first implantation region 7, the polysilicon layer 10, the first buried layer 3, the first epitaxial layer 2, the substrate 1 and the first The two electrodes 13 form a parallel first branch circuit. The second injection region 8 and the first injection region 7 form a reverse PN junction, thus forming a reverse fourth diode a2. The first buried layer 3 and the first epitaxial layer 2 form a forward PN junction, thus forming a forward fifth diode b2. The first epitaxial layer 2 and the substrate 1 form a reverse PN junction, thus forming a reverse sixth diode c2. The first subcircuit forms an equivalent circuit consisting of three diodes. In addition, since the first buried layer 3 includes the first sub-buried layer and the second sub-buried layer, the first implant region 7 includes the first sub-implant region and the second sub-implant region, the polysilicon The layer 10 includes the first polysilicon layer 10 and the second polysilicon layer 10, so the structure of the power device protection chip not only has a main circuit, but also has symmetrically distributed first sub-circuits and second sub-circuits. Divide the circuit. In summary, the power device protection chip to be protected by the present invention forms an equivalent circuit in which three groups of diodes are connected in parallel. Due to the unidirectional conductivity of the diodes and the small node capacitance, the access capacitance is effectively reduced, thereby enabling Reduce the parasitic capacitance of the device in high frequency circuits.

The technical solution of the present invention has been described in detail above in conjunction with the accompanying drawings. Through the improvement of the technical solution of the present invention, three groups of power device protection chips are integrated together, and the device area is reduced by introducing the buried layer process, which reduces the difficulty of the process and reduces the Device manufacturing costs. Three groups of diodes are connected in parallel to reduce parasitic capacitance, so that the protection characteristics and reliability of the improved power device protection chip are improved.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. a kind of power device protects chip characterized by comprising

The substrate of first conduction type；

First epitaxial layer of the second conduction type, is grown on the upper surface of substrate；

First buried layer of the first conduction type and the second buried layer of the second conduction type, are formed in first epitaxial layer, and At least partly surface exposure of first buried layer and the second buried layer in first epitaxial layer upper surface, second buried layer Doping concentration is higher than the doping concentration of first epitaxial layer；

Second epitaxial layer of the first conduction type, be formed in first epitaxial layer upper surface, and first buried layer is mixed Miscellaneous concentration is higher than the doping concentration of second epitaxial layer；

First injection region of the first conduction type and the second injection region of the second conduction type, are formed on second epitaxial layer Surface, and first injection region is connected with second injection region, the doping concentration of first injection region is higher than described The doping concentration of second epitaxial layer；

Polysilicon layer is connect through second epitaxial layer and with first injection region and first buried layer respectively；

Dielectric layer is formed in the upper surface of second epitaxial layer；

First electrode is given an account of including running through the dielectric layer and extending to the first part of second injection region and be formed in The second part of matter layer surface；

Second electrode is formed in the lower surface of the substrate and connect with the substrate.

2. power device according to claim 1 protects chip, which is characterized in that the doping concentration of first injection region Higher than the doping concentration of first buried layer.

3. power device according to claim 1 protects chip, which is characterized in that the doping concentration of second buried layer is high Doping concentration in second injection region.

4. power device according to claim 1 protects chip, which is characterized in that second buried layer and second note Enter area to be oppositely arranged.

5. power device according to claim 1 protects chip, which is characterized in that first buried layer includes being respectively set The first sub- buried layer and the second sub- buried layer in second buried layer two sides, first injection region include being respectively arranged at described the The the first sub- injection region and the second sub- injection region of two injection regions two sides, the polysilicon layer include and the described first sub- buried layer and institute The first polysilicon layer of the first sub- injection region connection is stated, and connect with the described second sub- buried layer and the second sub- injection region Second polysilicon layer.

6. a kind of production method of power device protection chip comprising:

In the first epitaxial layer of two conduction type of upper surface of substrate growth regulation of the first conduction type；

The first buried layer of the first conduction type and the second buried layer of the second conduction type, and institute are formed in first epitaxial layer At least partly surface exposure of the first buried layer and the second buried layer is stated in first epitaxial layer upper surface, second buried layer is mixed Miscellaneous concentration is higher than the doping concentration of first epitaxial layer；

The second epitaxial layer of the first conduction type, and the doping of first buried layer are formed in first epitaxial layer upper surface Concentration is higher than the doping concentration of second epitaxial layer；

The first groove of first buried layer is formed through second epitaxial layer and extended to, and is formed and is located at described first Groove upside and the second groove with the first groove connection；

The first injection region of the first conduction type and the second note of the second conduction type are formed in second epitaxial layer upper surface Enter area, and first injection region is connected into first injection region, the doping concentration of first injection region is higher than described the The doping concentration of two epitaxial layers；

Form the polysilicon layer that first buried layer connects in the first groove and the second groove, and by the polycrystalline Silicon layer is connected with first injection region；

Dielectric layer is formed in the upper surface of second epitaxial layer；

First electrode is formed, the first electrode includes running through the dielectric layer and extending to first of second injection region Divide and be formed in the second part of the dielectric layer surface；

The second electrode connecting with the substrate is formed in the lower surface of the substrate.

7. a kind of production method of power device protection chip according to claim 6, which is characterized in that first note The doping concentration for entering area is higher than the doping concentration of first buried layer.

8. a kind of production method of power device protection chip according to claim 6, which is characterized in that described second buries The doping concentration of layer is higher than the doping concentration of second injection region.

9. a kind of production method of power device protection chip according to claim 6, which is characterized in that by described second Buried layer is oppositely arranged with second injection region.

10. a kind of production method of power device protection chip according to claim 6, which is characterized in that described first Buried layer includes the first sub- buried layer and the second sub- buried layer for being respectively arranged at second buried layer two sides, and first injection region includes It is respectively arranged at the first sub- injection region and the second sub- injection region of second injection region two sides, the polysilicon layer includes and institute State the first polysilicon layer that the first sub- buried layer is connected with the described first sub- injection region, and with the described second sub- buried layer and described Second polysilicon layer of two sub- injection region connections.