CN119069529A - A SGT device with ESD and preparation method thereof - Google Patents
A SGT device with ESD and preparation method thereof Download PDFInfo
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Abstract
The invention discloses an SGT device with ESD and a preparation method, wherein the SGT device comprises an epitaxial layer, a dielectric layer and a metal layer which are sequentially stacked from bottom to top, and the metal layer comprises a grid metal layer and a source metal layer. An ESD groove and a source groove are sequentially formed in the epitaxial layer, a body region and a source region are arranged on two sides of the two source grooves, and the body regions on two sides of the two source grooves are respectively connected with the source metal layer through source contact holes. The ESD groove is internally provided with a first polysilicon layer, a second polysilicon layer and a third polysilicon layer which are sequentially stacked from bottom to top, the first polysilicon layer is connected with the source metal layer through an ESD source contact hole, and the third polysilicon layer is connected with the gate metal layer through an ESD gate contact hole. The ESD structure is sunk in the ESD groove, so that the overall size of the SGT device can be reduced, the reliability of the SGT device can be improved, and meanwhile, the packaging is convenient.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an SGT device with ESD and a preparation method thereof.
Background
As SGT device sizes continue to shrink, ESD has become a major failure mechanism for reliability, and the resulting damage has become a current deadly threat, as well as ESD design and failure analysis have become one of the most important issues in integrated circuit reliability research.
In the prior art, an ESD design is that a layer of ESD polysilicon is added between a gate and a source to form a zener diode group connected in series, so as to realize ESD protection between the gate and the source. The step difference not only increases the overall size of the SGT device, but also has the problems of photoresist residue, over-thin metal lead deposition and the like in process implementation, and can influence the reliability of products. In addition, the problems of wire bonding angle and the like are important to consider in the aspect of package design, and the compatible proportion is not high.
Accordingly, there is a need for further improvements in existing SGT devices.
Disclosure of Invention
The invention aims to provide an SGT device with ESD and a preparation method thereof, which not only can reduce the overall size of the SGT device, but also can improve the reliability of the SGT device and is convenient for packaging.
The invention adopts the following technical scheme:
An SGT device with ESD comprises an epitaxial layer, a dielectric layer and a metal layer which are sequentially stacked from bottom to top, wherein the metal layer comprises a grid metal layer and a source metal layer which are arranged at intervals;
The epitaxial layer is sequentially provided with an ESD groove and a source groove, two sides of each source groove are respectively provided with a body area and a source area, the body areas are positioned in the epitaxial layer, the source areas are positioned in the body areas, and the body areas at two sides of each source groove are respectively connected with the source metal layer through source contact holes;
The ESD groove is internally provided with a first polysilicon layer, a second polysilicon layer and a third polysilicon layer which are sequentially stacked from bottom to top, the first polysilicon layer is connected with the source metal layer through an ESD source electrode contact hole, and the third polysilicon layer is connected with the gate metal layer through an ESD gate electrode contact hole.
Preferably, the first polysilicon layer, the second polysilicon layer and the third polysilicon layer form an NPN structure, or
The first polysilicon layer, the second polysilicon layer and the third polysilicon layer form a PNP structure.
Preferably, a height difference between the upper surface of the first polysilicon layer, the upper surface of the second polysilicon layer, and the upper surface of the third polysilicon layer and the upper surface of the epitaxial layer is less than 0.05 μm.
Preferably, the ESD trench is further provided with a field oxide layer and a silicon nitride layer which are sequentially stacked from bottom to top, and the silicon nitride layer is arranged below the first polysilicon layer;
The source electrode groove is internally provided with the field oxide layer, the silicon nitride layer, the source electrode polycrystalline silicon layer, the IPO oxide layer and the grid electrode polycrystalline silicon layer which are sequentially stacked from bottom to top, the grid electrode oxide layer is arranged around the grid electrode polycrystalline silicon layer, and/or,
The ESD trench has a width greater than a width of the source region trench and/or,
The field oxide layer has a thickness greater than 0.01 μm, the silicon nitride layer has a thickness greater than 0.01 μm, and/or,
The thickness of the first polysilicon layer, the thickness of the second polysilicon layer, and the thickness of the third polysilicon layer are all greater than 1.0 μm.
Preferably, a passivation layer is disposed between the gate metal layer and the source metal layer.
Preferably, the epitaxial layer is arranged on a substrate, and a back gold layer is arranged on one surface of the substrate away from the epitaxial layer.
A method of making an SGT device having ESD, comprising:
step S10, forming an ESD groove and a source electrode groove on the epitaxial layer through an etching process;
step S20, sequentially forming a field oxide layer, a silicon nitride layer, a first polysilicon layer, a second polysilicon layer and a third polysilicon layer in the ESD groove, and sequentially forming a field oxide layer, a silicon nitride layer and a source polysilicon layer in the source groove;
Step S30, etching away part of the field oxide layer, the silicon nitride layer and the source polycrystalline silicon layer which are positioned in the source groove through an etching process, and sequentially forming an IPO oxide layer, a gate oxide layer and a gate polycrystalline silicon layer;
step S40, forming a body region on the epitaxial layer by an injection mode;
Step S50, forming a source region on the body region in an injection mode;
Step S60, forming a dielectric layer on the upper surface of the epitaxial layer, and forming a source electrode contact hole connected with the body region, an ESD source electrode contact hole connected with the first polysilicon layer and an ESD gate electrode contact hole connected with the third polysilicon layer from the dielectric layer through an etching process;
And step S70, forming a gate metal layer connected with the ESD gate contact hole and a source metal layer connected with the source contact hole and the ESD source contact hole on one surface of the dielectric layer, which is opposite to the epitaxial layer.
Preferably, the step S10 includes:
Step S11, forming a barrier layer on the upper surface of the epitaxial layer;
Step S12, forming the ESD groove and the source electrode groove on the upper surface of the epitaxial layer through an etching process;
and S13, removing impurities in the ESD groove and the source electrode groove through a sacrificial oxidation process, and removing the barrier layer.
Preferably, the step S20 includes:
step S21, forming the field oxide layer and the silicon nitride layer in the ESD groove and the source groove simultaneously;
Step S22, forming the first polysilicon layer on the silicon nitride layer in the ESD groove and forming the source polysilicon layer on the silicon nitride layer in the source groove, and removing the first polysilicon layer and the source polysilicon layer on the upper surface of the epitaxial layer through a chemical mechanical polishing process so that the upper surface of the first polysilicon layer and the upper surface of the source polysilicon layer are flush with the upper surface of the epitaxial layer;
Step S23, forming a second polysilicon layer on the first polysilicon layer, and removing the second polysilicon layer on the upper surface of the epitaxial layer through a chemical mechanical polishing process so that the upper surface of the second polysilicon layer is flush with the upper surface of the epitaxial layer;
And step S24, forming a third polysilicon layer on the second polysilicon layer, and removing the third polysilicon layer positioned on the upper surface of the epitaxial layer through a chemical mechanical polishing process so that the upper surface of the third polysilicon layer is flush with the upper surface of the epitaxial layer.
Preferably, before the step S10, a step S00 is further included, wherein a substrate is provided, and the epitaxial layer is formed on the substrate;
Step S80 is further included after step S70, where a passivation layer is formed between the gate metal layer and the source metal layer, and a back gold layer is formed on a side of the substrate away from the epitaxial layer.
Compared with the prior art, the invention has the beneficial effects that at least:
According to the SGT device with the ESD and the preparation method, the first polycrystalline silicon layer, the second polycrystalline silicon layer and the third polycrystalline silicon layer which are sequentially stacked from bottom to top are arranged in the ESD groove, the first polycrystalline silicon layer is connected with the source metal layer through the ESD source contact hole, the third polycrystalline silicon layer is connected with the gate metal layer through the ESD gate contact hole, namely the ESD structure is sunk in the ESD groove, so that the overall size of the SGT device can be reduced, step difference formed between the upper surface of the ESD structure and the upper surface of the epitaxial layer is avoided or reduced, the problems of photoresist residue at the step, excessive thin deposition of a metal lead and the like are avoided, and the reliability of the SGT device is further improved. In addition, the packaging method has the advantages of reducing the wire bonding angle and the like during packaging, thereby being convenient for packaging. Compared with the prior art that a layer of ESD structure is added between the grid electrode and the source electrode, the ESD structure has the function of the grid electrode, reduces the production flow, and reduces the production difficulty and the production cost.
Drawings
FIGS. 1-9 are schematic cross-sectional views of steps of SGT devices according to embodiments of the present invention.
FIG. 10 is a flow chart of a method of fabricating an SGT device according to an embodiment of the present invention.
In the figure, 100 parts of SGT devices, 1 parts of epitaxial layers, 11 parts of ESD grooves, 111 parts of first polycrystalline silicon layers, 1111 parts of ESD source electrode contact holes, 112 parts of second polycrystalline silicon layers, 113 parts of third polycrystalline silicon layers, 1131 parts of ESD gate electrode contact holes, 114 parts of field oxide layers, 115 parts of silicon nitride layers, 12 parts of source electrode grooves, 121 parts of source electrode polycrystalline silicon layers, 122 parts of IPO oxide layers, 123 parts of gate electrode polycrystalline silicon layers, 124 parts of gate electrode oxide layers, 13 parts of body regions, 131 parts of source electrode contact holes, 14 parts of source regions, 2 parts of medium layers, 3 parts of metal layers, 31 parts of gate electrode metal layers, 32 parts of source electrode metal layers, 33 parts of passivation layers, 34 parts of alloy layers, 4 parts of substrates and 5 parts of back gold layers are arranged.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted.
The words expressing the positions and directions described in the present invention are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present invention.
Referring to FIGS. 1-9, the present invention provides an SGT device 100 with ESD comprising an epitaxial layer 1, a dielectric layer 2 and a metal layer 3 stacked in sequence from bottom to top.
Specifically, the dielectric layer 2 is disposed above the epitaxial layer 1, and the metal layer 3 is disposed above the dielectric layer 2. The epitaxial layer 1 may be disposed on the substrate 4, and the substrate 4 may be P-type or N-type, for example, the P-type substrate 4 may be formed by doping a material such as sapphire, silicon, gallium nitride or silicon carbide with a trivalent element, for example, boron or the like, or the N-type substrate 4 may be formed by doping a material such as phosphorus or arsenic with a pentavalent element, for example. The epitaxial layer 1 may be formed by growing a layer of material of the same type as the substrate 4 on the substrate 4, and when the substrate 4 is P-type, growing a layer of P-type lightly doped material on the substrate 4. When the substrate 4 is of N type, a layer of N-type lightly doped grown epitaxial layer 1 is grown on the substrate 4.
The metal layer 3 may include a gate metal layer 31 and a source metal layer 32 that are disposed at intervals, and the material of the gate metal layer 31 and the material of the source metal layer 32 may be the same material or different materials. In this embodiment, the material of the gate metal layer 31 and the material of the source metal layer 32 are the same, and the material of the gate metal layer 31 and the material of the source metal layer 32 are both conductive materials, for example, aluminum. The dielectric layer 2 is made of an insulating material, for example, silicon dioxide, and the dielectric layer 2 can isolate the epitaxial layer 1 from the metal layer 3.
Preferably, a passivation layer 33 may be further disposed between the gate metal layer 31 and the source metal layer 32, the passivation layer 33 is made of an insulating material, the passivation layer 33 may insulate and isolate the gate metal layer 31 from the source metal layer 32, the passivation layer 33 may further fill a gap between the gate metal layer 31 and the source metal layer 32, and prevent foreign matters from falling into the gap between the gate metal layer 31 and the source metal layer 32 to cause a short circuit, and prevent water vapor from entering the gap between the gate metal layer 31 and the source metal layer 32, thereby protecting the gate metal layer 31 and the source metal layer 32.
The ESD trench 11 and the source trench 12 may be sequentially disposed on the epitaxial layer 1, and the number of the ESD trench 11 and the number of the source trench 12 may be one or more, and in this embodiment, the number of the ESD trench 11 is one and the number of the source trench 12 is two. The body region 13 and the source region 14 are arranged on both sides of the two source trenches 12, i.e. the body region 13 is divided into three sections by the two source trenches 12, and the source region 14 is also divided into three sections by the two source trenches 12. The body region 13 is located in the epitaxial layer 1, the source region 14 is located in the body region 13, the body region 13 can be formed on the substrate 4 at two sides of the two source trenches 12 through injection, then the source region 14 is formed on the body region 13 at two sides of the two source trenches 12 through injection, and the upper surface of the source region 14 and the upper surface of the epitaxial layer 1 are preferably arranged in a flush manner. The body regions 13 on two sides of the two source trenches 12 are respectively connected with the source metal layer 32 through source contact holes 131, and ions of elements in the same group as the body regions 13 can be arranged in the source contact holes 131, so that the ion concentration can be increased, the impedance can be further reduced, and the conductivity can be improved. Source contact hole 131 may be formed from the upper surface of dielectric layer 2 by an etching process, and source contact hole 131 may penetrate dielectric layer 2 and source region 14 and reach body region 13. The source region 14 and the epitaxial layer 1 are the same group element, and the source region 14 and the body region 13 are different group elements. When epitaxial layer 1 is a group iii element, source region 14 is also a group iii element and body region 13 is a group v element. When epitaxial layer 1 is a group v element, source region 14 is also a group v element and body region 13 is a group iii element.
Preferably, the ESD trench 11 and the source trench 12 may be formed on the upper surface of the epitaxial layer 1 at the same time by an etching process, the ESD trench 11 and the source trench 12 extend downward from the upper surface of the epitaxial layer 1, the depth of the ESD trench 11 is the same as or substantially the same as the depth of the source trench 12, and the width of the ESD trench 11 is preferably greater than the width of the source region 14 trench.
The ESD trench 11 may have a first polysilicon layer 111, a second polysilicon layer 112 and a third polysilicon layer 113 stacked in this order from bottom to top, i.e., the second polysilicon layer 112 is disposed on the first polysilicon layer 111 and the third polysilicon layer 113 is disposed on the second polysilicon layer 112. The first polysilicon layer 111 is connected to the source metal layer 32 through the ESD source contact hole 1111, and the third polysilicon layer 113 is connected to the gate metal layer 31 through the ESD gate contact hole 1131. Preferably, the thickness of the first polysilicon layer 111, the thickness of the second polysilicon layer 112, and the thickness of the third polysilicon layer 113 are all greater than 1.0 μm. An ESD source contact hole 1111 and an ESD gate contact hole 1131 may be formed from the upper surface of the dielectric layer 2 by an etching process, the ESD source contact hole 1111 may penetrate the dielectric layer 2 and be connected to the first polysilicon layer 111, and the ESD gate contact hole 1131 may penetrate the dielectric layer 2 and be connected to the third polysilicon layer 113.
In the application, by arranging the first polysilicon layer 111, the second polysilicon layer 112 and the third polysilicon layer 113 in the ESD trench 11 in a stacked manner from bottom to top, the first polysilicon layer 111 is connected with the source metal layer 32 through the ESD source contact hole 1111, and the third polysilicon layer 113 is connected with the gate metal layer 31 through the ESD gate contact hole 1131, i.e. the ESD structure is sunk in the ESD trench 11, the overall size of the SGT device 100 can be reduced, the step difference formed between the upper surface of the ESD structure and the upper surface of the epitaxial layer 1 is avoided or reduced, the problems of photoresist residue at the step, excessive thin metal lead deposition and the like are avoided, and the reliability of the SGT device 100 is further improved. In addition, the packaging method has the advantages of reducing the wire bonding angle and the like during packaging, thereby being convenient for packaging. Compared with the prior art that a layer of ESD structure is added between the grid electrode and the source electrode, the ESD structure has the function of the grid electrode, reduces the production flow, and reduces the production difficulty and the production cost.
In one embodiment, the material of the first polysilicon layer 111 and the material of the second polysilicon layer 112 are different types, and the material of the first polysilicon layer 111 and the material of the third polysilicon layer 113 are the same type, so that ESD isolation can be achieved. Specifically, when the material of the first polysilicon layer 111 and the material of the third polysilicon layer 113 are N-type, the material of the second polysilicon layer 112 is P-type, and the first polysilicon layer 111, the second polysilicon layer 112 and the third polysilicon layer 113 may form an NPN structure. When the material of the first polysilicon layer 111 and the material of the third polysilicon layer 113 are P-type, the material of the second polysilicon layer 112 is N-type, and the first polysilicon layer 111, the second polysilicon layer 112 and the third polysilicon layer 113 may form a PNP structure.
Preferably, the difference in height between the upper surface of the first polysilicon layer 111, the upper surface of the second polysilicon layer 112 and the upper surface of the third polysilicon layer 113 and the upper surface of the epitaxial layer 1 is less than 0.05 μm, i.e. the upper surface of the first polysilicon layer 111, the upper surface of the second polysilicon layer 112 and the upper surface of the third polysilicon layer 113 are arranged flush with the upper surface of the epitaxial layer 1. That is, the upper surface of the ESD structure is disposed flush or substantially flush with the upper surface of epitaxial layer 1, which may not only further reduce the overall size of SGT device 100, but may also further improve the reliability of SGT device 100.
In one embodiment, the ESD trench 11 further has a field oxide layer 114 and a silicon nitride layer 115 stacked in sequence from bottom to top,
The silicon nitride layer 115 is disposed under the first polysilicon layer 111, that is, the ESD trench 11 has a field oxide layer 114, a silicon nitride layer 115, the first polysilicon layer 111, the second polysilicon layer 112, and the third polysilicon layer 113, which are sequentially stacked from bottom to top. The difference in height between the upper surface of the field oxide layer 114 and the upper surface of the silicon nitride layer 115 and the upper surface of the epitaxial layer 1 is less than 0.05 μm, i.e. the upper surface of the field oxide layer 114 and the upper surface of the silicon nitride layer 115 may be disposed flush with the upper surface of the epitaxial layer 1. That is, the height difference between the upper surfaces of the field oxide layer 114, the silicon nitride layer 115, the first polysilicon layer 111, the second polysilicon layer 112, and the third polysilicon layer 113 located in the ESD trench 11 and the upper surface of the epitaxial layer 1 is less than 0.05 μm, or, the upper surfaces of the field oxide layer 114, the silicon nitride layer 115, the first polysilicon layer 111, the second polysilicon layer 112, and the third polysilicon layer 113 located in the ESD trench 11 are disposed flush with the upper surface of the epitaxial layer 1.
The source trench 12 has therein a field oxide layer 114, a silicon nitride layer 115, a source polysilicon layer 121, an IPO oxide layer 122, and a gate polysilicon layer 123 stacked in this order from bottom to top, and a gate oxide layer 124 is provided around the gate polysilicon layer 123. The field oxide layer 114 and the silicon nitride layer 115 in the source trench 12 may be formed simultaneously with the field oxide layer 114 and the silicon nitride layer 115 in the ESD trench 11. The thickness of the field oxide layer 114 is preferably greater than 0.01 μm and the thickness of the silicon nitride layer 115 is preferably greater than 0.01 μm. The provision of both field oxide layer 114 and silicon nitride layer 115 in this embodiment may improve the voltage withstand performance of SGT device 100 as compared to the provision of only field oxide layer 114.
A back gold layer 5 may also be disposed on a side of the substrate 4 away from the epitaxial layer 1, where the back gold layer 5 forms the drain of the SGT device 100, and the back gold layer 5 is made of a high conductivity metal, such as gold, silver, aluminum, and the like. In some embodiments, the back gold layer 5 may be disposed at other locations.
Referring to FIGS. 1-10, the present invention also provides a method of making an SGT device 100 with ESD, comprising steps S10-S70.
Referring to fig. 1, step S00 is further included before step S10, step S00 of providing a substrate 4 and forming an epitaxial layer 1 on the substrate 4. The substrate 4 may be P-type or N-type, and when the substrate 4 is P-type, a P-type lightly doped layer is grown on the substrate 4 to form the epitaxial layer 1. When the substrate 4 is of N type, a layer of N-type lightly doped grown epitaxial layer 1 is grown on the substrate 4. Of course, it is also possible to provide the substrate 4 with the epitaxial layer 1 directly.
Step S10 referring to fig. 2, an ESD trench 11 and a source trench 12 are formed on the epitaxial layer 1 by an etching process.
Specifically, step S10 may include steps S11 to S13.
In step S11, a barrier layer (not shown) may be formed on the upper surface of the epitaxial layer 1 by a deposition method, where the barrier layer may include an oxide layer and a first silicon nitride layer, and may protect other areas of the epitaxial layer 1 from being etched by an etching process.
In step S12, ESD trench 11 and source trench 12 are formed on the upper surface of epitaxial layer 1 by an etching process, wherein each SGT device 100 includes one ESD trench 11 and two source trenches 12. ESD trench 11 and source trench 12 of one or more SGT devices 100 may be formed simultaneously on epitaxial layer 1.
And S13, removing impurities in the ESD groove 11 and the source groove 12 through a sacrificial oxidation process, and removing the barrier layer. The sacrificial oxidation process may be performed using prior art techniques and is not described in detail herein.
In step S20, referring to fig. 3, a field oxide layer 114, a silicon nitride layer 115, a first polysilicon layer 111, a second polysilicon layer 112 and a third polysilicon layer 113 are sequentially formed in the ESD trench 11, and a field oxide layer 114, a silicon nitride layer 115 and a source polysilicon layer 121 are sequentially formed in the source trench 12.
Specifically, step S20 may include steps S21 to S24.
In step S21, a field oxide layer 114 and a silicon nitride layer 115 are formed in sequence in the ESD trench 11 and in the source trench 12 at the same time. A field oxide layer 114 is now grown in ESD trench 11 and in source trench 12, and a silicon nitride layer 115 is grown on field oxide layer 114. The provision of both field oxide layer 114 and silicon nitride layer 115 in this embodiment may improve the voltage withstand performance of SGT device 100 as compared to the provision of only field oxide layer 114.
In step S22, a first polysilicon layer 111 is formed on the silicon nitride layer 115 in the ESD trench 11 and a source polysilicon layer 121 is formed on the silicon nitride layer 115 in the source trench 12 at the same time, the first polysilicon layer 111 and the source polysilicon layer 121 may be formed by a deposition process or a deposition process, and then the first polysilicon layer 111 and the source polysilicon layer 121 located on the upper surface of the epitaxial layer 1 are removed by a Chemical Mechanical Polishing (CMP) process so that the upper surface of the first polysilicon layer 111 and the upper surface of the source polysilicon layer 121 are flush with the upper surface of the epitaxial layer 1. At this time, the interface of the first polysilicon layer 111 has a U shape as a whole, and the source polysilicon layer 121 may fill the source trench 12. The material of the first polysilicon layer 111 and the material of the source polysilicon layer 121 are preferably the same type, and the material of the first polysilicon layer 111 and the material of the source polysilicon layer 121 are more preferably the same type.
In step S23, a second polysilicon layer 112 is formed on the first polysilicon layer 111, the second polysilicon layer 112 may be formed by a deposition process or a deposition process, and then the second polysilicon layer 112 on the upper surface of the epitaxial layer 1 is removed by a Chemical Mechanical Polishing (CMP) process, so that the upper surface of the second polysilicon layer 112 is flush with the upper surface of the epitaxial layer 1, and the second polysilicon layer 112 on the upper surface of the source polysilicon layer 121 may be removed by the Chemical Mechanical Polishing (CMP) process.
In step S24, a third polysilicon layer 113 is formed on the second polysilicon layer 112, the third polysilicon layer 113 may be formed by a deposition process or a deposition process, and then the third polysilicon layer 113 on the upper surface of the epitaxial layer 1 is removed by a Chemical Mechanical Polishing (CMP) process, so that the upper surface of the third polysilicon layer 113 is flush with the upper surface of the epitaxial layer 1, and simultaneously the third polysilicon layer 113 on the upper surface of the source polysilicon layer 121 may also be removed by a Chemical Mechanical Polishing (CMP) process.
The material of the first polysilicon layer 111 and the material of the second polysilicon layer 112 are different types, and the material of the first polysilicon layer 111 and the material of the third polysilicon layer 113 are the same type, so that ESD isolation can be achieved. Specifically, when the material of the first polysilicon layer 111 and the material of the third polysilicon layer 113 are N-type, the material of the second polysilicon layer 112 is P-type, and the first polysilicon layer 111, the second polysilicon layer 112 and the third polysilicon layer 113 may form an NPN structure. When the material of the first polysilicon layer 111 and the material of the third polysilicon layer 113 are P-type, the material of the second polysilicon layer 112 is N-type, and the first polysilicon layer 111, the second polysilicon layer 112 and the third polysilicon layer 113 may form a PNP structure.
Step S30, referring to fig. 4, the field oxide layer 114, the silicon nitride layer 115 and the source polysilicon layer 121 in the source trench 12 are etched away by an etching process, and an IPO oxide layer 122, a gate oxide layer 124 and a gate polysilicon layer 123 are sequentially formed.
Specifically, the field oxide layer 114, the silicon nitride layer 115 and the source polysilicon layer 121 are etched away by an etching process, an IPO oxide layer 122 is grown on the source polysilicon layer 121, a gate oxide layer 124 is grown on the sidewall of the source trench 12 above the IPO oxide layer 122, a gate polysilicon layer 123 is formed in the source trench 12 by a deposition process or a deposition process, and finally the gate polysilicon layer 123 on the upper surface of the epitaxial layer 1 is etched away by an etching process, so that the upper surface of the gate polysilicon layer 123 is flush with the upper surface of the epitaxial layer 1, and a shielded gate structure is formed, which can optimize the capacitance characteristics of the SGT device 100.
In step S40, referring to fig. 5, body region 13 is formed on epitaxial layer 1 by implantation.
Specifically, ions of a group iii element or ions of a group v element are implanted into the epitaxial layer 1 through the trenches of the source region 14, and then high-temperature annealing is performed to form body regions 13, wherein the body regions 13 are distributed on both sides of the two source trenches 12. The high-temperature annealing temperature is 900-1150 ℃, the high-temperature annealing time is 20-200min, and the high-temperature annealing can promote ion diffusion and make ion distribution uniform.
In step S50, referring to fig. 6, a source region 14 is formed on the body region 13 by implantation.
Specifically, ions of a group iii element or ions of a group v element are implanted into the body region 13 through the trenches of the source region 14, and then high-temperature annealing is performed to form the source region 14, wherein the source region 14 is located in the body region 13, the source regions 14 are distributed on two sides of the two source trenches 12, and the upper surface of the source region 14 is preferably flush with the upper surface of the epitaxial layer 1. The high-temperature annealing temperature is 900-1150 ℃, the high-temperature annealing time is 20-200min, and the high-temperature annealing can promote ion diffusion and make ion distribution uniform. The source region 14 and the epitaxial layer 1 are the same group element, and the source region 14 and the body region 13 are different group elements. When epitaxial layer 1 is a group iii element, source region 14 is also a group iii element and body region 13 is a group v element. When epitaxial layer 1 is a group v element, source region 14 is also a group v element and body region 13 is a group iii element.
In step S60, referring to fig. 7, a dielectric layer 2 is formed on the upper surface of the epitaxial layer 1, and a source contact hole 131 connecting the body region 13, an ESD source contact hole 1111 connecting the first polysilicon layer 111, and an ESD gate contact hole 1131 connecting the third polysilicon layer 113 are formed from the dielectric layer 2 by an etching process.
Specifically, the dielectric layer 2 is formed on the upper surface of the epitaxial layer 1 through a deposition process or a deposition process, and then the source contact hole 131 of the connection body region 13, the ESD source contact hole 1111 connected to the first polysilicon layer 111, and the ESD gate contact hole 1131 connected to the third polysilicon layer 113 are formed from the dielectric layer 2 through an etching process. The source contact hole 131 is connected to the body region 13 through the dielectric layer 2 and the source region 14, the ESD source contact hole 1111 is connected to the first polysilicon layer 111 through the dielectric layer 2, and the ESD gate contact hole 1131 is connected to the third polysilicon layer 113 through the dielectric layer 2. The dielectric layer 2 is made of an insulating material, for example, silicon dioxide, and the dielectric layer 2 can isolate the epitaxial layer 1 from the metal layer 3.
Preferably, ions of elements of the same family as the body region 13 may be injected into the source contact hole 131, the ESD source contact hole 1111, and the ESD gate contact hole 1131, so that the ion concentration may be increased, the resistance in the contact hole may be reduced, and the conductivity may be improved.
The alloy layer 34 may be further formed in the source contact hole 131, the ESD source contact hole 1111, and the ESD gate contact hole 1131 by a deposition process or a deposition process, and the alloy layer 34 may further improve the conductivity of the contact hole. The alloy layer 34 may be made of Ti, tiN, W, or the like.
In step S70, referring to fig. 8, a gate metal layer 31 connected to the ESD gate contact hole 1131 and a source metal layer 32 connected to the source contact hole 131 and the ESD source contact hole 1111 are formed on the surface of the dielectric layer 2 facing away from the epitaxial layer 1.
Specifically, the gate metal layer 31 connected to the ESD gate contact hole 1131 and the source metal layer 32 connected to the source contact hole 131 and the ESD source contact hole 1111 may be formed on a surface of the dielectric layer 2 facing away from the epitaxial layer 1 by a deposition process, or a sputtering process. A metal layer can be formed on the surface of the dielectric layer 2 opposite to the epitaxial layer 1 by a deposition process, a deposition process or a sputtering process, and then the gate metal layer 31 and the source metal layer 32 are respectively formed by an etching process. The gate metal layer 31 and the source metal layer 32 are disposed at intervals, and the material of the gate metal layer 31 and the material of the source metal layer 32 may be the same material or different materials. In this embodiment, the material of the gate metal layer 31 and the material of the source metal layer 32 are the same, and the material of the gate metal layer 31 and the material of the source metal layer 32 are both conductive materials, for example, aluminum.
Step S80 is further included after step S70, and step S80 is to form a passivation layer 33 between the gate metal layer 31 and the source metal layer 32, and form a back gold layer 5 on a side of the substrate 4 away from the epitaxial layer 1, with reference to fig. 9.
Specifically, the passivation layer 33 may be formed between the gate metal layer 31 and the source metal layer 32 through a passivation process, the passivation layer 33 is made of an insulating material, the passivation layer 33 may insulate and isolate the gate metal layer 31 from the source metal layer 32, the passivation layer 33 may also fill a gap between the gate metal layer 31 and the source metal layer 32, so as to avoid a short circuit caused by foreign matters falling into the gap between the gate metal layer 31 and the source metal layer 32, and may also prevent water vapor and the like from entering the gap between the gate metal layer 31 and the source metal layer 32, thereby protecting the gate metal layer 31 and the source metal layer 32.
A back gold layer 5 may be formed on a surface of the substrate 4 away from the epitaxial layer 1 by evaporation, where the back gold layer 5 forms the drain of the SGT device 100, and the back gold layer 5 is made of a high conductivity metal, for example, gold, silver, aluminum, or the like. In some embodiments, the back gold layer 5 may be disposed at other locations.
As a preferred mode, before the back gold layer 5 is formed on the surface of the substrate 4, which is not provided with the epitaxial layer 1, the surface of the substrate 4, which is far away from the epitaxial layer 1, is thinned, and the thinning can be realized through mechanical grinding, chemical Mechanical Polishing (CMP) and other processes, so that the thickness and the weight of the whole SGT device can be obviously reduced, the heat dissipation effect of the SGT device can be improved, the stability and the long-term reliability can be improved, the path for transmitting electric signals can be reduced, the resistance and the inductance can be reduced, the electric performance and the working efficiency of the SGT device can be improved, the surface of the substrate 4 can be smoother, and the performance of the SGT device can be further improved
While embodiments of the present invention have been shown and described, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that changes, modifications, substitutions and alterations may be made therein by those of ordinary skill in the art without departing from the spirit and scope of the invention, all such changes being within the scope of the appended claims.
Claims (10)
1. The SGT device with ESD is characterized by comprising an epitaxial layer, a dielectric layer and a metal layer, wherein the epitaxial layer, the dielectric layer and the metal layer are sequentially stacked from bottom to top, and the metal layer comprises a grid metal layer and a source metal layer which are arranged at intervals;
The epitaxial layer is sequentially provided with an ESD groove and a source groove, two sides of each source groove are respectively provided with a body area and a source area, the body areas are positioned in the epitaxial layer, the source areas are positioned in the body areas, and the body areas at two sides of each source groove are respectively connected with the source metal layer through source contact holes;
The ESD groove is internally provided with a first polysilicon layer, a second polysilicon layer and a third polysilicon layer which are sequentially stacked from bottom to top, the first polysilicon layer is connected with the source metal layer through an ESD source electrode contact hole, and the third polysilicon layer is connected with the gate metal layer through an ESD gate electrode contact hole.
2. The SGT device with ESD of claim 1, wherein the first polysilicon layer, the second polysilicon layer and the third polysilicon layer form an NPN structure, or
The first polysilicon layer, the second polysilicon layer and the third polysilicon layer form a PNP structure.
3. The SGT device with ESD of claim 1 wherein a difference in height between an upper surface of the first polysilicon layer, an upper surface of the second polysilicon layer, and an upper surface of the third polysilicon layer and an upper surface of the epitaxial layer is less than 0.05 μm.
4. The SGT device with ESD of claim 1 wherein said ESD trench further has a field oxide layer and a silicon nitride layer disposed in a bottom-up sequence, said silicon nitride layer disposed below said first polysilicon layer;
The source electrode groove is internally provided with the field oxide layer, the silicon nitride layer, the source electrode polycrystalline silicon layer, the IPO oxide layer and the grid electrode polycrystalline silicon layer which are sequentially stacked from bottom to top, the grid electrode oxide layer is arranged around the grid electrode polycrystalline silicon layer, and/or,
The ESD trench has a width greater than a width of the source region trench and/or,
The field oxide layer has a thickness greater than 0.01 μm, the silicon nitride layer has a thickness greater than 0.01 μm, and/or,
The thickness of the first polysilicon layer, the thickness of the second polysilicon layer, and the thickness of the third polysilicon layer are all greater than 1.0 μm.
5. The SGT device with ESD of claim 1 wherein a passivation layer is disposed between said gate metal layer and said source metal layer.
6. The SGT device with ESD of claim 1 wherein said epitaxial layer is provided on a substrate, and a back gold layer is provided on a side of said substrate remote from said epitaxial layer.
7. A method for manufacturing an SGT device with ESD is characterized in that,
Step S10, forming an ESD groove and a source electrode groove on the epitaxial layer through an etching process;
step S20, sequentially forming a field oxide layer, a silicon nitride layer, a first polysilicon layer, a second polysilicon layer and a third polysilicon layer in the ESD groove, and sequentially forming a field oxide layer, a silicon nitride layer and a source polysilicon layer in the source groove;
Step S30, etching away part of the field oxide layer, the silicon nitride layer and the source polycrystalline silicon layer which are positioned in the source groove through an etching process, and sequentially forming an IPO oxide layer, a gate oxide layer and a gate polycrystalline silicon layer;
step S40, forming a body region on the epitaxial layer by an injection mode;
Step S50, forming a source region on the body region in an injection mode;
Step S60, forming a dielectric layer on the upper surface of the epitaxial layer, and forming a source electrode contact hole connected with the body region, an ESD source electrode contact hole connected with the first polysilicon layer and an ESD gate electrode contact hole connected with the third polysilicon layer from the dielectric layer through an etching process;
And step S70, forming a gate metal layer connected with the ESD gate contact hole and a source metal layer connected with the source contact hole and the ESD source contact hole on one surface of the dielectric layer, which is opposite to the epitaxial layer.
8. The method of claim 7, wherein the step S10 includes:
Step S11, forming a barrier layer on the upper surface of the epitaxial layer;
step S12, forming the ESD groove and the source electrode groove on the upper surface of the epitaxial layer through an etching process;
and S13, removing impurities in the ESD groove and the source electrode groove through a sacrificial oxidation process, and removing the barrier layer.
9. The method of claim 7, wherein the step S20 includes:
step S21, forming the field oxide layer and the silicon nitride layer in the ESD groove and the source groove simultaneously;
Step S22, forming the first polysilicon layer on the silicon nitride layer in the ESD groove and forming the source polysilicon layer on the silicon nitride layer in the source groove, and removing the first polysilicon layer and the source polysilicon layer on the upper surface of the epitaxial layer through a chemical mechanical polishing process so that the upper surface of the first polysilicon layer and the upper surface of the source polysilicon layer are flush with the upper surface of the epitaxial layer;
Step S23, forming a second polysilicon layer on the first polysilicon layer, and removing the second polysilicon layer on the upper surface of the epitaxial layer through a chemical mechanical polishing process so that the upper surface of the second polysilicon layer is flush with the upper surface of the epitaxial layer;
And step S24, forming a third polysilicon layer on the second polysilicon layer, and removing the third polysilicon layer positioned on the upper surface of the epitaxial layer through a chemical mechanical polishing process so that the upper surface of the third polysilicon layer is flush with the upper surface of the epitaxial layer.
10. The method of claim 7, further comprising a step S00, prior to said step S10, of providing a substrate, forming said epitaxial layer on said substrate;
Step S80 is further included after step S70, where a passivation layer is formed between the gate metal layer and the source metal layer, and a back gold layer is formed on a side of the substrate away from the epitaxial layer.
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