CN113937098B - Electrostatic protection chip for fast charging management system and preparation method thereof - Google Patents

Abstract

The invention discloses an electrostatic protection chip for a rapid charging management system, which comprises a substrate, a first epitaxial layer formed on the substrate, a first injection region on the first epitaxial layer, a second injection region on the first injection region and a second epitaxial layer on the second injection region, a first groove extending from the second epitaxial layer to the first epitaxial layer, a second groove positioned between the first grooves, a silicon oxide layer filled in the first groove, a third epitaxial layer filled in the second groove, a third injection region formed in the third epitaxial layer, a fourth injection region in the second epitaxial layer, a first dielectric layer, a second dielectric layer, a first contact hole and a second contact hole positioned between the first dielectric layer and the second dielectric layer, a first metal layer on the first dielectric layer and in the first contact hole, and a second metal layer on the second dielectric layer and in the second contact hole. The invention also provides a preparation method of the electrostatic protection chip for the rapid charging management system, which improves the discharge density and reduces the manufacturing cost of the device.

Description

Electrostatic protection chip for fast charging management system and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor chip manufacturing technology, and in particular relates to an electrostatic protection chip used in a fast charging management system and a preparation method thereof.

Background technique

As semiconductor devices are increasingly miniaturized, high-density, and multi-functional, electronic devices are increasingly vulnerable to voltage surges, which can even cause fatal injuries. Voltage surges ranging from electrostatic discharge to lightning can induce transient current spikes, and transient voltage suppressors (TVS) are often used to protect sensitive circuits from surges. Based on different applications, the transient voltage suppressor can protect the circuit by changing the surge discharge path and its own clamping voltage.

The low-capacitance TVS structure is suitable for protection devices of high-frequency circuits, because it can reduce the interference of parasitic capacitance on the circuit and reduce the attenuation of high-frequency circuit signals. In the fast charging source management system, a large number of TVS are used as circuit protection devices, and the fast charging source management system is very sensitive to the interference of signal attenuation and parasitic capacitance. Low capacitance TVS chips are very important to improve the fast charging source management system. Usually, in order to improve the reverse characteristic of TVS, a guard ring structure and a metal field plate structure are adopted, but these two structures are easy to introduce large additional capacitance, and increase the area of the device, resulting in a decrease in the working performance of the device.

Contents of the invention

In view of this, the present invention provides an electrostatic protection chip for a fast charging management system and a preparation method thereof, which reduce the parasitic capacitance of the device, increase the discharge density and improve the performance of the device, to solve the above-mentioned existing technical problems, and specifically adopt the following technical solutions to achieve.

In a first aspect, the present invention provides an electrostatic protection chip for a fast charging management system, including:

a substrate of the first conductivity type;

a first epitaxial layer of a second conductivity type formed on the substrate;

A first injection region of the second conductivity type formed on the upper surface of the first epitaxial layer, a second injection region of the first conductivity type formed on the first injection region, and a second injection region formed on the second injection region a second epitaxial layer of the first conductivity type on the upper surface;

First trenches extending from the second epitaxial layer into the first epitaxial layer and arranged at intervals, and second trenches located between the first trenches, the first trenches are filled with oxide a silicon layer, the second trench is filled with a third epitaxial layer of the second conductivity type, and the junction depth of the second trench is smaller than the junction depth of the first trench;

a third implantation region of the first conductivity type formed in the third epitaxial layer, a fourth implantation region of the first conductivity type formed in the second epitaxial layer between the first trenches;

A first dielectric layer arranged at intervals on the surface of the second epitaxial layer, the silicon oxide layer, the third epitaxial layer, and part of the third implantation region, formed in part of the third implantation region, the The third epitaxial layer, the second epitaxial layer, and part of the second dielectric layer arranged at intervals on the upper surface of the fourth injection region;

forming a first contact hole located between the first dielectric layer and the second dielectric layer, and a second contact hole located between the second dielectric layer, the inside of the first contact hole and the first contact hole A first metal layer is formed on the upper surface of a dielectric layer, a second metal layer is formed on the upper surface of the second dielectric layer and in the second contact hole, and the first metal layer is arranged symmetrically with respect to the second metal layer.

In the second aspect, the present invention also provides a method for preparing an electrostatic protection chip for a fast charging management system, comprising the following steps:

providing a substrate of a first conductivity type on which a first epitaxial layer of a second conductivity type is formed;

A first injection region of the second conductivity type and a second injection region of the first conductivity type located on the upper surface of the first injection region are formed on the first epitaxial layer, and a second injection region is formed on the upper surface of the second injection region. a second epitaxial layer of a conductivity type;

Extending from the second epitaxial layer to the first epitaxial layer, forming first trenches arranged at intervals by photolithography, filling the first trenches with silicon oxide to form a silicon oxide layer;

performing etching on the upper surface of the second epitaxial layer located between the first trenches to form a a second trench within the layer, the junction depth of the second trench being less than the junction depth of the first trench;

filling the second trench with ions of the second conductivity type to form a third epitaxial layer;

Performing ion implantation of the first conductivity type in the third epitaxial layer and in the second epitaxial layer between the first trenches respectively to form a third implantation region and a fourth implantation region;

Perform dielectric growth on the upper surface of the second epitaxial layer, respectively remove the dielectric corresponding to the upper surface of the third implantation region and the fourth implantation region to form a first contact hole and a second contact hole, and retain the second epitaxial layer. layer, the silicon oxide layer, the third epitaxial layer, and part of the medium on the upper surface of the third implantation region form a first dielectric layer arranged at intervals, and part of the third implantation region, the third epitaxial layer , the second epitaxial layer and part of the dielectric on the upper surface of the fourth injection region form a second dielectric layer arranged at intervals;

Filling the first contact hole and the upper surface of the first dielectric layer with metal to form a first metal layer, and filling the upper surface of the second dielectric layer and the second contact hole with metal to form a second metal layer, The first metal layer is arranged symmetrically with respect to the second metal layer.

The invention provides an electrostatic protection chip for a fast charging management system and a preparation method thereof. Compared with the prior art, it has the following beneficial effects:

By forming a first epitaxial layer with a conductivity type different from that of the substrate on the substrate, a first implanted region and a second implanted region with a different conductivity type are sequentially prepared on the upper surface of the first epitaxial layer, and the first implanted region and the second implanted region Forming a PN junction can enhance the withstand voltage performance of the device. A second epitaxial layer of the same conductivity type as the second implanted region is formed on the upper surface of the second implanted region. The second epitaxial layer can protect the first implanted region and the second implanted region and reduce etching damage, and can also reduce leakage in the device. current. Extending from the second epitaxial layer to the first epitaxial layer to form a first trench and filling the first trench with a silicon oxide layer can be used as an isolation trench and form multiple current paths, and a second trench is formed between the two first trenches. Two trenches, the junction depth of the second trench is smaller than that of the first trench, the second trench is filled with a third epitaxial layer with a doping concentration greater than that of the first epitaxial layer, and the upper surfaces of the third epitaxial layer and the second epitaxial layer are respectively formed The third injection region and the fourth injection region, the conductivity type of the third injection region and the third epitaxial layer are different to form a PN junction, the upper surface of the third injection region forms a corresponding first metal layer, and the upper surface of the fourth injection region forms a corresponding The second metal layer, the first metal layer and the second metal layer are located on the upper surface of the substrate to simplify the fabrication process of the device. The device is integrated with a simple process, which can realize the parallel connection of multiple bidirectional protection circuits. The isolation trench can reduce the parasitic capacitance of the device and meet the protection requirements of high-frequency devices in the fast charging power management system. Fill the third epitaxial layer in the second trench and perform ion implantation to form a PN junction, which ensures the interface quality of the PN junction and reduces the leakage of the device. The discharge structure adopts the form of a trench, which improves the discharge density and reduces the manufacturing of the device. cost.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and thus It should be regarded as a limitation on the scope, and those skilled in the art can also obtain other related drawings based on these drawings without creative work.

FIG. 1 is a flow chart of a method for preparing an electrostatic protection chip for a fast charging management system provided by an embodiment of the present invention;

2 to 9 are diagrams of the preparation process of the electrostatic protection chip used in the fast charging management system provided by the embodiment of the present invention;

Fig. 10 is a schematic diagram of the circuit principle of the electrostatic protection chip used in the fast charging management system provided by the embodiment of the present invention;

FIG. 11 is an equivalent circuit diagram of an electrostatic protection chip used in a fast charging management system provided by an embodiment of the present invention.

The main component symbols are explained as follows:

10-substrate; 11-first epitaxial layer; 12-first implantation region; 13-second implantation region; 14-second epitaxial layer; 15-first trench; 16-second trench; 17-oxidation Silicon layer; 18-third epitaxial layer; 20-third implantation region; 21-fourth implantation region; 22-first dielectric layer; 23-second dielectric layer; 24-first contact hole; 25-second contact Hole; 30-first metal layer; 40-second metal layer; 50-first diode; 60-second diode.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

It should be noted that when an element is referred to as being “fixed” to another element, it can be directly on the other element or there can also be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and similar expressions are used herein for purposes of illustration only.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

Referring to Fig. 1, Fig. 2 to Fig. 9, the present invention also provides a method for preparing an electrostatic protection chip for a fast charging management system, including the following steps:

S1: providing a substrate 10 of a first conductivity type, on which a first epitaxial layer 11 of a second conductivity type is formed;

Referring to Fig. 2, in the present embodiment, the first conductivity type is P-type, the second conductivity type is N-type, P-type ions are boron, N-type ions are phosphorus, and the material of substrate 10 is silicon, which is low in manufacturing cost and convenient accomplish. The first epitaxial layer 11 is prepared by epitaxial growth technology. The conductivity type of the first epitaxial layer 11 and the substrate 10 is different to form a PN junction. The epitaxial layer is a nascent single crystal layer that grows according to the crystal phase of the substrate. The silicon epitaxial growth is in On a silicon single crystal substrate with a certain crystal orientation, a layer of crystal with good lattice structure integrity and different resistivity and thickness with the same crystal orientation as the substrate is grown, and the epitaxial layer can play a supporting role.

S2: Forming a first implantation region 12 of the second conductivity type and a second implantation region 13 of the first conductivity type located on the upper surface of the first injection region 12 on the first epitaxial layer 11, in the second A second epitaxial layer 14 of the first conductivity type is formed on the upper surface of the injection region 13;

Referring to Fig. 3, in the present embodiment, the conductivity types of the first injection region 12 and the second injection region 13 are different to form a PN junction, and the doping concentration and thickness of the first injection region 12 and the second injection region 13 can be the same, or It can be different, preferably the thickness of the first implantation region 12 and the second implantation region 13 is greater than 5 μm, and the thickness of the second epitaxial layer 14 and the first epitaxial layer 11 is greater than 5 μm. The first implantation region 12 is formed by first implanting ions of the second conductivity type on the upper surface of the first epitaxial layer 11 and performing thermal annealing, while the preparation process of the second implantation region 13 is the same as that of the first implantation region 12, and then the second implantation region 13 A second epitaxial layer 14 is formed on the upper surface, the conductivity type of the second epitaxial layer 14 is the same as that of the second injection region 13 , and the thickness of the second epitaxial layer 14 is greater than that of the second injection region 13 .

It should be noted that by adjusting the ion doses of the first implanted region 12 and the second implanted region 13, the breakdown voltage of the PN junction, that is, the protection voltage of the device, will be affected. Without the protection of the second epitaxial layer 14, the implanted regions will directly In contact with the metal layer, a high doping concentration is required to form an ohmic contact with the metal layer. The ohmic contact is the connection between the metal electrode and the silicon wafer, otherwise the resistance is too large to affect the performance of the device, and the high doping concentration will also affect the device's strike. The adjustment of the breakdown voltage, the first injection region 12 and the second injection region 13 can reduce damage under the protection of the second epitaxial layer 14, and at the same time, the breakdown of the PN junction occurs inside the epitaxial layer and can reduce the leakage current, which improves to a certain extent device performance.

S3: extending from the second epitaxial layer 14 to the first epitaxial layer 11 to form first trenches 15 arranged at intervals by photolithography, filling the first trenches 15 with silicon oxide to form a silicon oxide layer 17;

Referring to Fig. 4 and Fig. 5, in this embodiment, the photoresist is firstly coated at intervals on the second epitaxial layer 14, from the upper surface of the second epitaxial layer 14 through the second implantation region 13, the first implantation region 12, the first epitaxy The layer 11 is photolithographically etched to form the first groove 15, the number of the first groove 15 is preferably two groups in total, and the distance between the two first grooves 15 in each group is greater than that of the first groove 15. The width of the groove 15. The bottom of the first trench 15 is located in the first epitaxial layer 11, which can ensure that the second implantation region 13, the first implantation region 12, the second epitaxial layer 14 and the first epitaxial layer 11 are isolated by the first trench 15, and the first trench Filling the groove 15 with silicon oxide can be used as an isolation trench to reduce the leakage current of the device.

S4: Etching the upper surface of the second epitaxial layer 14 located between the first trenches 15 to form a penetrating through the second epitaxial layer 14, the second implantation region 13 and the first implantation region 12 and Extending to the second trench 16 in the first epitaxial layer 11, the junction depth of the second trench 16 is smaller than the junction depth of the first trench 15;

Referring to FIG. 6, in this embodiment, firstly, a photoresist is applied to the upper surface of the second epitaxial layer 14 and the silicon oxide layer 17 to expose the second epitaxial layer 14 between the first grooves 15 and perform photolithography. method etching technology, form the second trench 16 from the upper surface of the second epitaxial layer 14, the second implantation region 13, the first implantation region 12 and the first epitaxial layer 11, and the junction depth of the second trench 16 is smaller than that of the first trench The width of the groove 15 and the second groove 16 is larger than that of the first groove 15, so that the device has bidirectional characteristics, which is convenient for the subsequent manufacturing process.

S5: filling the second trench 16 with ions of the second conductivity type to form a third epitaxial layer 18;

Referring to FIG. 7 , in this embodiment, the second trench 16 is filled with ions of the second conductivity type, that is, N-type ions to form a third epitaxial layer 18. The doping concentration of the third epitaxial layer 18 is greater than that of the first epitaxial layer 11. The triple epitaxial layer 18 is located between the two first trenches 15, which can ensure the uniform flow of current inside the device and improve the working stability of the device.

S6: performing ion implantation of the first conductivity type in the third epitaxial layer 18 and in the second epitaxial layer 14 between the first trenches 15 to form a third implantation region 20 and a fourth implantation region 21;

Referring to FIG. 8 , in this embodiment, photolithography is carried out in the third epitaxial layer 18 and the second epitaxial layer 14, and the third implantation region 20 is formed in the third epitaxial layer 18 by etching, and the third implantation region 20 is formed in the second epitaxial layer 14. The fourth injection region 21, the third injection region 20 and the fourth injection region 21 are formed by etching simultaneously, the doping concentration of the third injection region 20 and the fourth injection region 21 is higher than that of the second injection region 13, and the third injection region 20 and the fourth injection region 21 are formed by etching at the same time. The conductivity types of the three epitaxial layers 18 are different to form a PN junction, the conductivity type of the fourth injection region 21 is the same as that of the second epitaxial layer 14, and the increase in the depth of the PN junction increases the withstand voltage performance of the device. The third injection region 20 is arranged symmetrically with respect to the fourth injection region 21, and the projected area of the fourth injection region 21 in the direction perpendicular to the substrate 10 is larger than the third injection region 20, which facilitates the subsequent contact area between the metal and the semiconductor to reduce conduction. resistance, reducing the conduction loss of the device.

S7: Perform dielectric growth on the upper surface of the second epitaxial layer 14, respectively remove the dielectric corresponding to the upper surface of the third implantation region 20 and the fourth implantation region 21 to form a first contact hole 24 and a second contact hole 25 , retaining the second epitaxial layer 14, the silicon oxide layer 17, the third epitaxial layer 18 and part of the dielectric on the upper surface of the third implantation region 20 to form a first dielectric layer 22 arranged at intervals, and retaining part of the The medium on the upper surface of the third injection region 20, the third epitaxial layer 18, the second epitaxial layer 14 and part of the fourth injection region 21 forms a second dielectric layer 23 arranged at intervals;

Referring to FIG. 9, in this embodiment, dielectric growth is first performed on the second epitaxial layer 14, the silicon oxide layer 17, the third epitaxial layer 20, the third implantation region 20 and the fourth implantation region 21, and the third implantation region 20 and the fourth implantation region 21 are removed. The medium on the upper surface of the fourth implantation region 21 forms the first contact hole 24 and the second contact hole 25 respectively, and the second epitaxial layer 14, the silicon oxide layer 17, the third epitaxial layer 18 and part of the upper surface of the third implantation region 20 remain. Dielectric forms the first dielectric layer 22, and also retains part of the third implantation region 20, the third epitaxial layer 18, the silicon oxide layer 17, the second epitaxial layer 14, and part of the dielectric on the upper surface of the fourth implantation region 21 to form the second dielectric layer 23 , the first contact hole 24 is located between the first dielectric layer 22 and the second dielectric layer 23, the second contact hole 25 is located between the two second dielectric layers 23, and the size of the second contact hole 25 is larger than that of the first contact hole 24 . The first dielectric layer 22 , the second dielectric layer 23 , the first contact hole 24 and the second contact hole 25 are formed by dry etching, and the first contact hole 24 is arranged symmetrically with respect to the second contact hole 25 .

S8: filling the first contact hole 24 and the upper surface of the first dielectric layer 22 with metal to form the first metal layer 30, and filling the upper surface of the second dielectric layer 23 and the second contact hole 25 with metal A second metal layer 40 is formed, and the first metal layer 30 is arranged symmetrically with respect to the second metal layer 40 .

Referring to FIG. 9 again, in this embodiment, the first dielectric layer 22, the second dielectric layer 23, the first contact hole 24, and the second contact hole 25 are filled with metal by magnetron sputtering technology, and then dry etching technology is used Remove part of the metal on the second dielectric layer 23, the first metal layer 30 is L-shaped, the second metal layer 40 is T-shaped, the first metal layer 30 is symmetrically arranged with respect to the second metal layer 40, the first metal layer 30 and the second metal layer The two metal layers 40 are both located on the upper surface of the substrate 10, the first metal layer 30 and the second metal layer 40 can be connected to the circuit as two electrodes of the device, and the second metal layer 40 is the position where the leakage circuit is connected. The device can implement bidirectional protection.

It should be noted that the preparation process of the device only uses simple process integration to realize the parallel connection of multiple bidirectional protection circuits. The parasitic capacitance of the device is reduced through the first trench 15, that is, the isolation trench, which can meet the requirements of the fast charging source management system. In order to meet the protection requirements of high-frequency devices, the second trench 16, that is, the deep trench, is filled with N-type epitaxy, and ion implantation is performed in the N-type epitaxial layer to form a PN junction, which ensures the interface quality of the PN junction and reduces device leakage. The discharge structure adopts the groove form, which improves the discharge density and reduces the manufacturing cost of the device.

Referring to FIG. 9 again, the present invention also provides an electrostatic protection chip for a fast charging management system, including:

a substrate 10 of the first conductivity type;

a first epitaxial layer 11 of a second conductivity type formed on the substrate 10;

The first injection region 12 of the second conductivity type formed on the upper surface of the first epitaxial layer 11, the second injection region 13 of the first conductivity type formed on the first injection region 12, and the second injection region 13 formed on the first injection region 12, and the the second epitaxial layer 14 of the first conductivity type on the upper surface of the second injection region 13;

The first trenches 15 extending from the second epitaxial layer 14 into the first epitaxial layer 11 and arranged at intervals, the second trenches 16 between the first trenches 15, the first trenches The groove 15 is filled with a silicon oxide layer 17, the second groove 16 is filled with a third epitaxial layer 18 of the second conductivity type, and the junction depth of the second groove 16 is smaller than that of the first groove 15. Knot deep;

A third implantation region 20 of the first conductivity type formed in the third epitaxial layer 18, a fourth implantation region of the first conductivity type formed in the second epitaxial layer 14 between the first trenches 15 twenty one;

The first dielectric layer 22 arranged at intervals on the surface of the second epitaxial layer 14, the silicon oxide layer 17, the third epitaxial layer 18 and part of the third implantation region 20 is formed on part of the first Three injection regions 20, the third epitaxial layer 18, the second epitaxial layer 14, and a second dielectric layer 23 arranged at intervals on the upper surface of part of the fourth injection region 21;

Forming a first contact hole 24 between the first dielectric layer 22 and the second dielectric layer 23, and a second contact hole 25 between the second dielectric layer 23, the first contact hole 24 and the upper surface of the first dielectric layer 22 to form a first metal layer 30, the upper surface of the second dielectric layer 23 and the second contact hole 25 to form a second metal layer 40, the first metal layer 30 are arranged symmetrically with respect to the second metal layer 40 .

In this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, and the first trench 15 extends along the upper surface of the second epitaxial layer 14 into the first epitaxial layer 11 to achieve isolation and reduce leakage current. . The conductivity type of the first epitaxial layer 11 is different from that of the substrate 10 to form a PN junction. The second trench 16 is located between the two first trenches 15, the junction depth of the second trench 16 is smaller than the first trench 15, the second trench 16 is filled with the third epitaxial layer 18, and the first trench 15 The silicon oxide layer 17 is filled, the first trench 15 is an isolation trench, and the second trench 16 can realize bidirectional protection of the device. The doping concentration of the third epitaxial layer 18 is greater than that of the first epitaxial layer 11, and the second epitaxial layer 14 can protect the second implantation region 13 and the first implantation region 12 from etching damage, while the first implantation region 12 and the second implantation region The breakdown of the PN junction formed by the different conductivity types of the region 13 occurs in the epitaxial layer of the device, which can reduce the leakage current and improve the withstand voltage performance of the device. The third injection region 20 and the fourth injection region 21 have the same conductivity type and are prepared and formed at the same time. The third injection region 20 is arranged symmetrically with respect to the fourth injection region 21. The third injection region 20 forms a PN junction with the third epitaxial layer 18, and the fourth injection region 20 forms a PN junction with the third epitaxial layer 18. The conductivity type of the implanted region 21 and the second epitaxial layer 14 is the same, and the doping concentration of the third implanted region 20 and the fourth implanted region 21 is higher than that of the second implanted region 13, which can increase the current path and uniform current distribution inside the device.

Referring to Fig. 10 and Fig. 11, it should be noted that, when the device is connected to the circuit, the first metal layer 30 is connected to the voltage input terminal, and the first metal layer 30 on the other side can also be connected to another voltage input terminal. The second metal layer 40 can be connected to the voltage output terminal, the third implantation region 20, the third epitaxial layer, the first epitaxial layer 11, the first implantation region 12, the second implantation region 13, the second epitaxial layer 14 and the fourth implantation region The current path where the area 21 is located, that is, P-N-N-P, can be used as an electrostatic protection circuit, and the second metal layer 40 is where the protection leakage circuit is connected, and the device can realize dual-circuit protection. Wherein, the third injection region 20 and the third epitaxial layer 18 form a first diode 50, that is, a P-N junction. The first epitaxial layer 11, the first injection region 12, the second injection region 13, the second epitaxial layer 14 and the second The four injection regions 21 form the second diode 60, that is, the N-P structure, similar to the bidirectional TVS, the first metal layer 30 and the second metal layer 40 are located on the upper surface of the substrate 10, which can realize multi-channel bidirectional protection and improve the reliability of the device. application range.

The present invention provides an electrostatic protection chip for a fast charging management system and a preparation method thereof. By forming a first epitaxial layer 11 having a conductivity type different from that of the substrate on a substrate 10, the upper surface of the first epitaxial layer 11 is sequentially The first injection region 12 and the second injection region 13 with different conductivity types are prepared, and the formation of a PN junction between the first injection region 12 and the second injection region 13 can enhance the withstand voltage performance of the device. A second epitaxial layer 14 of the same conductivity type as the second implanted region 13 is formed on the upper surface of the second implanted region 13, the second epitaxial layer 14 can protect the first implanted region 12 and the second implanted region 13 and reduce etching damage, and also Can reduce the leakage current in the device. Extending from the second epitaxial layer 14 to the first epitaxial layer 11, a first trench 15 is formed, and the first trench 15 is filled with a silicon oxide layer 17, which can be used as an isolation trench and form multiple current paths. A second trench 16 is formed between the trenches 15, the junction depth of the second trench 16 is smaller than that of the first trench 15, and the second trench 16 is filled with a third epitaxial layer 18 having a doping concentration greater than that of the first epitaxial layer 11, The third epitaxial layer 18 and the upper surface of the second epitaxial layer 14 form a third implantation region 20 and a fourth implantation region 21 respectively. The conductivity type of the third implantation region 20 is different from that of the third epitaxial layer 18 to form a PN junction. A corresponding first metal layer 30 is formed on the upper surface of the substrate 10, and a corresponding second metal layer 40 is formed on the upper surface of the fourth injection region 21. The first metal layer 30 and the second metal layer 40 are located on the upper surface of the substrate 10, which can simplify the device manufacturing process. . The device is integrated with a simple process, which can realize the parallel connection of multiple bidirectional protection circuits. The isolation trench can reduce the parasitic capacitance of the device and meet the protection requirements of high-frequency devices in the fast charging power management system. Fill the third epitaxial layer 18 in the second trench 16 and perform ion implantation to form a PN junction, which ensures the interface quality of the PN junction and reduces the leakage of the device. The discharge structure adopts the form of a trench, which improves the discharge density and reduces the device. manufacturing cost.

In all examples shown and described herein, any specific values should be construed as merely exemplary and not limiting, and thus other examples of the exemplary embodiments may have different values.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

The above-mentioned embodiments only express several implementations of the present invention, and the description thereof is relatively specific and detailed, but should not be construed as limiting the scope of the present invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims (10)

1. An electrostatic protection chip for a rapid charge management system, comprising:

a substrate of a first conductivity type;

a first epitaxial layer of a second conductivity type formed on the substrate;

the epitaxial wafer comprises a first epitaxial layer, a second epitaxial layer and a first epitaxial layer, wherein the first epitaxial layer is formed on the upper surface of the first epitaxial layer;

the second epitaxial layer is arranged in the first epitaxial layer, the first epitaxial layer is arranged in the first epitaxial layer, the second epitaxial layer is arranged in the second epitaxial layer, the second epitaxial layer is arranged in the first epitaxial layer, the second epitaxial layer is arranged in the second epitaxial layer, and the junction depth of the second trench is smaller than that of the first trench;

a third implanted region of the first conductivity type formed in the third epitaxial layer, a fourth implanted region of the first conductivity type formed in the second epitaxial layer between the first trenches;

forming first dielectric layers arranged at intervals on the upper surfaces of the second epitaxial layer, the silicon oxide layer, the third epitaxial layer and part of the third injection region, and forming second dielectric layers arranged at intervals on the upper surfaces of part of the third injection region, the third epitaxial layer, the second epitaxial layer and part of the fourth injection region;

and forming a first contact hole between the first dielectric layer and the second dielectric layer and a second contact hole between the second dielectric layer, wherein a first metal layer is formed in the first contact hole and the upper surface of the first dielectric layer, a second metal layer is formed in the upper surface of the second dielectric layer and the second contact hole, and the first metal layers are symmetrically arranged relative to the second metal layer.

2. The ESD chip for rapid charge management system according to claim 1, wherein the first conductivity type is P-type, the second conductivity type is N-type, and the width of the first trench is smaller than the width of the second trench.

3. The ESD chip of claim 1, wherein the junction depths of the first and second implanted regions are the same, and the doping concentration of the first implanted region is the same as the doping concentration of the second implanted region.

4. The esd protection chip for rapid charge management system of claim 1, wherein the doping concentration of the third epitaxial layer is greater than the doping concentration of the first epitaxial layer.

5. The ESD chip of claim 1, wherein the third implant region has an ion concentration greater than the second implant region.

6. The electrostatic protection chip for a rapid charge management system according to claim 1, wherein the size of the first contact hole is smaller than the size of the second contact hole.

7. A preparation method of an electrostatic protection chip for a quick charge management system is characterized by comprising the following steps:

providing a substrate of a first conductive type, and forming a first epitaxial layer of a second conductive type on the substrate;

forming a first injection region of a second conductive type and a second injection region of the first conductive type on the upper surface of the first injection region on the first epitaxial layer, and forming a second epitaxial layer of the first conductive type on the upper surface of the second injection region;

photoetching the second epitaxial layer to form first trenches arranged at intervals, and filling silicon oxide into the first trenches to form a silicon oxide layer;

etching the upper surface of the second epitaxial layer between the first trenches to form a second trench which penetrates through the second epitaxial layer, the second injection region and the first injection region and extends into the first epitaxial layer, wherein the junction depth of the second trench is smaller than that of the first trench;

filling second conductive type ions into the second groove to form a third epitaxial layer;

respectively performing first conductive type ion implantation in the third epitaxial layer and the second epitaxial layer between the first trenches to form a third implantation region and a fourth implantation region;

growing a medium on the upper surface of the second epitaxial layer, respectively removing the corresponding medium on the upper surfaces of the third injection region and the fourth injection region to form a first contact hole and a second contact hole, retaining the medium on the upper surfaces of the second epitaxial layer, the silicon oxide layer, the third epitaxial layer and part of the third injection region to form first medium layers arranged at intervals, and retaining part of the medium on the upper surfaces of the third injection region, the third epitaxial layer, the second epitaxial layer and part of the fourth injection region to form second medium layers arranged at intervals;

and filling metal into the first contact hole and the upper surface of the first dielectric layer to form a first metal layer, filling metal into the upper surface of the second dielectric layer and the second contact hole to form a second metal layer, wherein the first metal layer is symmetrically arranged relative to the second metal layer.

8. The method of manufacturing an electrostatic protection chip for a rapid charge management system according to claim 7, wherein the thickness of the first epitaxial layer and the second epitaxial layer is greater than 5 μm.

9. The method for manufacturing an electrostatic protection chip for a rapid charging management system according to claim 7, wherein the first trench and the second trench are manufactured by dry etching, and the first metal layer and the second metal layer are manufactured by magnetron sputtering.

10. The method as claimed in claim 7, wherein a projected area of the third implantation region in a direction perpendicular to the substrate is smaller than a projected area of the fourth implantation region in a direction perpendicular to the substrate.

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