CN108520896B

CN108520896B - Voltage-resistant bipolar transistor and manufacturing method thereof

Info

Publication number: CN108520896B
Application number: CN201810413790.4A
Authority: CN
Inventors: 樊庆扬; 张文柱; 卫铭斐
Original assignee: Xian University of Architecture and Technology
Current assignee: Xian University of Architecture and Technology
Priority date: 2018-05-03
Filing date: 2018-05-03
Publication date: 2021-01-01
Anticipated expiration: 2038-05-03
Also published as: CN108520896A

Abstract

The invention discloses a voltage-resistant bipolar transistor and a manufacturing method thereof, and mainly solves the problems of weak resistance and low voltage-resistant value of the existing bipolar transistor in an EMP environment. It comprises a substrate (1), a heavily doped collector region (2), an epitaxial layer (3), a base region (4), an emitter region (5), a _SiO2 layer (6), _SiO2 trenches and vias . The heavily doped collector region is cylindrical and located in the epitaxial layer, and the epitaxial layer is divided into two parts: the cylindrical epitaxial layer and the cylindrical epitaxial layer; the cylindrical epitaxial layer includes a cylindrical base region and an emitter region. SiO ₂ trenches with the same junction depth; the base region contains a ring-shaped emitter region. The method of the invention effectively reduces the current edge-collecting effect on the emitter junction, thereby improving the withstand voltage characteristic of the collector junction; and solves the problem in the prior art that only protecting specific input and output terminals cannot improve the overall withstand voltage characteristics of the transistor , to achieve the purpose of improving the reliability of the transistor as a whole.

Description

Voltage-resistant bipolar transistor and manufacturing method thereof

Technical Field

The invention belongs to the technical field of semiconductor devices, in particular to an NPN type voltage-resistant bipolar transistor which can be used for manufacturing power devices, digital logic circuit devices or power electronic devices and the like.

Background

When a small amount of current is injected into the base region of the transistor biased in the amplifying region, the base current is amplified between the emitter region and the collector region, which is the amplifying effect of the transistor. With the development of pulse power technology and the improvement of microelectronic process technology, high-frequency power transistor devices are widely applied to communication systems, however, in practical conditions, the current electromagnetic environment is gradually worsened by means of high-power microwaves generated by various pulse power generation devices under various frequencies, and the electromagnetic application environment of various communication systems is more and more severe. Most semiconductor devices belong to micro-power consumption and micro-structure devices, reliability of the semiconductor devices is easily reduced or even completely failed under the action of external electric stress, electromagnetic pulse EMP is one of main reasons for generating external electric stress, and the semiconductor devices are extremely destructive. In recent years, the integration level of semiconductor devices has been greatly improved, the geometric dimensions have been further reduced, and the semiconductor devices are more and more susceptible to damage caused by the influence of EMP, and the mechanism of the EMP damaging the semiconductor devices has become one of the research hotspots in the field. The EMP is a burst high-intensity pulse of broadband electromagnetic radiation, and the characteristics of high power, short pulse, strong current and the like enable the EMP to have strong nonlinear electromagnetic response with an electronic system, and in addition, the thermal effect of the EMP can also heat a target, so that the temperature of various electronic devices contained in the electronic system is increased, and the devices are damaged or fail to function. Therefore, in the application design of the microwave power transistor device, it is required to provide a high output power and a high gain, and have a strong capability of withstanding short-time high-voltage pulses.

At present, in practical application, the scheme for solving the EMP effect in the circuit is mainly to connect two clamping pn junctions in parallel to the input end of the circuit and conduct the EMP signal of high voltage and large current to the power end so as to avoid the damage of a transistor, but the method only resists the EMP through a peripheral circuit and the withstand voltage value of the transistor is not improved; or, the circuit is mainly protected from the EMP attack, for example, the BVcbo is improved by performing trench field oxidation isolation on the transistor as proposed in CN 103346085B, "a manufacturing process for improving the BVcbo of the bipolar transistor"; for a circuit with the output end of the transistor vulnerable to EMP, the transistor which is subjected to key protection design aiming at the collector junction of the output end is adopted. However, in the EMP environment, the electromagnetic pulse signal may enter through any port of the circuit, and does not enter into the circuit from a certain port of the circuit, and the EMP signal entering into the circuit in an injection or coupling manner may still cause damage to the transistor. Only the specific input and output ends are protected, and the voltage withstanding characteristic of the transistor cannot be improved on the whole.

Disclosure of Invention

The invention aims to provide a voltage-resistant bipolar transistor and a manufacturing method thereof aiming at the problems of weak resistance and low voltage resistance value of the existing bipolar transistor in an EMP environment.

In order to achieve the purpose, the invention provides a voltage-resistant bipolar transistor which comprises a substrate (1), an epitaxial layer (3) on the substrate, a heavily doped collector region (2), a base region (4) and SiO in the epitaxial layer₂Trench, emitter region (5) in base region, SiO uppermost cladding₂Layer (6) and SiO₂A via in the layer; the method is characterized in that:

the heavily doped collector region (2) is a cylindrical heavily doped region, and the epitaxial layer (3) is divided into a cylindrical inner epitaxial layer and a cylindrical outer epitaxial layer by the region;

the cylindrical epitaxial layer comprises a cylindrical base region (4) and SiO with the same junction depth as the emitter region (5)₂A trench;

SiO₂epitaxial layers are arranged among the grooves, the heavily doped collector region (2) and the base region (4) at intervals, and the two epitaxial layers are not in contact with each other;

the base region (4) includes an annular emitter region (5).

In addition, the invention also provides a manufacturing method of the voltage-resistant bipolar transistor, which comprises the following specific steps:

1) selecting monocrystalline silicon as an initial material as a substrate;

2) under the vacuum condition, generating an N-type low-concentration doped epitaxial layer on a monocrystalline silicon substrate through chemical vapor deposition, namely a collector region of the transistor;

3) growing a layer of silicon dioxide on the surface of the epitaxial layer through a thermal oxidation process, then coating photoresist in a spinning mode, and exposing by utilizing a photoetching machine to make a cylindrical pattern of a heavily doped region; selectively doping impurities into the cylindrical pattern region by ion implantation to form a heavily doped collector region of the device, and removing residual silicon dioxide and photoresist; at the moment, the epitaxial layer is divided into a cylindrical inner epitaxial layer and a cylindrical outer epitaxial layer by the heavily doped collector region;

4) growing a layer of silicon dioxide on the surface of the epitaxial layer by a thermal oxidation process, then coating photoresist in a spinning mode, and exposing by utilizing a photoetching machine to form a grooveEtching off silicon dioxide and epitaxial layer by dry etching technique to form a SiO layer with the same junction depth as emitter region₂Removing residual silicon dioxide and photoresist;

5) injecting boron ions into the epitaxial layer inside and outside the cylinder through an ion injection process to form a circular base region;

6) injecting phosphorus ions into the base region through an ion injection process to form an annular emitter region;

7) and 6) padding a layer of silicon dioxide on the uppermost part of the device after the step 6), then photoetching to form contact holes of a heavily doped collector region, a base region and an emitter region, and finally forming electrodes through a metal wiring process.

It can be seen from the above description of the method for manufacturing a voltage-withstanding transistor according to the present invention that an annular emitter region, a cylindrical base region, and a cylindrical heavily doped collector region are respectively formed in a lightly doped epitaxial layer by an ion implantation process, wherein a lightly doped epitaxial layer region is separated between the base region and the heavily doped collector region, and the highly resistive lightly doped region can distribute a higher voltage drop in the process of injecting a strong pulse from a collector, thereby improving the voltage-withstanding characteristic of the transistor.

Compared with the prior art, the invention has the following advantages:

first, the invention adopts the annular structure for the emitter region, and the BE junction area is increased through the annular emitter region, thereby overcoming the problem of larger current density of the BE junction in the prior art and effectively improving the breakdown voltage value of the BE junction.

Secondly, because the invention manufactures SiO at the position of BC junction close to the collector₂Trenches, here SiO₂The insertion of the first and second conductive layers solves the problem of current edge effect of the BC junctions, so that the breakdown voltage value between the BC junctions is improved;

drawings

FIG. 1 is a schematic diagram of a transistor structure corresponding to step e) in a device manufacturing process of the present invention, wherein (a) is a top view and (b) is a cross-sectional view;

FIG. 2 is a schematic cross-sectional view of a device of the present invention;

fig. 3 is a schematic flow chart of a manufacturing process of the device of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described with reference to the accompanying drawings and specific embodiments.

Referring to fig. 1, 2 and 3, the device of the invention comprises a substrate 1, a heavily doped collector region 2, an epitaxial layer 3, a base region 4, an emitter region 5, SiO₂Layer 6, SiO₂Trenches and vias. Wherein, the substrate 1 is the lowest layer and adopts monocrystalline silicon; the heavily doped collector region 2 is cylindrical and is positioned in the epitaxial layer 3; the epitaxial layer 3 is doped on the substrate by adopting N type low concentration; the base region 4 is positioned in the epitaxial layer 3 surrounded by the heavily doped collector region 2; the emitter region 5 is positioned in the base region 4 and is annular, and the distance of the inner diameter of the emitter region is equal to the distance from the outer edge of the emitter region to the inner edge of the epitaxial layer; SiO 2₂The trench is SiO embedded in the epitaxial layer 3₂A layer; SiO 2₂ Layer 6 is the oxide layer that finally covers over the device; the through holes are respectively two base electrode contact holes, two emitter electrode contact holes and a heavy doping collector electrode contact hole.

Referring to fig. 3, the steps of manufacturing the voltage-resistant bipolar transistor provided by the present invention are as follows:

example 1:

step 1: a substrate is selected.

Firstly, selecting lightly doped P-type silicon as an initial material to be used as a substrate;

step 2: and growing an epitaxial layer.

Generating a low-concentration epitaxial layer 3 doped in N type on top of a silicon substrate 1 by chemical vapor deposition under vacuum condition, the doping concentration being in the order of 8e15cm^-3The doping element is arsenic with the thickness of 2 um-10 um. The epitaxial layer is used as a collector region of the transistor;

and step 3: and manufacturing a heavily doped collector region.

Growing a layer of silicon dioxide on the surface of the epitaxial layer by a thermal oxidation process, then spin-coating photoresist, exposing by using a photoetching machine, making a cylindrical graph of a heavily doped region, namely a region 2 shown in figure 1a), etching a heavily doped collector region needing ion implantation, and selectively doping impurity arsenic into a preset region by ion implantation to form a heavily doped collector region of the device, wherein the thickness of the heavily doped collector region is 0.2 mu m; the doping elements in the epitaxial layer are the same as the impurity elements in the epitaxial layer and are higher than the doping concentration of the epitaxial layer by one order of magnitude, so that good ohmic contact with the metal electrode is formed conveniently; and removing the residual silicon dioxide and the photoresist.

At the moment, the epitaxial layer is divided into a cylindrical inner epitaxial layer and a cylindrical outer epitaxial layer by the heavily doped collector region.

And 4, step 4: and manufacturing a groove.

Growing a layer of thin silicon dioxide on the surface of the epitaxial layer by a thermal oxidation process, then coating photoresist in a spinning way, exposing by using a photoetching machine, making a pattern needing groove oxidation, and etching the silicon dioxide and the epitaxial layer by using a dry etching technology, thereby forming a SiO with the same junction depth as that of an emitter region₂Trenches, i.e. SiO within the region 3 in FIG. 2₂The groove can inhibit lateral breakdown between the collector region and the base region; and removing the residual silicon dioxide and the photoresist.

Cylindrical heavily doped collector region, SiO₂The trench and the base region are not contacted with each other, and low-concentration collector regions are arranged at intervals, namely, the low-concentration collector regions are separated by the N-type doped low-concentration epitaxial layer.

And 5: and manufacturing a base region.

Implanting boron element into the lightly doped epitaxial layer surrounded by the cylindrical heavily doped collector region by ion implantation to form a circular base region 4 with a doping concentration of 5e16cm^-3(ii) a The thickness of a light doped epitaxial layer separated between the circular base region and the cylindrical heavy doped collector region is 0.3-0.4 um, so that the capacitance between the base region and the collector region can be effectively reduced; the height of the cylinder in the longitudinal direction of the lightly doped epitaxial layer is consistent with the diameter length of the bottom surface of the cylinder in the transverse direction.

Step 6: and manufacturing an emitting area.

Phosphorus is implanted into the base region by an ion implantation process to form an annular emitter region, i.e., region 5, having a doping concentration of 3e18cm^-3(ii) a The inner diameter distance of the circular emitting region is equal to the distance from the outer edge of the circular emitting region to the inner edge of the epitaxial layer.

And 7: and (5) manufacturing an electrode.

Finally, a layer of silicon dioxide is laid on the upper surface of the device completed in the step 6, after a proper thermal process impurity activation process is carried out, contact holes of a base electrode, an emitting electrode and a collector electrode are formed by utilizing a photoetching and etching method, and the step is shown in a figure 3 (g); the contact holes, namely the through holes, formed in the contact structure are totally 5, namely two base contact holes, two emitter contact holes and a heavy doping collector contact hole, and the positions of the contact holes are as follows:

a base contact hole: one above the middle base region and the other near SiO₂The position above the base region of the trench;

heavily doped collector contact hole: located near SiO₂The position above the heavily doped collector region of the trench; the contact hole of the collector electrode is arranged at the position closest to SiO₂A through hole is formed above the heavily doped collector region of the groove and is communicated to the top end of the surface; then the contact resistance of the electrode is reduced through silicide process treatment;

emitter contact holes: one is located near SiO₂One above the emitter region of the trench and the other away from the SiO₂A position above the emitter region of the trench.

Finally, forming an electrode through a metal wiring process; close to SiO₂The trench oxide layer existing between the b c junction formed by the base b and the heavily doped collector c of the trench functions to reduce the current crowding effect between the b c junctions.

After the metal connecting lines of each electrode are formed by the metal wiring process, the passivation layer process is used for surface passivation treatment, so that the surface of the transistor is protected from adverse environmental factors.

Example 2:

step 1: a substrate is selected.

step 2: and growing an epitaxial layer.

Generating a low-concentration epitaxial layer 3 doped in N type on the top of the silicon substrate 1 by chemical vapor deposition under vacuum conditionOf the order of 8e15cm^-3The doping element is phosphorus, and the thickness is 2 um-10 um. The epitaxial layer serves as the collector region of the transistor.

Steps 3-7 are the same as in example 1.

Example 3:

steps 1 to 3 are the same as in example 1 or 2;

and 4, step 4: and manufacturing a groove.

Growing a layer of thin silicon dioxide on the surface of the epitaxial layer through a thermal oxidation process, then coating photoresist in a spinning mode, exposing by using a photoetching machine, making a pattern needing groove oxidation, and etching the silicon dioxide and the epitaxial layer by using a dry etching technology, thereby forming two bilaterally symmetrical SiO layers₂Trenches, respectively being the first SiO₂Trench and second SiO₂The depth of the grooves is the same as the junction depth of the emitting region; the two grooves can inhibit lateral breakdown between the collector region and the base region; and removing the residual silicon dioxide and the photoresist.

Step

5, 6 the same as example 1 or 2;

and 7: and (5) manufacturing an electrode.

Finally, a layer of silicon dioxide is laid on the upper surface of the device finished in the step 6, after a proper thermal process impurity activation process is carried out, contact holes of a base electrode, an emitting electrode and a collector electrode are formed by utilizing a photoetching and etching method; the contact holes, i.e. through holes, formed here are 7 in total, namely three base contact holes, two emitter contact holes and two heavily doped collector contact holes, which are located as follows:

a base contact hole: the first one is arranged above the middle base region, and the other two are respectively arranged near the first SiO₂Trench and near the second SiO₂The position above the base region of the trench;

heavily doped collector contact hole: one is located near the first SiO₂One of the heavily doped collector regions is located above the second SiO₂Heavy doping current collection of trenchA location above the region; the collector contact hole is processed by a silicide process, so that the contact resistance of the electrode can be effectively reduced;

emitter contact holes: one is located near the first SiO₂One above the emitter region of the trench and the other near the second SiO₂A position above the emitter region of the trench.

Finally, forming an electrode through a metal wiring process; the trench oxide layer existing between b c junctions formed by the base b and the heavily doped collector c has the function of reducing the current crowding effect between b c junctions.

Example 4:

the specific steps are the same as those of the

embodiment

1, 2 or 3, and SiO is further increased on the basis of the structure of the embodiment₂Area of trench oxide layer.

The number of structures of the trench oxide layer inserted between the b c junctions is increased, the effect achieved by the structures in the

embodiments

1, 2 or 3 can still be achieved, and the gain of the stepped tube of the structure can be improved; the current collection edge effect on the emitter junction can be reduced, the voltage withstanding characteristic of the collection junction is further improved, and the purpose of integrally improving the reliability of the transistor is achieved. But as the area of the trench oxide layer between the b c junctions increases, the junction capacitance between the b c junctions increases further.

The invention has not been described in detail in part of the common general knowledge of those skilled in the art.

The foregoing description is only exemplary of the invention and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made therein without departing from the principles and arrangements of the invention, but such modifications and variations are within the scope of the appended claims.

Claims

1. A voltage-resistant bipolar transistor, comprising a substrate (1), an epitaxial layer (3) on the substrate, a heavily doped collector region (2), a base region (4) and a _SiO2 groove in the epitaxial layer The groove, the emitter region (5) in the base region, the uppermost covering _SiO2 layer (6) and the through hole in the _SiO2 layer; it is characterized by:

The heavily doped collector region (2) is a cylindrical heavily doped region, and the region divides the epitaxial layer (3) into two parts, a cylindrical epitaxial layer and a cylindrical epitaxial layer;

The cylindrical epitaxial layer comprises a cylindrical base region (4) and a _SiO2 trench with the same junction depth as the emitter region (5);

An epitaxial layer is spaced between the _SiO2 trench, the heavily doped collector region (2), and the base region (4), so that they are not in contact with each other;

The base region (4) includes a circular emitting region (5); and a base electrode is provided on both the central base region and the position above the base region close to the SiO ₂ trench.

2 . The transistor according to claim 1 , wherein the diameter of the annular emitting region is equal to the distance from the outer edge of the annular emitting region to the inner edge of the cylindrical epitaxial layer. 3 .

3. The transistor according to claim 1, characterized in that: there are 5 through holes in the SiO layer, which are respectively _two base contact holes, two emitter contact holes and a heavily doped collector contact hole , its location is as follows:

Base contact holes: one is located above the middle base area, and the other is located above the base area close to the SiO ₂ trench;

Heavily doped collector contact hole: located above the heavily doped collector region close to the _SiO2 trench;

Emitter contact holes: one over the emitter near the _SiO2 trench and the other over the emitter away from the _SiO2 trench.

4 . The transistor according to claim 1 , wherein the substrate is a single crystal silicon substrate, the epitaxial layer is N-type doped, the heavily doped collector region is N-type doped, and the base region is P. 5 . Type doping, the emitter region is N-type doping.

5. A method of making a voltage-resistant bipolar transistor, comprising the steps of:

1) Select single crystal silicon as the initial material as the substrate;

2) Under vacuum conditions, an N-type low-concentration doped epitaxial layer is formed on a single crystal silicon substrate by chemical vapor deposition, which is the collector region of the transistor;

3) A layer of silicon dioxide is grown on the surface of the epitaxial layer by a thermal oxidation process, then a photoresist is spin-coated, and a photolithography machine is used for exposure to make a cylindrical pattern of heavily doped regions; impurities are selectively implanted by ion implantation doping into the cylindrical pattern area to form a heavily doped collector area of the device, and then remove the residual silicon dioxide and photoresist; at this time, the epitaxial layer is divided into cylindrical epitaxy by the heavily doped collector area. layer and cylindrical epitaxial layer;

4) A layer of silicon dioxide is grown on the surface of the epitaxial layer by a thermal oxidation process, then a photoresist is spin-coated, exposed by a photolithography machine, a groove pattern is made, and a dry etching technology is used to etch away the silicon dioxide and Epitaxial layer, forming a SiO ₂ trench with the same depth as the emitter junction, and then removing the residual silicon dioxide and photoresist;

5) Through the ion implantation process, implant boron ions into the cylindrical epitaxial layer to form a cylindrical base region;

6) Phosphorus ions are implanted in the base region through an ion implantation process to form a ring-shaped emitter region;

7) A layer of silicon dioxide is deposited on the top of the device after step 6), and then contact holes of heavily doped collector region, base region and emitter region are formed by photolithography, and finally electrodes are formed by metal wiring process.

6 . The method according to claim 5 , wherein the thickness of the N-type low-concentration doped epitaxial layer between the heavily doped collector region and the base region is 0.3-0.4 um, and the longitudinal cylinder height of the layer is 0.3-0.4 um. Consistent with the diameter and length of the bottom surface of the horizontal cylinder.

7 . The method according to claim 5 , wherein the doping concentration of the epitaxial layer in step 2) is 8e15cm ⁻³ ; the doping element is arsenic or phosphorus, and the thickness is 2um˜10um. 8 .

8. The method according to claim 5, wherein the doping element of the heavily doped collector region in step 3) is the same as the doping element in the epitaxial layer, and is an order of magnitude higher than the doping concentration of the epitaxial layer ; Thickness of heavily doped collector region is 0.2um.

9 . The method according to claim 5 , wherein the concentration of implanted boron ions in step 5) is 5e16 cm ⁻³ . 10 .

10 . The method according to claim 5 , wherein the concentration of implanted phosphorus ions in step 6) is 3e18 cm ⁻³ . 11 .