CN117995893B - High-voltage anti-nuclear radiation power transistor structure and preparation method - Google Patents

Abstract

The present invention relates to the technical field of high-voltage power semiconductor devices, and in particular to a high-voltage nuclear radiation-resistant power transistor structure and a preparation method. The structure comprises: an N-type high-concentration substrate; an N-type low-concentration epitaxial layer, arranged on the N-type high-concentration substrate; a deep P-type doped gate region, wherein two deep P-type doped gate regions are symmetrically arranged on the top outer side of the N-type low-concentration epitaxial layer; a thin P-type doped base region, arranged in the middle of the top of the N-type low-concentration epitaxial layer, and the two ends of the thin P-type doped base region overlap with the top of the deep P-type doped gate region respectively; an N-type high-concentration emitter region, arranged in the middle of the top of the thin P-type doped base region; and a metal electrode. The present invention aims to solve the problems of large degradation of electrical parameters such as transistor current amplification and breakdown voltage, and functional failure under nuclear radiation conditions of power transistors, and improve the nuclear radiation resistance performance of high-voltage power transistors.

Description

A high voltage nuclear radiation resistant power transistor structure and preparation method

Technical Field

The present invention relates to the technical field of high-voltage power semiconductor devices, and in particular to a high-voltage nuclear radiation-resistant power transistor structure and a preparation method thereof.

Background technique

Power transistors are composed of multiple transistor cells to achieve high power capacity. At the same time, silicon power bipolar transistors are characterized by mature technology, low cost, and high reliability, and are widely used in electrical systems in various industries. At the same time, in practical application fields, nuclear radiation can damage semiconductor materials, causing a significant reduction in the life of minority carriers in the base region of transistors, a significant decrease in current gain, and rapid degradation of the electrical characteristics of the device. When the radiation accumulates to a certain extent, the device function fails and the electrical system cannot work.

The main methods to reduce the impact of nuclear radiation on semiconductor device parameters are: 1) Replacement of semiconductor materials, 2) Use of narrow emitter, thin base, base doping with gold or platinum, electron irradiation, etc., 3) Surface passivation technology. Each of these methods has some characteristics, which can reduce the change of transistor current gain and improve the sensitivity of the device surface to radiation, but for power devices such as high-voltage transistors with wide base and low-doping concentration epitaxial layer structure, its anti-nuclear radiation performance is difficult to be significantly improved.

Summary of the invention

The purpose of the present invention is to provide a high-voltage nuclear radiation-resistant power transistor structure and a preparation method to solve the problems of large degradation of electrical parameters such as transistor current amplification and breakdown voltage, functional failure, etc. under nuclear radiation conditions of power transistors, and to improve the nuclear radiation resistance performance of high-voltage power transistors.

In order to solve the above technical problems, the present invention provides a high-voltage nuclear radiation-resistant power transistor structure, comprising:

N-type high concentration substrate;

An N-type low-concentration epitaxial layer is disposed on the N-type high-concentration substrate;

A deep P-type doped gate region, wherein two of the deep P-type doped gate regions are symmetrically arranged on the top outer side of the N-type low-concentration epitaxial layer;

A thin P-type doped base region is arranged in the middle of the top of the N-type low-concentration epitaxial layer, and two ends of the thin P-type doped base region overlap with the top of the deep P-type doped gate region respectively;

An N-type high-concentration emitter region is arranged in the middle of the top of the thin P-type doped base region;

The metal electrodes include a collector, a base and an emitter, which are respectively arranged at the bottom of the N-type high-concentration substrate, the top of the deep P-type doped gate region and the top of the N-type high-concentration emitter region.

Preferably, the doping concentration of the N-type low-concentration epitaxial layer is 1E13 cm ^-3 -2E14 cm ^-3 , and the thickness of the N-type low-concentration epitaxial layer is 10 um -60 um.

Preferably, the P-type impurity implantation concentration of the deep P-type doped gate region is 2E13 cm ^-2 ~1E15 cm ^-2 .

Preferably, the P-type impurity implantation concentration of the thin P-type doped base region is 1E14 cm ^-2 ~ 5E15 cm ^-2 .

Preferably, the N+ ion implantation concentration of the N-type high-concentration emitter region is 1E15 cm ^-2 to 1E16 cm ^-2 .

Preferably, the top of the N-type low-concentration epitaxial layer also includes a silicon dioxide isolation dielectric layer to isolate the base and the emitter.

Preferably, the gate spacing _WG of the deep P-type doped gate region needs to be smaller than half of the depletion width _WD of the deep P-type doped gate region under high voltage working conditions, that is, 2 _WD > _WG .

The present invention also provides a method for preparing a high-voltage nuclear radiation-resistant power transistor structure, comprising the following steps:

Step 1: Prepare an N-type low-concentration epitaxial layer on an N-type high-concentration substrate;

Step 2: Grow a field oxide layer with a thickness of 0.5um~1um on the N-type low-concentration epitaxial layer, and the annealing process temperature is 950℃~1150℃;

Step 3: applying photoresist on the surface of the field oxide layer, and wet etching after exposure to form a deep P-type doped gate region;

Step 4: growing a buffer oxide layer with a thickness of 0.01um to 0.1um in the deep P-type doped gate region, and the annealing process temperature is 900℃ to 1000℃;

Step 5: Use an ion implanter to perform P-type impurity implantation and annealing, and complete the diffusion of the deep P-type doped gate region at high temperature. The annealing process temperature is 1100°C~1200°C;

Step 6: Apply photoresist on the surface of the deep P-type doped gate region, and wet-etch to form a thin P-type doped base region after exposure, and then perform base region P-type impurity implantation and annealing, wherein the annealing process temperature is 950°C~1050°C;

Step 7: Apply photoresist on the surface of the thin P-type doped base region, wet-etch to form an N-type high-concentration emitter region after exposure, and then perform N+ ion implantation and annealing, with the annealing process temperature being 900°C to 1000°C;

Step 8: Apply photoresist on the surface of the N-type high-concentration emitter region and the deep P-type doped gate region, and form contact holes by wet etching after exposure;

Step 9: Deposit 1um~2um thick metal aluminum on the contact hole and perform photolithography etching to form the corresponding base and emitter;

Step 10: Thinning the back side of the N-type high-concentration substrate, metallizing the back side after thinning and photoetching to form a corresponding collector electrode.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention takes semiconductor device physics as its theoretical basis and applies charge balance theory in structural design, and proposes a power transistor structure and preparation method having a thin base region feature, which can achieve high withstand voltage and can work reliably in a nuclear radiation environment. The structure can effectively suppress the degradation of electrical parameters such as transistor current amplification and breakdown voltage under nuclear radiation conditions, thereby significantly improving its anti-nuclear radiation performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a high-voltage nuclear radiation-resistant power transistor according to the present invention.

FIG. 2 is a schematic diagram of an equivalent circuit of a high voltage nuclear radiation resistant transistor of the present invention.

FIG3 is a schematic diagram of growing an N-type low-concentration epitaxial layer on an N-type high-concentration substrate according to the present invention.

FIG. 4 is a schematic diagram of deep P-type ion implantation and diffusion annealing according to the present invention.

FIG. 5 is a schematic diagram of ion implantation doping and diffusion annealing of a thin P-type base region according to the present invention.

FIG. 6 is a schematic diagram of forming an emitter region by performing N-type high-concentration ion implantation and annealing according to the present invention.

FIG. 7 is a schematic diagram of the present invention performing metal aluminum deposition and photolithography etching to form a metal electrode.

FIG8 is a schematic diagram of the layout structure design of the high-voltage nuclear radiation resistant transistor structure of the present invention.

In the figure: 1-N-type high concentration substrate, 2-N-type low concentration epitaxial layer, 3-deep P-type doped gate region, 4-thin P-type doped base region, 5-N-type high concentration emitter region, 6-metal electrode.

Detailed ways

The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

As shown in FIG1 , an embodiment of the present invention provides a high-voltage nuclear radiation-resistant power transistor structure, including:

N-type high concentration substrate 1;

An N-type low-concentration epitaxial layer 2 is disposed on an N-type high-concentration substrate 1;

Deep P-type doped gate regions 3, two deep P-type doped gate regions 3 are symmetrically arranged on the top outer side of the N-type low-concentration epitaxial layer 2;

A thin P-type doped base region 4 is arranged in the middle of the top of the N-type low-concentration epitaxial layer 2, and two ends of the thin P-type doped base region 4 overlap with the top of the deep P-type doped gate region 3 respectively;

An N-type high-concentration emitter region 5 is arranged in the top middle portion of the thin P-type doped base region 4;

The metal electrode 6 includes a collector, a base and an emitter, which are arranged at the bottom of the N-type high-concentration substrate 1, the top of the deep P-type doped gate region 3 and the top of the N-type high-concentration emitter region 5 respectively.

Furthermore, a silicon dioxide isolation dielectric layer is disposed on the top of the N-type low-concentration epitaxial layer 2 to isolate the base and the emitter.

As shown in FIGS. 3 to 7 , the present invention also provides a method for preparing a high-voltage nuclear radiation-resistant power transistor structure, comprising the following steps:

Step 1: preparing an N-type low-concentration epitaxial layer 2 on an N-type high-concentration substrate 1; the doping concentration of the N-type low-concentration epitaxial layer 2 is 1E13cm ^-3 ~2E14cm ^-3 , and the thickness of the N-type low-concentration epitaxial layer 2 is 10um~60um;

Step 2: growing a field oxide layer with a thickness of 0.5um to 1um on the N-type low-concentration epitaxial layer 2, and the annealing process temperature thereof is 950°C to 1150°C;

Step 3: coating a photoresist on the surface of the field oxide layer, and performing wet etching after exposure to form a deep P-type doped gate region 3;

Step 4: growing a buffer oxide layer with a thickness of 0.01um to 0.1um in the deep P-type doped gate region 3, and the annealing process temperature is 900°C to 1000°C;

Step 5: perform P-type impurity implantation and annealing through an ion implanter, and complete the diffusion of the deep P-type doped gate region 3 at high temperature. The P-type impurity implantation concentration of the deep P-type doped gate region 3 is 2E13cm ^-2 ~1E15cm ^-2 , and the annealing process temperature is 1100℃~1200℃;

Step 6: Apply photoresist on the surface of the deep P-type doped gate region 3, and wet-etch to form a thin P-type doped base region 4 after exposure, and then perform base region P-type impurity implantation and annealing. The P-type impurity implantation concentration of the thin P-type doped base region 4 is 1E14cm ^-2 ~5E15cm ^-2 , and the annealing process temperature is 950℃~1050℃;

Step 7: Apply photoresist on the surface of the thin P-type doped base region 4, and wet-etch to form an N-type high-concentration emitter region 5 after exposure, and then perform N+ ion implantation and annealing. The N+ ion implantation concentration of the N-type high-concentration emitter region 5 is 1E15cm ^-2 ~1E16cm ^-2 , and the annealing process temperature is 900℃~1000℃;

Step 8: coating photoresist on the surface of the N-type high-concentration emitter region 5 and the deep P-type doped gate region 3, and wet etching to form contact holes after exposure;

Step 9: Deposit 1um~2um thick metal aluminum on the contact hole and perform photolithography etching to form the corresponding base and emitter;

Step 10: Thinning the back side of the N-type high-concentration substrate 1, metallizing the back side after thinning and photoetching to form a corresponding collector electrode.

In the traditional power transistor cell structure, the current amplification characteristics of the transistor are related to the minority carrier characteristics of the emitter region, base region and collector region, which are divided into two types of recombination, diffusion and drift formation currents of n-type carriers (electrons) and p-type carriers (holes). Gamma rays in nuclear radiation form ionizing total dose radiation, which causes the interface state at the interface of silicon and silicon dioxide to increase, and the recombination effect is enhanced. Under the same current density, the proportion of diffusion and drift formation currents decreases, and the current amplification decreases. The neutron irradiation effect in nuclear radiation is mainly a displacement effect, which causes lattice defects in silicon crystals and enhances carrier recombination. Reducing the base thickness can reduce the base volume, and the number of lattice defects decreases year-on-year. Under the same conditions, a smaller recombination current component can be maintained, which inhibits the degradation of current amplification performance under neutron irradiation, and ultimately effectively improves the performance degradation of high-voltage power transistor devices in nuclear radiation environments.

As shown in FIG2 , a diffusion region of a deep P-type doped gate region 3 is formed around the thin P-type doped base region 4, so that the device is divided into two parts connected in series in the vertical structure: the upper part is a common bipolar transistor Q1, which is composed of an N-type epitaxial collector, a thin P-type doped base region 4, and an N-type high-concentration emitter region 5; and the lower part is an electrostatic induction transistor Q3, which is composed of a diffusion region of the deep P-type doped gate region 3 as the gate of the electrostatic induction transistor, and an N-type low-concentration epitaxial region between the gates as the transistor channel. In addition, in the horizontal direction, there is also a side bipolar transistor Q2, which uses the diffusion region of the deep P-type doped gate region 3 as the base region of the transistor Q3, the N-type epitaxial substrate as the collector, and the top N-type high-concentration region as the emitter region. When the device is in normal operation, the collector is applied with a forward voltage, the transistor CB junction is reverse biased, and the collector junction space charge region expands downward. After reaching a certain reverse bias, the lateral depletion layer edges of the diffusion region of the deep P-type doped gate region 3 overlap, and the channel of the electrostatic induction transistor is pinched off. As shown in FIG8 , the collector junction electric field under the base region of the ordinary bipolar transistor is shielded, thereby realizing the thin base region feature of the high-voltage transistor and improving the anti-nuclear radiation performance. Moreover, the high-voltage anti-nuclear radiation power transistor structure of the present invention can also be applied to anti-irradiation high-voltage switch tubes.

As shown in FIG8 , the gate spacing _WG of the deep P-type doped gate region 3 must be less than half of the depletion width _WD of the deep P-type doped gate region 3 under high voltage working conditions, that is, 2 _WD > _WG . _WD is related to the high voltage setting conditions and the substrate and epitaxial layer resistivity materials used.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims (3)

1. A high voltage nuclear radiation resistant power transistor structure, comprising: N-type high concentration substrate; An N-type low-concentration epitaxial layer is disposed on the N-type high-concentration substrate; A deep P-type doped gate region, wherein two of the deep P-type doped gate regions are symmetrically arranged on the top outer side of the N-type low-concentration epitaxial layer; A thin P-type doped base region is arranged in the middle of the top of the N-type low-concentration epitaxial layer, and two ends of the thin P-type doped base region overlap with the top of the deep P-type doped gate region respectively; An N-type high-concentration emitter region is arranged in the middle of the top of the thin P-type doped base region; Metal electrodes, including a collector, a base and an emitter, are arranged at the bottom of the N-type high-concentration substrate, the top of the deep P-type doped gate region and the top of the N-type high-concentration emitter region respectively; The doping concentration of the N-type low-concentration epitaxial layer is 1E13cm ^-3 ~2E14cm ^-3 , and the thickness of the N-type low-concentration epitaxial layer is 10um~60um; The P-type impurity implantation concentration of the deep P-type doped gate region is 2E13cm ^-2 ~1E15cm ^-2 ; The P-type impurity implantation concentration of the thin P-type doped base region is 1E14cm ^-2 ~ 5E15cm ^-2 ; The N+ ion implantation concentration of the N-type high-concentration emitter region is 1E15cm ^-2 ~ 1E16cm ^-2 ; The gate spacing _WG of the deep P-type doped gate region needs to be smaller than half of the depletion width _WD of the deep P-type doped gate region under high voltage working conditions, that is, 2 _WD > _WG . 2. A high-voltage nuclear radiation-resistant power transistor structure as described in claim 1, characterized in that the top of the N-type low-concentration epitaxial layer also includes a silicon dioxide isolation dielectric layer to isolate the base and the emitter. 3. A method for preparing a high-voltage nuclear radiation-resistant power transistor structure, for preparing a high-voltage nuclear radiation-resistant power transistor structure as claimed in claim 1 or 2, characterized in that it comprises the following steps: Step 1: Prepare an N-type low-concentration epitaxial layer on an N-type high-concentration substrate; Step 2: Grow a field oxide layer with a thickness of 0.5um~1um on the N-type low-concentration epitaxial layer, and the annealing process temperature is 950℃~1150℃; Step 3: applying photoresist on the surface of the field oxide layer, and wet etching after exposure to form a deep P-type doped gate region; Step 4: growing a buffer oxide layer with a thickness of 0.01um to 0.1um in the deep P-type doped gate region, and the annealing process temperature is 900℃ to 1000℃; Step 5: Use an ion implanter to perform P-type impurity implantation and annealing, and complete the diffusion of the deep P-type doped gate region at high temperature. The annealing process temperature is 1100°C~1200°C; Step 6: Apply photoresist on the surface of the deep P-type doped gate region, and wet-etch to form a thin P-type doped base region after exposure, and then perform base region P-type impurity implantation and annealing, wherein the annealing process temperature is 950°C~1050°C; Step 7: Apply photoresist on the surface of the thin P-type doped base region, wet-etch to form an N-type high-concentration emitter region after exposure, and then perform N+ ion implantation and annealing, with the annealing process temperature being 900°C to 1000°C; Step 8: Apply photoresist on the surface of the N-type high-concentration emitter region and the deep P-type doped gate region, and form contact holes by wet etching after exposure; Step 9: Deposit 1um~2um thick metal aluminum on the contact hole and perform photolithography etching to form the corresponding base and emitter; Step 10: Thinning the back side of the N-type high-concentration substrate, metallizing the back side after thinning and photoetching to form a corresponding collector electrode.