CN109002075A - Base current mirror image circuit, RSSI circuit and the chip of bipolar junction transistor - Google Patents
Base current mirror image circuit, RSSI circuit and the chip of bipolar junction transistor Download PDFInfo
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- CN109002075A CN109002075A CN201710423128.2A CN201710423128A CN109002075A CN 109002075 A CN109002075 A CN 109002075A CN 201710423128 A CN201710423128 A CN 201710423128A CN 109002075 A CN109002075 A CN 109002075A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
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Abstract
The invention discloses a kind of base current mirror image circuit of bipolar junction transistor, RSSI circuit and chips, wherein base current mirror image circuit waits for the base current of mirror image bipolar junction transistor for mirror image, including circuit input end, circuit output end, mirror image bipolar junction transistor, clamp circuit, the first current mirror, the first current source, the second current source and the first load circuit, circuit input end is drawn by the collector to mirror image bipolar junction transistor；Clamp circuit is used to clamp the voltage of the collector of the collector and mirror image bipolar junction transistor to mirror image bipolar junction transistor.The present invention can be by copying the three parts electric current of the input current of trans-impedance amplifier, to replicate obtained electric current as received signal strength indicator information in proportion.RSSI circuit precision with higher provided by the invention is and at the same time can satisfy the application demand of PIN type photodiode and APD type photodiode.
Description
Technical field
The invention belongs to technical field of integrated circuits, in particular to the base current mirror image electricity of a kind of bipolar junction transistor
Road, RSSI (Received Signal Strength Indication, received signal strength indicator) circuit and chip.
Background technique
Three components form a simple optical fiber telecommunications system as shown in figure 1, and three components are respectively as follows: (1) photoelectric conversion
Device, such as laser 10, it can convert electrical signals to optical signal；(2) optical fiber 20, its effect are caused by transmission laser
Light；(3) photodetector photaesthesia to fibre-optic terminus and can convert optical signals to telecommunications such as photodiode 30
Number, common photodiode can be divided into PIN type photodiode and APD type photodiode.Light signal energy passes through optical fiber
Loss can be generated before the photodiode for reaching distal end, in order to which subsequent conditioning circuit facilitates processing signal, photodiode presses one
After light intensity is converted to electric current by fixed ratio, need that this electric current is converted to voltage by a TIA (trans-impedance amplifier).Figure
2 be the circuit diagram of common TIA a kind of, IinIt is the input current of TIA, it is numerically equal to Ib、IRf、IDCRThe sum of three,
Middle IbIt is the electric current for flowing through bipolar junction transistor Q2 base stage, IRfIt is to flow through resistance RfElectric current, IDCRIt is to flow through bipolar junction transistor
The electric current of Q1 collector.In the application of trans-impedance amplifier, it usually needs be monitored, be able to achieve to the signal strength received
The module of this functionality is called RSSI circuit, some TIA chip interiors in addition to include TIA circuit as shown in Figure 2 other than also simultaneously
Integrated RSSI circuit.
Photodiode needs suitable bias voltage that could work.As shown in figure 3, what PIN type photodiode needed
Bias voltage is lower, so its bias voltage needed usually generates inside TIA chip 4, TIA chip 4 is biased including PIN type
Circuit and TIA circuit.But for APD type photodiode, higher bias voltage is needed, it can not be in TIA chip
It realizes inside.As shown in figure 4, the APD type biased electrical that the bias voltage of APD type photodiode is generally external by TIA chip 4 '
Road provides.A kind of common PIN type biasing circuit is utilized in TIA chip interior, photodiode cathode pin and VDD it
Between plus resistance realize, RSSI information can be obtained by the voltage of measurement photodiode cathode at this time；It is another common
PIN type photodiode biasing circuits as shown in figure 5, A point is connected with PIN type photodiode cathode pin in Fig. 5, scheming
In 5 by current mirror by electric current in M0 namely flow through PIN type photodiode current replication come out can also obtain RSSI letter
Breath.Obtaining for RSSI information can be by means of the PIN type biasing circuit of TIA chip interior, but due to APD type under both of these case
Photodiode is biased using external voltage, so chip interior can not for the TIA chip of external APD type photodiode
It realizes such as similar RSSI information acquiring pattern of PIN type photodiode, i.e., can not realize RSSI circuit function in TIA chip interior
Energy.
Summary of the invention
The technical problem to be solved by the present invention is in order to overcome in the prior art TIA chip interior cannot achieve for APD
The defect of the RSSI circuit function of type photodiode, providing one kind can be to the base stage of the bipolar junction transistor in TIA circuit
Electric current test so that can TIA chip interior realize be directed to APD type photodiode received signal strength indicator function
Base current mirror image circuit, RSSI circuit and the chip of the bipolar junction transistor of energy.
The present invention is to solve above-mentioned technical problem by following technical proposals:
A kind of base current mirror image circuit of bipolar junction transistor, it is characterized in that, the ambipolar crystalline substance of mirror image is waited for for mirror image
The base current of body pipe, including circuit input end, circuit output end, mirror image bipolar junction transistor, clamp circuit, the first electric current
Mirror, the first current source, the second current source and the first load circuit, the circuit input end of the base current mirror image circuit by
The collector to mirror image bipolar junction transistor is drawn；
The clamp circuit includes first input end, the second input terminal and output end, and described the first of the clamp circuit
Input terminal is electrically connected with the circuit input end of the base current mirror image circuit, second input of the clamp circuit
End is electrically connected with the collector of the mirror image bipolar junction transistor, the output end of the clamp circuit and first current mirror electricity
Connection；
The clamp circuit is used to clamp the collector and the ambipolar crystalline substance of the mirror image to mirror image bipolar junction transistor
The voltage of the collector of body pipe；
The one of the input terminal of first current mirror, the base stage of the mirror image bipolar junction transistor and first current source
End electrical connection；
The input of the output end of first current mirror, one end of second current source and first load circuit
End electrical connection；
The output end of first load circuit is electrically connected with the circuit output end of the base current mirror image circuit.
In the present solution, mirror image bipolar junction transistor with to mirror image bipolar junction transistor be same type bipolar junction transistor, lead to
Crossing clamp circuit makes the collector voltage of the two equal, and then can be realized the proportional relationship of base current of the two, into one
It walks and mirror image output is carried out to the base current of mirror image bipolar junction transistor, finally copied in circuit output end ambipolar to mirror image
The base current of transistor.
In the present solution, the first load circuit is used to export the electric current of the first current mirror output, which can be used in testing.
In the present solution, by base current mirror image circuit the base current to mirror image bipolar junction transistor can not influenced
In the case where in circuit output end copy the base current to mirror image bipolar junction transistor.This programme is for TIA circuit in Fig. 2
The base current of bipolar junction transistor Q2 can be copied when middle, the electric current of circuit output end output at this time can be used for obtaining RSSI
Information.
Preferably, the clamp circuit includes the amplifier of Differential Input Single-end output, the homophase input of the amplifier
End is the first input end of the clamp circuit, and the inverting input terminal of the amplifier is described the of the clamp circuit
Two input terminals, the output end of the amplifier are the output end of the clamp circuit.
In the present solution, the effect of the amplifier is to clamp mirror image bipolar junction transistor and the collection to mirror image bipolar junction transistor
The voltage of electrode, so that the two voltage value is equal.
Preferably, first current mirror includes the first MOS (Metal-oxide-semicondutor) pipe and the second metal-oxide-semiconductor, institute
State the grid electrical connection of the output end of clamp circuit, the grid of first metal-oxide-semiconductor and second metal-oxide-semiconductor；First MOS
The drain electrode of pipe is electrically connected with the base stage of the mirror image bipolar junction transistor；The drain electrode of second metal-oxide-semiconductor and first load
The input terminal of circuit is electrically connected；
The ratio of the breadth length ratio of first metal-oxide-semiconductor and the breadth length ratio of second metal-oxide-semiconductor is equal to first current source
Electric current and second current source electric current ratio.
In the present solution, the grid of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor is connected, the first current mirror, the width of the first metal-oxide-semiconductor are constituted
The ratio of the breadth length ratio of long ratio and the second metal-oxide-semiconductor is equal to the ratio of the electric current of the first current source and the electric current of the second current source, energy
Enough so that the electric current of the drain electrode output of the second metal-oxide-semiconductor is equal to the drain current of the first metal-oxide-semiconductor.
Preferably, first load circuit includes the second current mirror, the input of second current mirror is connected to described
The input terminal of first load circuit, the output end of second current mirror are exported to the output end of first load circuit, institute
State the ratio between the electric current of the input branch of the second current mirror and the electric current of the output branch of second current mirror is for 1:n, the n
Positive real number.
In the present solution, the first load circuit is realized by the second current mirror, the second current mirror is used to export the first current mirror
Electric current carry out the output of n times of mirror image.
Preferably, first load of collector series connection to mirror image bipolar junction transistor, the mirror image bipolar transistor
The second load of collector series connection of pipe.
In the present solution, the type of the first load and the second load can be selected according to circuit requirements.
Preferably, first load and second load are resistance.
In the present solution, using ohmic load.
The first resistor preferably, emitter to mirror image bipolar junction transistor is connected, the resistance value of the first resistor
For R1, the emitter series connection second resistance of the mirror image bipolar junction transistor, the resistance value of the second resistance is R2, described to mirror
As the area of the emitter of bipolar junction transistor is AQ1, the area of the emitter of the mirror image bipolar junction transistor is AQ2, R2/
R1 is equal to AQ2/AQ1。
In the present solution, if the source electrode to mirror image bipolar junction transistor is equipped with the first resistor for inhibiting noise, then mirror image is double
The source electrode of bipolar transistor also must be provided with matched second resistance, and the resistance value ratio of two resistance will be with the hair of two transistors
The area ratio of emitter-base bandgap grading is adapted, so that two transistor base currents are at expected proportionate relationship.
Also a kind of RSSI circuit of the present invention, is used for trans-impedance amplifier, and the trans-impedance amplifier includes the first bipolar transistor
Pipe, the second bipolar junction transistor and 3rd resistor, the input current of the trans-impedance amplifier split into the described first ambipolar crystalline substance
The base current of the collector current of body pipe, the electric current of the 3rd resistor and second bipolar junction transistor, feature
It is,
The RSSI circuit includes resistor current mirror image circuit, collector current mirror image circuit and bipolar transistor above-mentioned
The base current mirror image circuit of pipe；
Second bipolar junction transistor is described to mirror image bipolar junction transistor；
Electric current of the resistor current mirror image circuit for 3rd resistor described in mirror image；
Electric current of the collector current mirror image circuit for the collector of the first bipolar junction transistor described in mirror image.
In the present solution, passing through resistor current mirror image circuit, current collection in the case where not influencing trans-impedance amplifier normal work
Electrode current mirror image circuit and the base current mirror image circuit difference mirror image output electric current of 3rd resistor, the first bipolar junction transistor
The base current of collector current and the second bipolar junction transistor, then RSSI information is obtained by three output electric currents.
Preferably, the collector current mirror image circuit includes third bipolar junction transistor and third current mirror, described
The grid of three bipolar junction transistors is electrically connected with the grid of first bipolar junction transistor, and the third current mirror is used for mirror image
The collector current of the third bipolar junction transistor.
In the present solution, by the way that the grid of third bipolar junction transistor to be electrically connected with the grid of the first bipolar junction transistor,
The collector current of the first bipolar junction transistor can be copied in the collector of third bipolar junction transistor, further by the
The output of three current mirrors.
Preferably, the resistor current mirror image circuit waits for the electric current of mirror image resistance, the resistor current mirror image for mirror image
Circuit includes the band source of mirror image circuit first input end, the second input terminal of mirror image circuit, mirror image circuit output end and differential configuration
The common-source circuits of pole negative-feedback；
The mirror image circuit first input end and second input terminal of mirror image circuit are respectively by described to mirror image resistance
It draws at both ends；
The common-source circuits include mirror image resistance, common-source circuits first input end, the second input terminal of common-source circuits,
The first output end of common-source circuits, common-source circuits second output terminal；The common-source circuits first input end and the mirror image
The electrical connection of circuit first input end, second input terminal of common-source circuits are electrically connected with second input terminal of mirror image circuit；
First output end of common-source circuits and the current difference of the common-source circuits second output terminal, which are equal to, flows through the mirror image electricity
Electric current in resistance；
The resistor current mirror image circuit further includes the 4th current mirror, the 5th current mirror, the 6th current mirror and the second load
Circuit, second load circuit includes load input terminal and load outputs；
The input terminal of 4th current mirror is electrically connected with first output end of common-source circuits, the 4th current mirror
Output end be electrically connected with the load input terminal；
The input terminal of 5th current mirror is electrically connected with the common-source circuits second output terminal, the 5th current mirror
Output end be electrically connected with the input terminal of the 6th current mirror；
The output end of 6th current mirror is electrically connected with the load input terminal；
The electric current ratio of the output branch of the electric current and the 5th current mirror of the input branch of 5th current mirror is 1:
The electric current ratio of m, the output branch of the electric current and the 6th current mirror of the input branch of the 6th current mirror are 1:k, described
The electric current ratio of the output branch of the electric current and the 4th current mirror of the input branch of 4th current mirror is 1:(m*k)；
The load outputs are electrically connected with the mirror image circuit output end, and the electric current of the load outputs is born with described
The ratio for carrying the electric current of input terminal is 1:n；M, k, n are positive real number.
In the present solution, ideally the voltage difference of the two ends of mirror image resistance is equal to the voltage difference of the two ends to mirror image resistance, lead to
Cross common-source circuits can will be on mirror image ohmically current replication to mirror image resistance, specially common-source circuits first export
The current difference of end and common-source circuits second output terminal, which is equal to, flows through the ohmically electric current of mirror image.On this basis, using three
The output of the positive real number multiple of the ohmically electric current of mirror image is realized in current mirror combination, and can be surveyed by load circuit output end
?.Resistance R can be copied when this programme is in TIA circuit in Fig. 2fOn electric current IRf, mirror image circuit output end is defeated at this time
Use when electric current out can be used for obtaining RSSI information.
Preferably, the common-source circuits further include third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, third current source and the 4th electric current
Source；The third current source is equal with the electric current that the 4th current source provides；
The grid of the third metal-oxide-semiconductor is electrically connected with the mirror image circuit first input end, the grid of the 4th metal-oxide-semiconductor
It is electrically connected with second input terminal of mirror image circuit；
One end of the source electrode of the third metal-oxide-semiconductor, one end of the third current source and the mirror image resistance is electrically connected, institute
State the other end electrical connection of the source electrode of the 4th metal-oxide-semiconductor, one end of the 4th current source and the mirror image resistance；
The drain electrode of the third metal-oxide-semiconductor is electrically connected with first output end of common-source circuits；The leakage of 4th metal-oxide-semiconductor
Pole is electrically connected with the common-source circuits second output terminal.
In the present solution, third current source is equal with the electric current that the 4th current source provides, the grid voltage of third metal-oxide-semiconductor and
The difference of the grid voltage of four metal-oxide-semiconductors is the ohmically voltage value of mirror image, that is, to the voltage difference at mirror image resistance both ends,
It is the ohmically electric current of mirror image to realize the difference of the electric current of third metal-oxide-semiconductor drain electrode and the electric current of the 4th metal-oxide-semiconductor drain electrode,
The electric current that third metal-oxide-semiconductor drains is exported with m*k times of mirror image to load input terminal by the 4th current mirror, while passing through the 5th electricity
Stream mirror is exported again by the 6th current mirror with k times after first exporting the electric current that the 4th metal-oxide-semiconductor drains to the 6th current mirror with m times of mirror image
To load input terminal, what load input terminal obtained at this time is m*k times of the ohmically electric current of mirror image.
Preferably, second load circuit include the 5th current source and the 7th current mirror, the 7th current mirror it is defeated
Enter end be electrically connected with one end of the load input terminal and the 5th current source, the output end of the 7th current mirror with it is described
Load outputs electrical connection, the electricity of the output branch of the electric current and the 7th current mirror of the input branch of the 7th current mirror
Stream is than being 1:n.
In the present solution, the second load circuit is realized by the 5th current source and the 7th current mirror, the output of the 7th current mirror
The use when electric current of end output can be used for obtaining RSSI information.
Preferably, the resistor current mirror image circuit further includes source follower, the source follower is serially connected with described
To between mirror image resistance and the common-source circuits；
The source follower includes follower first input end, the second input terminal of follower, the first output end of follower
And follower second output terminal；
The follower first input end is electrically connected with the mirror image circuit first input end, and the follower second inputs
End is electrically connected with second input terminal of mirror image circuit；
First output end of follower is electrically connected with the common-source circuits first input end, and the follower second is defeated
Outlet is electrically connected with second input terminal of common-source circuits；
The source follower is used to adjust the electricity of the follower first input end Yu second input terminal of follower
It presses to adapt to the voltage of the common-source circuits.
In the present solution, mirror image circuit first input end and the input of mirror image circuit second can be adjusted by source follower
The voltage of two o'clock is held to adapt to the requirement of subsequent conditioning circuit.
Preferably, the source follower includes the first branch and second branch；
The first branch includes the 6th current source and the 5th metal-oxide-semiconductor being serially connected between power supply and ground, the 5th MOS
The source electrode of pipe is electrically connected with the 6th current source, and grid and the follower first input end of the 5th metal-oxide-semiconductor are electrically connected
It connects；
The second branch includes the 7th current source and the 6th metal-oxide-semiconductor being serially connected between power supply and ground, the 6th MOS
The source electrode of pipe is electrically connected with the 7th current source, and the grid of the 6th metal-oxide-semiconductor is electrically connected with second input terminal of follower
It connects；
6th current source is equal with the electric current that the 7th current source provides.
In the present solution, source follower is realized by two metal-oxide-semiconductors and the identical current source of two current values, follower the
One input terminal and the second input terminal of follower are respectively connected to the grid of two metal-oxide-semiconductors, by the current value for controlling two current sources
Or the breadth length ratio of two metal-oxide-semiconductors realizes the control to the first output end of follower and follower second output terminal output voltage
System.
The present invention also provides a kind of chips, including trans-impedance amplifier, it is characterized in that, the chip further includes above-mentioned
RSSI circuit.
In the present solution, integrated chip trans-impedance amplifier and RSSI circuit, which can be to trans-impedance amplifier
Input current carries out mirror image output, using the electric current that the mirror image exports as received signal strength indicator information.What this programme provided
The RSSI circuit precision with higher of chip interior is and at the same time can satisfy PIN type photodiode and APD type photoelectricity two
The application demand of pole pipe.
The positive effect of the present invention is that: the base current mirror image circuit of bipolar junction transistor provided by the invention,
RSSI circuit and chip can be by copying the three parts electric current of the input current of trans-impedance amplifier in proportion, i.e., first is bipolar
The base current of the collector current of transistor npn npn, the electric current of 3rd resistor and the second bipolar junction transistor is obtained with duplication
Electric current as received signal strength indicator information.RSSI circuit precision with higher provided by the invention is and at the same time can
Meet the application demand of PIN type photodiode and APD type photodiode.
Detailed description of the invention
Fig. 1 is a kind of simple optical fiber telecommunications system schematic diagram in the prior art.
Fig. 2 is a kind of circuit diagram of common TIA in the prior art.
Fig. 3 is PIN type photodiode in the prior art and TIA chip operation schematic diagram.
Fig. 4 is APD type photodiode in the prior art and TIA chip operation schematic diagram.
Fig. 5 is a kind of common PIN type photodiode biasing circuits figure in the prior art.
Fig. 6 is the base current mirror image circuit figure of bipolar junction transistor in the embodiment of the present invention 1.
Fig. 7 is RSSI circuit module schematic diagram in the embodiment of the present invention 2.
Fig. 8 is the circuit diagram that collector current mirror image circuit 303 implements in Fig. 7.
Fig. 9 is the module diagram that resistor current mirror image circuit 302 implements in Fig. 7.
Figure 10 is the circuit diagram that source follower 3026 implements in Fig. 9.
Figure 11 is the circuit diagram that common-source circuits 3024 implement in Fig. 9.
Figure 12 is the circuit diagram of the second load circuit 3025 specific implementation in Fig. 9.
Figure 13 is that resistor current mirror image circuit 302 implements circuit diagram in Fig. 7.
Figure 14 is the base current mirror image circuit figure of bipolar junction transistor in the embodiment of the present invention 4.
Figure 15 is the circuit diagram that source follower 3026 implements in the embodiment of the present invention 5.
Figure 16 is the circuit diagram of the second load circuit 3025 specific implementation in the embodiment of the present invention 6.
Figure 17 is the base current mirror image circuit figure of bipolar junction transistor in the embodiment of the present invention 7.
Specific embodiment
The present invention is further illustrated below by the mode of embodiment, but does not therefore limit the present invention to the reality
It applies among a range.
Embodiment 1
As shown in fig. 6, including the base current mirror of a single-stage common emitter amplifier circuit 2 and a bipolar junction transistor
As circuit 1, the base current I of mirror image bipolar junction transistor Q4 is waited for for mirror imageb1.The wherein base current mirror of bipolar junction transistor
As circuit 1 includes circuit input end 101, circuit output end 102, mirror image bipolar junction transistor Q5, the 103, first electricity of clamp circuit
Flow mirror 104, the first current source Ic1, the second current source Ic2With the first load circuit 105.The circuit of base current mirror image circuit 1 is defeated
Enter end 101 by the collector extraction to mirror image bipolar junction transistor Q4, the output output of circuit output end 102 electric current IOUT1.Wherein,
It is bipolar npn transistor npn npn to mirror image bipolar junction transistor Q4 and mirror image bipolar junction transistor Q5.
Clamp circuit 103 includes first input end 1031, the second input terminal 1032 and output end 1033, clamp circuit 103
First input end 1031 be electrically connected with the circuit input end 101 of base current mirror image circuit 1, the second of clamp circuit 103 is defeated
Enter end 1032 to be electrically connected with the collector of mirror image bipolar junction transistor Q5, the output end of clamp circuit 103 and the first current mirror 104
Electrical connection.Clamp circuit 103 is used to clamp the collector and mirror image bipolar junction transistor Q5 to mirror image bipolar junction transistor Q4
The voltage of collector.
The input terminal 1041 of first current mirror 104, the base stage of mirror image bipolar junction transistor Q5 and the first current source Ic1One
End electrical connection；The output end 1042 of first current mirror 104, the second current source Ic2One end and the first load circuit 105 it is defeated
Enter 1051 electrical connection of end；First current source Ic1The other end and the second current source Ic2The other end be grounded.
The output end 1052 of first load circuit 105 is electrically connected with the circuit output end 102 of base current mirror image circuit 1.
In the present embodiment, clamp circuit 103 includes the amplifier AMP1 of Differential Input Single-end output, and amplifier AMP1's is same
Phase input terminal is the first input end 1031 of clamp circuit 103, and the inverting input terminal of amplifier AMP1 is the of clamp circuit 103
Two input terminals 1032, the output end of amplifier AMP1 are the output end 1033 of clamp circuit 103.
In the present embodiment, the first current mirror 104 includes the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2, the first metal-oxide-semiconductor M1 and the
Two metal-oxide-semiconductor M2 are PMOS tube.The output end 1033 of clamp circuit 103, the grid of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2
Grid electrical connection；The drain electrode of first metal-oxide-semiconductor M1 is electrically connected with the base stage of mirror image bipolar junction transistor Q5；The leakage of second metal-oxide-semiconductor M2
Pole is electrically connected with the input terminal 1051 of the first load circuit 105.The width of the breadth length ratio of first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 are long
The ratio of ratio is equal to the first current source Ic1Electric current and the second current source Ic2Electric current ratio.
In the present embodiment, the first load circuit 105 includes that the input terminal of the second current mirror CM2, the second current mirror CM2 accesses
The input terminal 1051 of first load circuit 105, the output end of the second current mirror CM2 are exported to the output of the first load circuit 105
The ratio between the electric current at end 1052, the output branch of the electric current and the second current mirror CM2 of the input branch of the second current mirror CM2 is 1:n,
Wherein n is positive real number.
In the present embodiment, to the first load of collector series connection of mirror image bipolar junction transistor Q4, resistance value Ra, mirror image is bipolar
The second load of collector series connection of transistor npn npn Q5, resistance value Rb.
In the present embodiment, to the emitter series connection first resistor of mirror image bipolar junction transistor Q4, the resistance value of first resistor is
The emitter series connection second resistance of R1, mirror image bipolar junction transistor Q5, the resistance value of second resistance is R2, to mirror image bipolar transistor
The area of the emitter of pipe Q4 is AQ3, the area of the emitter of mirror image bipolar junction transistor Q5 is AQ4, R2/R1 is equal to AQ4/AQ3。
In the present embodiment, if not having first resistor in single-stage common emitter amplifier circuit, second resistance can also be saved；The
One load and the second load are ohmic load, can also be other types of loads.Pass through the base stage electricity of bipolar junction transistor
Traffic mirroring circuit 1, which can copy the base current to mirror image bipolar junction transistor Q4, to be come.
In the present embodiment, electric current I is exportedOUT1Expression formula is [(n*Ib1*Ic2*Ra)/(Ic1*Rb)]。
Embodiment 2
As shown in fig. 7, the present embodiment additionally provides a kind of RSSI circuit 3, it, should for trans-impedance amplifier as shown in Figure 2
Trans-impedance amplifier includes the first bipolar junction transistor Q1, the second bipolar junction transistor Q2 and 3rd resistor Rf, trans-impedance amplifier
Input current IinSplit into the collector current I of the first bipolar junction transistor Q1DCR, 3rd resistor RfElectric current IRfAnd second
The base current I of bipolar junction transistor Q2b。
Wherein, RSSI circuit 3 includes resistor current mirror image circuit 302, collector current mirror image circuit 303 and base current
Mirror image circuit 301, wherein base current mirror image circuit 301 uses the base current of the bipolar junction transistor in embodiment 1
Mirror image circuit 1 is realized.Second bipolar junction transistor Q2 is equivalent in Fig. 6 to mirror image bipolar junction transistor Q4.Resistor current mirror image
Circuit 302 is used for mirror image 3rd resistor RfElectric current IRfTo export the second output electric current I in Fig. 7OUT2；Collector current mirror image
Electric current I of the circuit 303 for the collector of the first bipolar junction transistor of mirror image Q1DCRElectric current is exported to export third in Fig. 7
IOUT3, base current mirror image circuit 301 is by the base current I of the second bipolar junction transistor Q2 in Fig. 7bMirror image output is defeated for first
Electric current I outOUT1；Three obtained output electric current is for generating RSSI information.
In the present embodiment, as shown in figure 8, collector current mirror image circuit 301 includes third bipolar junction transistor Q3 and the
Three current mirror CM3, the grid of third bipolar junction transistor Q3 are electrically connected with the grid of the first bipolar junction transistor Q1 in Fig. 2, the
Collector current output third of the three current mirror CM3 for mirror image third bipolar junction transistor Q3 exports electric current IOUT3。
In the present embodiment, resistor current mirror image circuit 302 implements module frame chart as shown in figure 9, waiting for mirror for mirror image
As resistance (3rd resistor R in Fig. 2f) electric current, resistor current mirror image circuit 302 include mirror image circuit first input end 3021,
The second input terminal of mirror image circuit 3022, mirror image circuit output end 3023, source follower 3026, the band source electrode of differential configuration are negative anti-
Common-source circuits 3024, the 4th current mirror CM4, the 5th current mirror CM5, the 6th current mirror CM6 and the second load circuit of feedback
3025.Mirror image circuit first input end 3021 and the second input terminal of mirror image circuit 3022 are respectively by 3rd resistor RfBoth ends draw
Out.
Source follower 3026 is defeated including follower first input end A1, the second input terminal of follower A2, follower first
Outlet A3 and follower second output terminal A4.Source follower 3026 is for adjusting follower first input end A1 and follower
The voltage of second input terminal A2 is to adapt to the voltage requirements of common-source circuits 3024.Common-source circuits 3024 include common-source circuits
First input end B1, the second input terminal of common-source circuits B2, the first output end of common-source circuits B3, common-source circuits second export
Hold B4.Second load circuit 3025 includes load input terminal F1 and load outputs F2.Follower first input end A1 and mirror image
Circuit first input end 3021 is electrically connected, and follower the second input terminal A2 is electrically connected with the second input terminal of mirror image circuit 3022, with
It is electrically connected with the first output terminals A of device 3 with common-source circuits first input end B1, follower second output terminal A4 and common-source circuits
Second input terminal B2 electrical connection, common-source circuits the first output end B3 are electrically connected with the input terminal C1 of the 4th current mirror CM4, common source
Polar circuit second output terminal B4 is electrically connected with the input terminal D1 of the 5th current mirror CM5, the output end D2 of the 5th current mirror CM5 and
The input terminal E1 of six current mirror CM6 is electrically connected, the output end C2 of the 4th current mirror CM4, the 6th current mirror CM6 output end E2 with
Load input terminal F1 electrical connection, load outputs F2 are electrically connected with mirror image circuit output end 3023.
As shown in Figure 10, source follower 3026 further includes the first branch and second branch；The first branch includes being serially connected with
The 6th current source I between power supply and groundc6With the 5th metal-oxide-semiconductor M5, the source electrode and the 6th current source I of the 5th metal-oxide-semiconductor M5c6One
End, which is electrically connected, simultaneously to be exported to the first output terminals A of follower 3, and the grid of the 5th metal-oxide-semiconductor M5 is by resistance and capacitor and follower the
One input terminal A1 electrical connection；Second branch includes the 7th current source I being serially connected between power supply and groundc7With the 6th metal-oxide-semiconductor M6,
The source electrode and the 7th current source I of six metal-oxide-semiconductor M6c7One end be electrically connected and export to follower second output terminal A4, the 6th metal-oxide-semiconductor
The grid of M6 is electrically connected by resistance and capacitor with the second input terminal of follower A2.5th metal-oxide-semiconductor M5 and the 6th in the present embodiment
Metal-oxide-semiconductor M6 is PMOS (p-type Metal-oxide-semicondutor) pipe.
As shown in figure 11, common-source circuits 3024 further include mirror image resistance Rd, third metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4,
Three current source Ic3With the 4th current source Ic4.Third metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 is NMOS (N-type metal-oxide-half
Conductor) pipe.Mirror image resistance RdFor with 3rd resistor RfThe identical resistance of type, 3rd resistor RfWith mirror image resistance RdResistance value it
Than for p.Mirror image resistance RdVoltage difference of the two ends be approximately equal to 3rd resistor RfVoltage difference of the two ends.Common-source circuits 3,024 first
The current difference of output end B3 and common-source circuits second output terminal B4, which are equal to, flows through mirror image resistance RdOn electric current.Third current source
Ic3With the 4th current source Ic4The electric current of offer is equal.
The grid of third metal-oxide-semiconductor M3 is electrically connected with common-source circuits first input end B1, and the grid of the 4th metal-oxide-semiconductor M4 is together
Source circuit the second input terminal B2 electrical connection；Source electrode, the third current source I of third metal-oxide-semiconductor M3c3One end and mirror image resistance Rd's
One end electrical connection, source electrode, the 4th current source I of the 4th metal-oxide-semiconductor M4c4One end and mirror image resistance RdThe other end electrical connection；The
The drain electrode of three metal-oxide-semiconductor M3 is electrically connected with the first output end of common-source circuits B3；The drain electrode of 4th metal-oxide-semiconductor M4 and common-source circuits the
Two output end B4 electrical connection.Third current source Ic3The other end and the 4th current source Ic4The other end be grounded.
As shown in figure 12, the second load circuit 3025 includes the 5th current source Ic5With the 7th current mirror CM7, the 7th current mirror
The input terminal and load input terminal F1 and the 5th current source I of CM7c5One end electrical connection, the output end of the 7th current mirror CM7 and negative
Carry output end F2 electrical connection, the 5th current source Ic5The other end ground connection, the 7th current mirror CM7 input branch electric current and the 7th
The electric current ratio of the output branch of current mirror CM7 is 1:n.
Figure 13 is that resistor current mirror image circuit 302 implements circuit diagram, wherein the 4th current mirror CM4 is in order to indicate convenient
It is divided into two parts CM4, a and CM4, b, wherein CM4, a are the input branch of the 4th current mirror CM4, and CM4, b are the 4th current mirror
The output branch of CM4.The electric current ratio of the output branch of the electric current and the 5th current mirror CM5 of the input branch of 5th current mirror CM5
Electric current ratio for 1:m, the output branch of the electric current and the 6th current mirror CM6 of the input branch of the 6th current mirror CM6 is 1:k, the
The electric current ratio of the output branch of the electric current and the 4th current mirror CM4 of the input branch of four current mirror CM4 is 1:(m*k)；7th electricity
The electric current ratio for flowing the electric current of the input branch of mirror CM7 and the output branch of the 7th current mirror CM7 is 1:n, and m, k, n are positive reality
Number.Second output electric current IOUT2Expression formula is [n*IC5+(2*m*n*k*IRf/p)]。
Embodiment 3
A kind of chip, including the RSSI circuit in trans-impedance amplifier shown in Fig. 2 and embodiment 2.
Embodiment 4
The present embodiment provides a kind of base current mirror image circuits of bipolar junction transistor, and as shown in figure 14, a single-stage is total
The base current mirror image circuit 1 of emitter amplifier circuit 2 and a bipolar junction transistor, the present embodiment are different from embodiment 1
It is to mirror image bipolar junction transistor Q4 and mirror image bipolar junction transistor Q5 is positive-negative-positive bipolar junction transistor, the first current source Ic1
The other end and the second current source Ic2The other end connect power supply, the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 are NMOS tube.
Embodiment 5
The present embodiment provides a kind of RSSI circuit, the realization circuit of source follower 3026 is such as different from Example 2
Shown in Figure 15, wherein the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 is NMOS tube.
Embodiment 6
The present embodiment provides a kind of RSSI circuit, the realization circuit of the second load circuit 3025 as different from Example 2
As shown in figure 16, wherein the 5th current source Ic5Another termination power.
Embodiment 7
The present embodiment provides a kind of RSSI circuits, as shown in figure 17, as different from Example 2: third metal-oxide-semiconductor M3 and
Four metal-oxide-semiconductor M4 are PMOS tube, third current source Ic3The other end and the 4th current source Ic4The other end connect power supply；The
Five metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 are NMOS tube；5th current source Ic5Another termination power.
The present invention is by by the electric current I of trans-impedance amplifier in Fig. 2b、IRf、IDCRIt copies and in proportion, then will copy and
Electric current addition just obtained and input current IinThe numerically electric current of proportional relationship, using this electric current as received signal strength
Indicate information, this RSSI circuit precision with higher is and at the same time can satisfy PIN type photodiode and APD type photoelectricity
The application of diode.
Although specific embodiments of the present invention have been described above, it will be appreciated by those of skill in the art that this is only
For example, protection scope of the present invention is to be defined by the appended claims.Those skilled in the art without departing substantially from
Under the premise of the principle and substance of the present invention, many changes and modifications may be made, but these change and
Modification each falls within protection scope of the present invention.
Claims (15)
1. a kind of base current mirror image circuit of bipolar junction transistor, which is characterized in that wait for mirror image bipolar transistor for mirror image
The base current of pipe, including circuit input end, circuit output end, mirror image bipolar junction transistor, clamp circuit, the first current mirror,
First current source, the second current source and the first load circuit, the circuit input end of the base current mirror image circuit is by institute
State the collector extraction to mirror image bipolar junction transistor；
The clamp circuit includes first input end, the second input terminal and output end, first input of the clamp circuit
End be electrically connected with the circuit input end of the base current mirror image circuit, second input terminal of the clamp circuit and
The collector of the mirror image bipolar junction transistor is electrically connected, and the output end of the clamp circuit is electrically connected with first current mirror
It connects；
The clamp circuit is used to clamp the collector and the mirror image bipolar junction transistor to mirror image bipolar junction transistor
Collector voltage；
One end electricity of the input terminal of first current mirror, the base stage of the mirror image bipolar junction transistor and first current source
Connection；
The input terminal electricity of the output end of first current mirror, one end of second current source and first load circuit
Connection；
The output end of first load circuit is electrically connected with the circuit output end of the base current mirror image circuit.
2. the base current mirror image circuit of bipolar junction transistor as described in claim 1, which is characterized in that the clamp circuit
Amplifier including Differential Input Single-end output, the non-inverting input terminal of the amplifier are the described first defeated of the clamp circuit
Enter end, the inverting input terminal of the amplifier is second input terminal of the clamp circuit, the output end of the amplifier
For the output end of the clamp circuit.
3. the base current mirror image circuit of bipolar junction transistor as described in claim 1, which is characterized in that first electric current
Mirror includes the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, the output end of the clamp circuit, the grid of first metal-oxide-semiconductor and described second
The grid of metal-oxide-semiconductor is electrically connected；The drain electrode of first metal-oxide-semiconductor is electrically connected with the base stage of the mirror image bipolar junction transistor；It is described
The drain electrode of second metal-oxide-semiconductor is electrically connected with the input terminal of first load circuit；
The ratio of the breadth length ratio of first metal-oxide-semiconductor and the breadth length ratio of second metal-oxide-semiconductor is equal to the electricity of first current source
The ratio of stream and the electric current of second current source.
4. the base current mirror image circuit of bipolar junction transistor as described in claim 1, which is characterized in that first load
Circuit includes the second current mirror, and the input of second current mirror is connected to the input terminal of first load circuit, and described the
The output end of two current mirrors is exported to the output end of first load circuit, the electric current of the input branch of second current mirror
The ratio between electric current with the output branch of second current mirror is 1:n, and the n is positive real number.
5. the base current mirror image circuit of bipolar junction transistor as described in claim 1, which is characterized in that described double to mirror image
The first load of collector series connection of bipolar transistor, the second load of collector series connection of the mirror image bipolar junction transistor.
6. the base current mirror image circuit of bipolar junction transistor as claimed in claim 5, which is characterized in that first load
It is resistance with second load.
7. the base current mirror image circuit of bipolar junction transistor as described in claim 1, which is characterized in that described double to mirror image
The emitter series connection first resistor of bipolar transistor, the resistance value of the first resistor is R1, the mirror image bipolar junction transistor
Emitter series connection second resistance, the resistance value of the second resistance are R2, the face of the emitter to mirror image bipolar junction transistor
Product is AQ1, the area of the emitter of the mirror image bipolar junction transistor is AQ2, R2/R1 is equal to AQ2/AQ1。
8. a kind of RSSI circuit, it to be used for trans-impedance amplifier, the trans-impedance amplifier includes the first bipolar junction transistor, second bipolar
Transistor npn npn and 3rd resistor, the input current of the trans-impedance amplifier split into the collector of first bipolar junction transistor
The base current of electric current, the electric current of the 3rd resistor and second bipolar junction transistor, which is characterized in that
The RSSI circuit includes resistor current mirror image circuit, collector current mirror image circuit and any one of such as claim 1 to 7
The base current mirror image circuit of the bipolar junction transistor；
Second bipolar junction transistor is described to mirror image bipolar junction transistor；
Electric current of the resistor current mirror image circuit for 3rd resistor described in mirror image；
Electric current of the collector current mirror image circuit for the collector of the first bipolar junction transistor described in mirror image.
9. RSSI circuit as claimed in claim 8, which is characterized in that the collector current mirror image circuit includes that third is bipolar
The grid electricity of transistor npn npn and third current mirror, the grid of the third bipolar junction transistor and first bipolar junction transistor
Connection, collector current of the third current mirror for third bipolar junction transistor described in mirror image.
10. RSSI circuit as claimed in claim 8, which is characterized in that the resistor current mirror image circuit waits for mirror for mirror image
As the electric current of resistance, the resistor current mirror image circuit includes mirror image circuit first input end, the second input terminal of mirror image circuit, mirror
As the common-source circuits with source negative feedback of circuit output end and differential configuration；
The mirror image circuit first input end and second input terminal of mirror image circuit are respectively by the both ends to mirror image resistance
It draws；
The common-source circuits include mirror image resistance, common-source circuits first input end, the second input terminal of common-source circuits, common source
The first output end of polar circuit, common-source circuits second output terminal；The common-source circuits first input end and the mirror image circuit
First input end electrical connection, second input terminal of common-source circuits are electrically connected with second input terminal of mirror image circuit；It is described
The first output end of common-source circuits and the current difference of the common-source circuits second output terminal, which are equal to, to be flowed through on the mirror image resistance
Electric current；
The resistor current mirror image circuit further includes the 4th current mirror, the 5th current mirror, the 6th current mirror and the second load electricity
Road, second load circuit includes load input terminal and load outputs；
The input terminal of 4th current mirror is electrically connected with first output end of common-source circuits, the 4th current mirror it is defeated
Outlet is electrically connected with the load input terminal；
The input terminal of 5th current mirror is electrically connected with the common-source circuits second output terminal, the 5th current mirror it is defeated
Outlet is electrically connected with the input terminal of the 6th current mirror；
The output end of 6th current mirror is electrically connected with the load input terminal；
The electric current ratio of the output branch of the electric current and the 5th current mirror of the input branch of 5th current mirror is 1:m, institute
State the 6th current mirror input branch electric current and the 6th current mirror output branch electric current ratio be 1:k, the described 4th
The electric current ratio of the output branch of the electric current and the 4th current mirror of the input branch of current mirror is 1:(m*k)；
The load outputs are electrically connected with the mirror image circuit output end, and the electric current of the load outputs and the load are defeated
The ratio for entering the electric current at end is 1:n；M, k, n are positive real number.
11. RSSI circuit as claimed in claim 10, which is characterized in that the common-source circuits further include third metal-oxide-semiconductor,
Four metal-oxide-semiconductors, third current source and the 4th current source；The third current source is equal with the electric current that the 4th current source provides；
The grid of the third metal-oxide-semiconductor is electrically connected with the mirror image circuit first input end, the grid of the 4th metal-oxide-semiconductor and institute
State the electrical connection of the second input terminal of mirror image circuit；
One end of the source electrode of the third metal-oxide-semiconductor, one end of the third current source and the mirror image resistance is electrically connected, and described the
The other end of the source electrode of four metal-oxide-semiconductors, one end of the 4th current source and the mirror image resistance is electrically connected；
The drain electrode of the third metal-oxide-semiconductor is electrically connected with first output end of common-source circuits；The drain electrode of 4th metal-oxide-semiconductor with
The common-source circuits second output terminal electrical connection.
12. RSSI circuit as claimed in claim 10, which is characterized in that second load circuit include the 5th current source and
One end of 7th current mirror, the input terminal and the load input terminal and the 5th current source of the 7th current mirror is electrically connected
It connects, the output end of the 7th current mirror is electrically connected with the load outputs, the electricity of the input branch of the 7th current mirror
The electric current ratio of stream and the output branch of the 7th current mirror is 1:n.
13. RSSI circuit as claimed in claim 10, which is characterized in that the resistor current mirror image circuit further include source electrode with
With device, the source follower is serially connected with described between mirror image resistance and the common-source circuits；
The source follower include follower first input end, the second input terminal of follower, the first output end of follower and
Follower second output terminal；
The follower first input end is electrically connected with the mirror image circuit first input end, second input terminal of follower with
The second input terminal of mirror image circuit electrical connection；
First output end of follower is electrically connected with the common-source circuits first input end, the follower second output terminal
It is electrically connected with second input terminal of common-source circuits；
The source follower be used to adjust the voltage of the follower first input end and second input terminal of follower with
Adapt to the voltage of the common-source circuits.
14. RSSI circuit as claimed in claim 13, which is characterized in that the source follower includes the first branch and second
Branch；
The first branch includes the 6th current source and the 5th metal-oxide-semiconductor being serially connected between power supply and ground, the 5th metal-oxide-semiconductor
Source electrode is electrically connected with the 6th current source, and the grid of the 5th metal-oxide-semiconductor is electrically connected with the follower first input end；
The second branch includes the 7th current source and the 6th metal-oxide-semiconductor being serially connected between power supply and ground, the 6th metal-oxide-semiconductor
Source electrode is electrically connected with the 7th current source, and the grid of the 6th metal-oxide-semiconductor is electrically connected with second input terminal of follower；
6th current source is equal with the electric current that the 7th current source provides.
15. a kind of chip, including trans-impedance amplifier, which is characterized in that the chip further includes such as any one of claim 8 to 14
The RSSI circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110701245.7A CN113448376A (en) | 2017-06-07 | 2017-06-07 | Base current mirror circuit, RSSI circuit and chip of bipolar transistor |
| CN201710423128.2A CN109002075B (en) | 2017-06-07 | 2017-06-07 | Base current mirror circuit, RSSI circuit and chip of bipolar transistor |
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| CN201710423128.2A CN109002075B (en) | 2017-06-07 | 2017-06-07 | Base current mirror circuit, RSSI circuit and chip of bipolar transistor |
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| CN202110701245.7A Division CN113448376A (en) | 2017-06-07 | 2017-06-07 | Base current mirror circuit, RSSI circuit and chip of bipolar transistor |
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| CN201710423128.2A Active CN109002075B (en) | 2017-06-07 | 2017-06-07 | Base current mirror circuit, RSSI circuit and chip of bipolar transistor |
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| CN109002076A (en) * | 2017-06-07 | 2018-12-14 | 上海韦玏微电子有限公司 | Resistor current mirror image circuit, RSSI circuit and chip |
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| CN114690842A (en) * | 2020-12-29 | 2022-07-01 | 圣邦微电子（北京）股份有限公司 | Current source circuit for biasing bipolar transistor |
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| CN109002075B (en) | 2021-07-23 |
| CN113448376A (en) | 2021-09-28 |
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