CN108899364B - A kind of MOS gated thyristor integrated with Schottky diode and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of power semiconductor devices, and relates to an MOS (metal oxide semiconductor) grid-controlled thyristor integrated with a Schottky diode. The invention forms a Schottky diode between a P well region and a cathode by designing the cathode of the device as a Schottky contact, wherein P is⁺The region can accelerate the extraction of carriers during turn-off, but does not influence the pulse performance of the device, and whether P is reserved or not can be selected according to requirements during manufacturing⁺And (4) a zone. The two structures can ensure that the current distribution is more uniform when the device works, the minimum current required by the latch of the device is reduced, the pulse peak current of the device is further improved under the low current, the current rise rate (di/dt) is improved, the time of the device working under the IGBT mode is shortened, the lattice temperature of the device working under the IGBT mode at the pulse discharge initial stage is effectively reduced, and the pulse characteristic of the device is further improved.

Description

A kind of MOS gated thyristor integrated with Schottky diode and preparation method thereof

technical field

The invention belongs to the technical field of power semiconductor devices, and relates to a MOS gate-controlled thyristor (SD-MCT) integrated with a Schottky diode and a preparation method thereof.

Background technique

Pulse power technology is an emerging science and technology developed in the early 1960s due to the needs of national defense scientific research. Simply put, pulse power technology is an electro-physical technology that rapidly compresses slowly stored energy and releases it to the load in the form of pulses. With the development of nuclear physics, electron beam accelerator physics, laser and plasma physics research, pulsed power technology has developed rapidly and has become one of the most active cutting-edge technologies in the world. It has broad application prospects in military and civilian fields. , in the military field, it is used in nuclear fusion technology, fuze systems for national defense and military defense, etc.; in the civilian field, it is used in food processing, medical treatment, waste water treatment, waste gas treatment, ozone preparation, generator ignition, ion implantation, material processing, etc. (Yu Mingwei. LCC resonant pulse current source design [D]. Harbin Institute of Technology, 2015.)

With the expansion of the pulse application field, the pulse power switch plays an important role as the key device of the pulse power supply. At present, commonly used semiconductor pulse power switches include power MOSFET, thyristor (SCR), insulated gate bipolar transistor (IGBT), MOS controlled thyristor (MCT) and the newly developed cathode short-circuit gated thyristor (CS-MCT). The above semiconductor pulse power switches have their own advantages and disadvantages. Among them, there is a conductance modulation effect inside the bipolar power device, which makes it have a smaller conduction power consumption than the conventional unipolar device, but the conductance modulation degree of different types of bipolar devices is different. Among them, due to the positive feedback effect of NPN tube and PNP tube inside the thyristor, its conductance modulation degree is higher, and the conduction power consumption is smaller. However, due to the current concentration effect during the turn-on process, the di/dt capability of the thyristor is poor. In addition, the thyristor is a current-controlled device, and its driving circuit is more complicated than that of a voltage-controlled device. IGBTs are mainly used in high-frequency medium pulse power supplies. IGBTs are voltage-controlled devices and are relatively simple to drive. However, the degree of conductance modulation of IGBTs is limited by the drift region and the reverse-biased PN junction in the P-type base region, resulting in the turn-on power consumption of the device. In addition, the conduction of the IGBT is controlled by the gate voltage, and the maximum current is also limited by the saturation current. Gate - controlled thyristor (MOS- Controlled T hyristor , MCT) has low resistance characteristics similar to thyristor, and also has high di/dt capability and voltage control characteristics, but the device requires gate control signals of different signs during the switching process. , resulting in a more complex drive circuit (Temple VA K.MOS controlled thyristors (MCT's) [C]. Electron Devices Meeting, 1984 International. IEEE, 1984: 282-285.). The CS-MCT solves the above contradiction and belongs to a voltage-controlled device. It has a thyristor structure with a short-circuited cathode inside, so that it has a small on-resistance and a large di/dt capability and can also be zero-biased at the gate. It realizes the blocking of the device at the same time, which greatly simplifies the gate drive circuit; when its working mode is triggered by the initial IGBT mode to trigger the latch to enter the thyristor mode, the conduction is not controlled by the gate voltage, not limited by the saturation current, and can be more The current level is greatly improved; at the same time, the current concentration phenomenon at the cathode contact hole is alleviated, and the lattice temperature is effectively reduced (Chen W, et al. Experimentally demonstrate a cathode short MOS-controlled thyristor (CS-MCT) for single orrepetitive pulse applications [C]. ISPSD, 201628th International Symposiumon. IEEE, 2016:311-314.).

SUMMARY OF THE INVENTION

Aiming at the above CS-MCT structure, the present invention proposes a number of new MOS gate-controlled thyristor structures integrating Schottky diodes, which are named SD-MCT. By designing the cathode of the device as a Schottky contact, a Schottky diode is formed between the P-well region and the cathode. This structure can make the current distribution of the device more uniform and reduce the minimum current required for device latch-up. The pulse peak current of the device is further increased at a small current, the current rise rate (di/dt) is increased, the time for the device to work in the IGBT mode is shortened, and the lattice temperature of the device in the IGBT mode at the initial stage of the pulse discharge is effectively reduced. the pulse characteristics of the device.

The technical scheme of the present invention is as follows:

The first type of MOS gated thyristor integrated with Schottky diodes, its cell structure includes an anode 1, a P+ anode region 2 and a drift region 3 stacked in sequence from bottom to top; the upper layer of the drift region 3 has a P well region 4 , there are 2 N well regions 5 symmetrically arranged along the vertical centerline of the device on the upper layer of the P well region 4 and a P ^{+ region 6 located on the upper layer of the N well region 5, and the P + region} 6 is close to the gate of the device; on the upper surface of the drift region 3 Both ends also have a gate oxide layer 7, the gate oxide layer 7 also extends along the upper surface of the P well region 4 to cover part of the N well region 5 and the upper surface of the P+ region 6; the gate oxide layer 7 has a polysilicon gate 8 , the gate oxide layer 7 and the polysilicon gate 8 on both sides are symmetrically distributed along the vertical center line of the device; the surface of the device between the gate oxide layers 7 on both sides is covered with a Schottky contact cathode metal 9, and the polysilicon gate 8 The upper surface of the cathode metal 9 is filled with an isolation medium for isolation.

Further, by setting the doping concentration of the P well region 4 , a Schottky diode is formed between the P well region 4 and the cathode 9 .

In the above scheme, the P ⁺ region 6 will speed up the extraction of carriers during turn-off, but it will not affect the pulse performance of the device, and whether to retain the P ⁺ region 6 can be selected according to requirements during fabrication. If the P ⁺ region 6 is removed, it is the second type of MOS gated thyristor integrated with Schottky diodes.

Further, the gate structure may be a planar gate or a trench gate.

The beneficial effect of the present invention is that, compared with the existing CS-MCT structure, the current distribution of the device can be made more uniform during operation, thereby reducing the minimum current required for the device to latch up, shortening the time that the device works in the IGBT mode, and making the device work in the IGBT mode. Faster latch into thyristor mode, enhance conductance modulation effect, reduce device on-resistance, improve current rise rate (di/dt), further increase the pulse peak current of the device at small currents, and reduce the maximum crystal value of the device during pulse discharge. The temperature of the grid is improved, and the pulse characteristics of the device are comprehensively improved.

Description of drawings

1 is a schematic diagram of the two-dimensional structure of an existing CS-MCT;

Fig. 2 is the equivalent circuit diagram of the existing CS-MCT;

3 is a schematic diagram of the two-dimensional structure of the first SD-MCT proposed by the present invention;

4 is an equivalent circuit diagram of the first SD-MCT proposed by the present invention;

Fig. 5 is the two-dimensional structure schematic diagram of the second SD-MCT proposed by the present invention;

6 is an equivalent circuit diagram of the second SD-MCT proposed by the present invention;

Fig. 7 is the structural representation after preparing N-drift region in the manufacturing process flow of the present invention;

8 is a schematic view of the structure after the gate oxide layer is formed in the manufacturing process flow of the present invention;

9 is a schematic structural diagram of depositing a layer of polysilicon/metal on the gate oxide layer and then etching to form a gate electrode in the manufacturing process flow of the present invention;

10 is a schematic structural diagram of forming a P-well region by ion implantation of P-type impurities and pushing junctions in the manufacturing process flow of the present invention;

11 is a schematic structural diagram of an N-well region formed by ion-implanting N-type impurities and pushing junctions in the manufacturing process flow of the present invention;

12 is a schematic structural diagram of forming a P ⁺ region by ion implantation of P-type impurities and pushing junctions in the manufacturing process flow of the present invention;

13 is a schematic structural diagram of the front-side deposition of the BPSG insulating dielectric layer and the etching of the contact holes in the manufacturing process flow of the present invention;

14 is a schematic structural diagram after front metallization in the manufacturing process flow of the present invention;

15 is a schematic structural diagram of a P-type impurity implantation to form an anode region after the back surface is thinned in the manufacturing process flow of the present invention;

16 is a schematic structural diagram of the backside metallization in the manufacturing process flow of the present invention;

17 is a schematic diagram of a hole current vector distribution and a hole density distribution diagram of the second SD-MCT device proposed by the present invention after latching (current density is 600A/cm ² );

FIG. 18 is a schematic diagram of a hole current vector distribution and a hole density distribution diagram of the existing CS-MCT device after latching (current density is 600A/cm ² );

19 is a comparison of the hole concentration distribution at the PN junction of the N well region and the P well region when the current density of the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure is 600A/cm ² picture;

20 is a simulation comparison diagram of the latch trigger current J _tr of the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure under different cell widths;

FIG. 21 is a simulation comparison diagram of anode current during pulse discharge under small current between the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure;

FIG. 22 is a simulation comparison diagram of the maximum lattice temperature of the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure during pulse discharge at a small current.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings

As shown in FIG. 1 , it is a schematic diagram of the cell structure of the existing CS-MCT device, and its equivalent circuit diagram is shown in FIG. 2 . In the present invention, the cathode in the existing CS-MCT structure is made into Schottky contact, the schematic diagram of the cell structure is shown in FIG. 3 , and the equivalent circuit diagram is shown in FIG. 4 . Compared with the equivalent circuit of the CS-MCT structure (see Figure 2), the first SD-MCT removes the P ⁺ doping at the contact hole on the basis of the existing CS-MCT, so that the P well region and the cathode are A Schottky contact is formed between them, that is, a Schottky diode is integrated between the P-well region and the cathode. The working principle of this structure is:

A forward bias is applied to the anode, and holes are injected into the drift region from the anode. As the gate voltage increases, when the gate voltage reaches the threshold voltage, the ON-FET is turned on, and electrons flow into the drift region from the cathode, reducing the drift region. At this stage, the device works in IGBT mode; because the P-well region is wide and the concentration is not very high, its equivalent resistance is large , the flow of holes through the P-well region will generate a voltage drop in the P-well region. In theory, when this voltage drop exceeds the turn-on voltage of the PN junction between the P-well region and the N-well region by 0.7V, the P-well region will be The thyristor is turned on, and the device works in the thyristor mode, the conductance modulation effect is enhanced, and the on-resistance of the device is effectively reduced. In the present invention, the cathode is made into Schottky contact. Since the cathode material is aluminum, the doping concentration of the N well region is in the order of 1E20, the work function of aluminum is greater than that of the N well region, and electrons flow from the metal to the N well region. A negative space charge region is formed on the surface of the N-well region. The direction of the electric field is directed from the surface to the body, causing a potential difference between the surface and the body. The energy band on the surface of the N-well region is bent downward. The electron concentration here is much larger than that in the body, forming a high conductance. The anti-barrier layer, that is, the formation of ohmic contact; and the doping concentration of the P well region is in the order of 1E17, the work function of aluminum is smaller than the work function of the semiconductor in the P well region, so the surface energy band of the P well region is bent downward, resulting in empty space. The potential barrier of the hole forms a P-type barrier layer, that is, a Schottky diode is formed between the P well region and the cathode metal. The Schottky diode has a turn-on voltage drop of about 0.3V, so only holes are required. The current flows through the P-well region to form a voltage drop of about 0.4V, which can open the PN junction between the P-well region and the N-well region, which greatly reduces the current required for the device to enter the thyristor mode and effectively shortens the device operation. time in IGBT mode.

FIG. 5 shows the second SD-MCT, that is, the P ⁺ region 6 is removed on the basis of the first SD-MCT, and the equivalent circuit diagram is shown in FIG. 6 . Its working principle is basically the same as that of the first SD-MCT, except that the carrier extraction is slightly slower when the device is turned off, but it does not affect the pulse performance of the device.

Taking the cell structure of the first SD-MCT shown in Figure 3 as an example, the fabrication steps are as follows:

Step 1: Select a silicon wafer with suitable resistivity as the substrate to form an N-type drift region 3, as shown in Figure 7;

The second step: forming a gate oxide layer 7 on the upper surface of the N-type drift region 3 by thermal oxidation, as shown in FIG. 8 ;

The third step: deposit polysilicon 8 on the upper surface of the gate oxide layer 7, and etch away excess polysilicon and gate oxide layer according to the polysilicon mask to form a gate electrode, as shown in Figure 9;

The fourth step: implanting P-type impurities in the upper layer of the N-type drift region 3, and using the self-alignment process of the polysilicon gate to form the P-well region 4, as shown in FIG. 10;

The fifth step: inject N-type impurities into the upper layer of the N-type drift region 3, and use the self-alignment process of the polysilicon gate and the mask of the N-well region to form the N-well region 5; the N-well region 5 is located in the P-well region 4, As shown in Figure 11;

Further, the left and right N-well regions can be pulled through to form a part of the N-well region that is combined into one, and a part of the N-well region that is separated from the left and right. By adjusting the ratio between the two, it can ensure that the withstand voltage does not decrease;

Step 6: Implant P-type impurities in the upper layer of the N-type drift region 3, and use the self-alignment process of the polysilicon gate and the mask of the Pdeep region to form a P ⁺ region 6; the P ⁺ region 6 is located in the N well region 5, such as As shown in Figure 12;

Further, in the preparation step of the second SD-MCT, step 6 is omitted;

Step 7: deposit a BPSG insulating dielectric layer on the upper surface of the device, and etch the contact holes, as shown in Figure 13;

The eighth step: depositing metal on the upper surface of the device to form cathodes 9 respectively; as shown in Figure 14;

The ninth step: deposit passivation layer;

The tenth step: thinning and polishing the lower surface of the N-type semiconductor drift region 3, implanting P-type impurities and performing ion activation to form a P ⁺ anode region 2, as shown in FIG. 15;

The eleventh step: back gold, deposit metal on the bottom of P ⁺ anode 2 to form anode 1, as shown in Figure 16.

Example:

Taking the cell width of 50 μm as an example, Figure 17 and Figure 18 show the hole current when the current density is 600A/cm ² after latching the second SD-MCT device of the present invention and the existing CS-MCT device respectively. Schematic diagram of vector distribution and distribution of hole density. Among them, the direction of the arrow represents the movement direction of the hole current. It can be seen from the comparison that the unlatched part of SD-MCT is significantly smaller than the unlatched part of CS-MCT, so the SD-MCT device of the present invention has a more uniform current distribution, and under the same current density, it enters the thyristor mode The area is significantly larger than that of CS-MCT, which alleviates the current concentration effect.

19 is a comparison of the hole concentration distribution at the PN junction of the N well region and the P well region when the current density of the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure is 600A/cm ² picture. It is further proved that the hole distribution of the SD-MCT device of the present invention is more uniform, and the conduction area into the thyristor mode is also larger. The MCT structure also alleviates the current concentration effect here.

FIG. 20 is a simulation comparison diagram of the latch trigger current J _tr of the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure under different cell widths. It can be seen that under different cell widths, the J _tr of SD-MCT is smaller than that of CS-MCT, and the _effect of cell width is relatively small.

The main application of the SD-MCT device of the present invention is in the pulse field. Figures 21 and 22 respectively show the anode of the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure under pulse discharge at a small current Simulation comparison plot of current and maximum lattice temperature. The simulation shows that the peak current is increased by 6.89%, the current rise rate (di/dt) is increased by 16.97%, the time of the device in IGBT mode is shortened by 80%, and the pulse discharge response is faster, which also makes the device work in IGBT mode The calorific value is greatly reduced in the discharge process, resulting in a 25.64% decrease in the lattice temperature during discharge.

It should be noted that the core invention of the present invention is to propose two MOS gated thyristors (SD-MCTs) integrated with Schottky diodes, and briefly describe the fabrication steps thereof. The simulation results cited in the specification are only to illustrate the advantages of the present invention more specifically, and do not mean that the optimal value has been reached. Those skilled in the art can obtain better results by optimizing the parameters of the present invention. The preparation process of the present invention is a process performed after the overall structure of the device is completed, and there are many variations and various forming processes. The present invention is neither possible nor necessary to step by step, but those skilled in the art should understand that various layout or process changes made on the basis of the present invention are all within the scope of protection of the present invention. .

Claims (2)

1. A MOS-gated thyristor integrated with Schottky diode has a cell structure including a bottom gateAn anode (1) and a P sequentially laminated on the anode⁺An anode region (2) and a drift region (3); the upper layer of the drift region (3) is provided with a P well region (4), the upper layer of the P well region (4) is provided with 2N well regions (5) which are symmetrically arranged along the vertical centerline of the device and a P well region positioned on the upper layer of the N well region (5)⁺Region (6), and P⁺The region (6) is close to the device gate; the two ends of the upper surface of the drift region (3) are respectively provided with a gate oxide layer (7), and the gate oxide layers (7) extend to cover parts of the N well region (5) and the P well region (4) along the upper surface of the P well region (4)⁺The upper surface of the zone (6); the gate oxide layer (7) is provided with a polysilicon gate (8), and the gate oxide layer (7) and the polysilicon gate (8) on two sides are symmetrically distributed along the vertical central line of the device; the surface of the device between the gate oxide layers (7) on the two sides is covered with cathode metal (9) in Schottky contact, namely the Schottky contact is formed between the P well region (4) and the cathode metal (9) by setting the doping concentration of the P well region (4), a Schottky diode is formed, and an isolation medium is filled between the upper surface of the polysilicon gate (8) and the cathode metal (9) for isolation.

2. A manufacturing method of an MOS grid-controlled thyristor integrated with a Schottky diode is characterized by comprising the following steps:

the first step is as follows: selecting a silicon wafer as a substrate according to the required resistivity to form an N-type drift region (3);

the second step is that: forming a gate oxide layer (7) on the upper surface of the N-type drift region (3) through thermal oxidation;

the third step: depositing polycrystalline silicon (8) on the upper surface of the gate oxide layer (7), and etching off redundant polycrystalline silicon and the gate oxide layer according to a mask of the polycrystalline silicon to form a gate electrode;

the fourth step: injecting P-type impurities into the upper layer of the N-type drift region (3), and forming a P well region (4) by utilizing a self-alignment process of a polysilicon grid;

the fifth step: injecting N-type impurities into the upper layer of the N-type drift region (3), and forming 2N well regions (5) by utilizing a self-alignment process of a polysilicon gate and a mask of the N well regions; the N well regions (5) are positioned in the P well region (4), and the N well regions (5) on two sides are symmetrically distributed along the vertical central line of the device;

and a sixth step: p-type impurities are implanted into the upper layer of the N-type drift region (3) by utilizing the majorityForming P by self-alignment process of the crystalline silicon grid and mask of the Pdeep area⁺A zone (6); p⁺The region (6) is located in the N well region (5);

the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching a contact hole;

eighth step: depositing cathode metal (9) on the upper surface of the device to form a cathode, and setting the doping concentration of the P well region (4) to enable Schottky contact to be formed between the P well region (4) and the cathode metal (9) so as to form a Schottky diode;

the ninth step: depositing a passivation layer;

the tenth step: thinning and polishing the lower surface of the N-type semiconductor drift region (3), injecting P-type impurities and carrying out ion activation to form P⁺An anode region (2);

the eleventh step: back gold at P⁺And depositing metal at the bottom of the anode (2) to form the anode (1).

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